HV232X

HV232 SUTEX | Alldatasheet

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Technical content

Features

❏ HVCMOS ® technology for high performance ❏ Very low quiescent power dissipation – 10µA ❏ Output On-resistance typically 22 ohms ❏ Integrated bleed resistors on the outputs ❏ Low parasitic capacitances ❏ DC to 10MHz analog signal frequency ❏ -60dB typical output off isolation at 5MHz ❏ CMOS logic circuitry for low power ❏ Excellent noise immunity ❏ On-chip shift register, latch and clear logic circuitry ❏ Flexible high voltage supplies ❏ Surface mount package available General Description The Supertex HV232 is a low charge injection 8-channel high- voltage analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric trans- ducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. This IC is suitable for various combinations of high voltage supplies, e.g., V PP /VNN : +50V/–150V, or +100V/–100V. Absolute Maximum Ratings* VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage 220V VPP Positive high voltage supply -0.5V to V NN +200V VNN Negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V DD +0.3V Analog Signal Range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 °C to +150°C Power dissipation µ-BGA 1.0W 28-pin PLCC 1.2W 48 lead TQFP 1.0W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. HV232 VPP – VNN 200V HV232PJ HV232FG HV232GA HV232X

Ordering Information

28-lead plastic 48-lead TQFP µ-BGA Die chip carrier 10/31/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

Electrical Characteristics

DC Characteristics (over recommended operating conditions unless otherwise noted) 30 26 38 48 I SIG = 5mA V PP = 40V, 25 22 27 32 I SIG = 200mA V NN = -160V Small Signal Switch (ON) RONS 25 22 27 30 ohms I SIG = 5mA V PP = 100V, Resistance 18 18 24 27 I SIG = 200mA V NN = -100V 23 20 25 30 I SIG = 5mA V PP = 160V, 22 16 25 27 I SIG = 200mA V NN = -40V Small Signal Switch (ON)∆R ONS 20 5.0 20 20 % I SW = 5mA, VPP = 100V, Resistance Matching VNN = -100V Large Signal Switch (ON) RONL 15 ohms V SIG = VPP - 10V, ISIG = 1A Resistance Output Switch Shunt R INT 20 35 50 K Ω Output switch to RGND Resistance Switch Off Leakage I SOL 5.0 1.0 10 15 µAV SIG = VPP - 10V Per Switch DC Offset Switch Off 300 100 300 300 mV No Load DC Offset Switch On 500 100 500 500 mV No Load Pos. HV Supply Current I PPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON, ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON, ISW = 5mA Peak Current Output Switch Frequency fSW 50 KHz Duty Cycle = 50% 6.5 7.0 8.0 V PP = 40V, VNN = -160V IPP Supply Current I PP 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 160V, VNN = -40V 6.5 7.0 8.0 V PP = 40V, VNN = -160V INN Supply Current I NN 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 160V, VNN = -40V Logic Supply I DD 4.0 4.0 4.0 mA f CLK = 5MHz, VDD = 5.0V Average Current Logic Supply I DDQ 10 10 10 µA Quiescent Current Logic Input Capacitance CIN 10 10 10 pF 0°C +25°C +70°CCharacteristics Sym Units Test Conditionsmin max min typ max min max 50KHz Output Switching Frequency with no load HV232

AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) 0°C +25°C +70°C Characteristics Sym min max min typ max min max Units Test Conditions Set Up Time Before LE Rises tSD 150 150 150 ns Time Width of LE t WLE 150 150 150 ns Clock Delay Time to Data Out tDO 55 150 60 150 70 150 ns Time Width of CL t WCL 150 150 150 ns Set Up Time Data to Clock t SU 15 15 8.0 20 ns Hold Time Data from Clock t h 35 35 35 ns Clock Freq f CLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK /2 Clock Rise and Fall Times t r, tf 1.0 1.0 1.0 µs Turn On Time t ON 5.0 5.0 5.0 µsV SIG = VPP -10V, R L = 10KΩ Turn Off Time t OFF 5.0 5.0 5.0 µsV SIG = VPP -10V, R L = 10KΩ 20 20 20 V PP = 160V, VNN = -40V Maximum V SIG Slew Rate dv/dt 20 20 20 V/ns V PP = 100V, VNN = -100V 20 20 20 V PP = 40V, VNN = -160V Off Isolation KO -30 -30 -33 -30 dB f = 5MHz, 1KΩ//15pF load -58 -58 -58 dB f = 5MHz, 50Ω load Switch Crosstalk K CR -60 -60 -70 -60 dB f = 5MHz, 50Ω load Output Switch Isolation I ID 300 300 300 mA 300ns pulse width, Diode Current 2.0% duty cycle Off Capacitance SW to GND C SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND C SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz HV232

AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Symbol Parameter Value VDD Logic power supply voltage1, 3 4.5V to 13.2V VPP Positive high voltage supply1, 3 40V to VNN + 200V VNN Negative high voltage supply1, 3 -40V to -160V VIH High-level input voltage V DD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak to peak V NN +10V to VPP -10V2 TA Operating free air-temperature 0 °C to 70°C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2V SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD , VPP , and VNN should not be less than 1.0msec. Operating Conditions* VPP = 40V, VNN = -160V, RL = 50Ω VPP = 100V, VNN = -100V, RL = 50Ω VPP = 160V, VNN = -40V, RL = 50Ω 150 150 150 150 150 150 mVOutput Voltage Spike +25 °C UnitsCharacteristics Sym Test Conditions min typ max +V SPK -VSPK +V SPK -VSPK +V SPK -VSPK

/K53/K77/K69/K74/K63/K68 /K4F/K46/K46 /K4C/K65/K61/K6B/K61/K67/K65 /K49 /K53/K4F/K4C /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K50/K50 /KD0/K31/K30/K56 /K44/K43 /K4F/K66/K66/K73/K65/K74 /K4F/K4E/K2F/K4F/K46/K46 /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K4F/K55/K54 /K54 /K4F/K4E /K2F/K54 /K4F/K46/K46 /K54 /K65/K73/K74 /K43/K69/K72/K63/K75/K69/K74 /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K50/K50 /KD0/K31/K30/K56 /K52 /K4C /K31/K30/K4B Ω /K56 /K4F/K55/K54 /K49/K73/K6F/K6C/K61/K74/K69/K6F/K6E /K44/K69/K6F/K64/K65 /K43/K75/K72/K72/K65/K6E/K74 /K49 /K49/K44 /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K4E/K4E /K56 /K53/K49/K47 /K43/K72/K6F/K73/K73/K74/K61/K6C/K6B /K4B /K43/K52 /K3D /K32/K30/K4C/K6F/K67 /K56 /K4F/K55/K54 /K56 /K49/K4E /K56 /K49/K4E /K3D/K31 /K30/K56 /K50/KD0/K50 /K40/K35/K4D/K48/K7A /K4E/K43 /K35/K30 Ω /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K35/K30 Ω /K43/K68/K61/K72/K67/K65 /K49/K6E/K6A/K65/K63/K74/K69/K6F/K6E /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K53/K49/K47 /K56 /K4F/K55/K54 /K31/K30/K30/K30/K70/K46 /K51/K3D /K31/K30/K30/K30/K70/K46 /K78 ∆/K56 /K4F/K55/K54 ∆/K56 /K4F/K55/K54 /K4F/K75/K74/K70/K75/K74 /K56 /K6F/K6C/K74/K61/K67/K65 /K53/K70/K69/K6B/K65 /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K56 /K4F/K55/K54 /K31/K4B Ω /K52 /K4C /K35/K30 Ω /K2B/K56 /K53/K50/K4B /KD0/K56 /K53/K50/K4B /K4F/K46/K46 /K49/K73/K6F/K6C/K61/K74/K69/K6F/K6E /K4B /K4F /K3D /K32/K30/K4C/K6F/K67 /K56 /K4F/K55/K54 /K56 /K49/K4E /K56 /K49/K4E /K3D/K31 /K30/K56 /K50/KD0/K50 /K40/K35/K4D/K48/K7A /K56 /K50/K50 /K35/K56 /K56 /K4E/K4E /K56 /K50/K50 /K56 /K4E/K4E /K56 /K44/K44 /K47/K4E/K44 /K52 /K4C /K56 /K4F/K55/K54 /K4F/K70/K65/K6E /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 /K4F/K70/K65/K6E /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 /K52 /K47/K4E/K44 HV232

(TYP) V 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR D N – 1 D N D N + 1 50%50% 90% 10% Logic Timing Waveforms Block Diagram D LE CL LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL

8 BIT

Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→ H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LLL OFF HLL O N X XX XX XXX HL HOLD PREVIOUS STATE X XXXXXXX XH OFF OFF OFF OFF OFF OFF OFF OFF Truth Table HV232

Pin Configurations Package Outlines HV232 28 Pin J-Lead Pin Function Pin Function

1 SW3 15 N/C

2 SW3 16 D IN

3 SW2 17 CLK

4 SW2 18 LE

5 SW1 19 CL

6 SW1 20 D OUT

7 SW0 21 SW7

8 SW0 22 SW7

9 N/C 23 SW6

10 V PP 24 SW6

11 R GND 25 SW5

12 V NN 26 SW5

13 GND 27 SW4

1 SW5

2 N/C

3 SW4

4 N/C

5 SW4

6 N/C

7 N/C

8 SW3

9 N/C

10 SW3

11 N/C

12 SW2

13 N/C

14 SW2

15 N/C

16 SW1

17 N/C

18 SW1

19 N/C

20 SW0

21 N/C

22 SW0

23 N/C

Pin #1 Pin 1 top view 48-pin TQFP Pin 12 Pin Function

25 V NN

26 N/C

28 GND

30 N/C

31 N/C

32 N/C

34 CLK

36 CLR

38 N/C

39 SW7

40 N/C

41 SW7

42 N/C

43 SW6

44 N/C

45 SW6

46 N/C

47 SW5

48 N/C

A B C D E F G H 12 3 4 567 8 9 A B C D E F G H SIYYWW HV232GA AAAAAAA DA TUM AXIS "X" LOT # AXIS "Y" 2.675 5.350 ± 0.05 3.00 0.65 6.00 ± 0.05 0.65 0.325 DIE 4.09 A1 CORNER INDEX DIE 4.65 HV232 Polyimide Tape Adhesive Elastomer Seal

4 Sides/Edges

0.243 ± 0.03 0.99 ± 0.05 0.05 0.323 ± 0.03 ENLARGED VIEW Notes: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Do not subject part to ultrasonic cleaning or intense UV. 3. Contact ball position per JESD 95-1, SPP-010. 4. Units are in millimeters.

µ-BGA Function Table Ball Location Function A4 SW1 C3 SW2 C4 SW1 C5 SW0 C6 V PP C7 V NN D1 SW3 D3 SW3 D4 SW2 D5 SW0 D6 R GND D7 GND D9 V DD E1 SW4 E3 SW4 E4 SW5 E5 SW7 E6 LE E7 CLK E9 D IN F3 SW5 F4 SW6 F5 SW7 F6 D OUT F7 CLR H4 SW6 HV232

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TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 10/31/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.