HV230_07 SUTEX | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
Features
HVCMOS® technology for high performance Very low quiescent power dissipation – 10µA Output On-resistance typically 22Ω Integrated bleed resistors on the outputs Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5.0MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Block Diagram Low Charge Injection 8-Channel High Voltage Analog Switches with Bleed Resistors General Description The Supertex HV230 and HV232 are low charge injection 8- channel high-voltage analog switch integrated circuits(ICs) with bleed resistors. These devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. These ICs are suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +50V/–150V, or +100V/–100V. LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 VPP VNNVDD RGND DOUT DIN CLK 8-Bit Shift Register Latches Level Shifters Output Switches D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL
Ordering Information
Device 28-Lead PLCC 48-Lead LQFP/TQFP (1.4mm) 26-Lead BCC 26-Ball fpBGA HV230 - - - HV230GA HV230B1-G HV230GA-G HV232 HV232PJ HV232FG --HV232PJ-G HV232FG-G -G indicates the part is RoHS compliant (Green) Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 220V VPP positive high voltage supply -0.5V to V NN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 OC to +150OC Power dissipation: 28-Lead PLCC 48-Lead LQFP/TQFP(1.4mm) 26-Lead BCC 26-Ball fpBGA 1.2W 1.0W 1.0W 1.0W Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 1,3 4.5V to 13.2V VPP positive high voltage supply 1,3 40V to VNN +200V VNN negative high voltage supply 1,3 -40V to -160V VIH High level input voltage V DD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V2 TA Operating free air temperature 0 OC to 70OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up fi rst and powered down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
Electrical Characteristics
DC Characteristics (over recommended operating conditions unless otherwise noted) 30 26 38 48 I SIG = 5mA V PP = 40V, 25 22 27 32 I SIG = 200mA V NN = -160V Small Signal Switch (ON) R ONS 25 22 27 30 Ω ISIG = 5mA V PP = 100V, Resistance 18 18 24 27 I SIG = 200mA V NN = -100V 23 20 25 30 I SIG = 5mA V PP = 160V, 22 16 25 27 I SIG = 200mA V NN = -40V Small Signal Switch (ON) ∆RONS 20 5.0 20 20 % I SW = 5mA, VPP = 100V, Resistance Matching VNN = -100V Large Signal Switch (ON) R ONL 15 Ω VSIG = VPP - 10V, ISIG = 1A Resistance Output Switch Shunt R INT 20 35 50 KΩ Output switch to RGND Resistance IRINT = 0.5mA Switch Off Leakage I SOL 5.0 1.0 10 15 µA V SIG = VPP - 10V Per Switch DC Offset Switch Off 300 100 300 300 mV No Load DC Offset Switch On 500 100 500 500 mV No Load Pos. HV Supply Current I PPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current I NNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current I PPQ 10 50 µA ALL SWs ON, I SW = 5mA Neg. HV Supply Current I NNQ -10 -50 µA ALL SWs ON, I SW = 5mA Peak Current Output Switch Frequency f SW 50 KHz Duty Cycle = 50% 6.5 7.0 8.0 V PP = 40V, VNN = -160V IPP Supply Current I PP 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 160V, VNN = -40V 6.5 7.0 8.0 V PP = 40V, VNN = -160V INN Supply Current I NN 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 160V, VNN = -40V Logic Supply I DD 4.0 4.0 4.0 mA f CLK = 5MHz, VDD = 5.0V Average Current Logic Supply I DDQ 10 10 10 µA Quiescent Current Logic Input Capacitance C IN 10 10 10 pF 0°C +25°C +70°CCharacteristics Sym Units Test Conditionsmin max min typ* max min max 50KHz Output Switching Frequency with no load *Typical values only for HV232
AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) 0°C +25°C +70°C Characteristics Sym min max min typ* max min max Units Test Condi tions Set Up Time Before LE Rises t SD 150 150 150 ns Time Width of LE t WLE 150 150 150 ns Clock Delay Time to Data Out t DO 55 150 60 150 70 150 ns Time Width of CL t WCL 150 150 150 ns Set Up Time Data to Clock t SU 15 15 8.0 20 ns Hold Time Data from Clock t h 35 35 35 ns Clock Freq f CLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK/2 Clock Rise and Fall Times t r, tf 1.0 1.0 1.0 µs Turn On Time t ON 5.0 5.0 5.0 µs V SIG = VPP -10V, RL = 10KΩ Turn Off Time t OFF 5.0 5.0 5.0 µs V SIG = VPP -10V, RL = 10KΩ 20 20 20 V PP = 160V, VNN = -40V Maximum VSIG Slew Rate dv/dt 20 20 20 V/ns V PP = 100V, VNN = -100V 20 20 20 V PP = 40V, VNN = -160V Off Isolation KO -30 -30 -33 -30 dB f = 5MHz, 1KΩ//15pF load -58 -58 -58 dB f = 5MHz, 50Ω load Switch Crosstalk K CR -60 -60 -70 -60 dB f = 5MHz, 50Ω load Output Switch Isolation I ID 300 300 300 mA 300ns pulse width, Diode Current 2.0% duty cycle Off Capacitance SW to GND C SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND C SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) VPP = 40V, VNN = -160V, RL = 50Ω VPP = 100V, VNN = -100V, RL = 50Ω VPP = 160V, VNN = -40V, RL = 50Ω 150 150 150 150 150 150 mVOutput Voltage Spike +25°C UnitsCharacteristics Sym Test Conditions min typ* max +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK *Typical values only for HV232 *Typical values only for HV232
D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N LL L O F F HL L O N L L L OFF HL L O N L L L OFF HL L O N LL L O F F HL L O N L L L OFF HLL O N X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF Truth Table Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. D OUT is high when data in shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. DATA IN CLOCK DATA OUT DN + 1 N N - 1DD 50% 50% 50% 50% 50% 50%50% 50% 50% OUT (TYP) V OFF ON CLR t WCL 90% 10% t OFF DD SD ON t tt t t h WLE SU t LE Logic Timing Waveforms
VPP –10V DC Offset ON/OFF VPP 5V VNN VPP VNN VDD GND VOUT TON/TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP –10V RL 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20Log VOUT VIN VIN = 10 VP–P @5MHz NC 50Ω VPP VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x ∆VOUT ∆VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ RL 50Ω +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP–P @5MHz VPP VNN VPP VNN VDD GND RL VOUT Open RGND RGND Open RGND RGND RGND RGND RGND RGND
1 SW5 25 V NN
2 N/C 26 N/C
4 N/C 28 GND
6 N/C 30 N/C
7 N/C 31 N/C
8 SW3 32 N/C
9 N/C 33 D
10 SW3 34 CLK
11 N/C 35 LE
12 SW2 36 CLR
13 N/C 37 D
14 SW2 38 N/C
15 N/C 39 SW7
16 SW1 40 N/C
17 N/C 41 SW7
18 SW1 42 N/C
19 N/C 43 SW6
20 SW0 44 N/C
21 N/C 45 SW6
22 SW0 46 N/C
23 N/C 47 SW5
1 SW3 15 N/C
2 SW3 16 D IN
3 SW2 17 CLK
6 SW1 20 D
7 SW0 21 SW7
8 SW0 22 SW7
9 N/C 23 SW6
11 R GND 25 SW5
12 V NN 26 SW5
13 GND 27 SW4
14 V DD 28 SW4
28-Lead (J-Lead) PLCC Package Outline (PJ) 48-Lead LQFP/TQFP (1.4mm) Package Outline (FG) Linear dimensions in millimeters. Angular dimensions in degrees Pin 1 identifier located within the area indicated Corner shape may differ from drawing.. 0.22 ± 0.05
0.50 BSC
9.00 ± 0.20 7.00 ± 0.20 9.00 ± 0.20 7.00 ± 0.20 1.60 max 0.45 - 0.750.05 - 0.15 0O - 7O 1.75 nom 1.75 nom 1 Side View Top View (4 places) B.C. of Bend Radii 0.480 ± 0.010 (12.192 ± 0.254) 0.050 ± 0.010 (1.270 ± 0.254) 0.450 ± 0.005 (11.430 ± 0.127) 0.027 ± 0.003 (0.6858 ± 0.0762) 0.1725 ± 0.0075 (4.3815 ± 0.1905) min.0.020 (0.508) 0.410 ± 0.010 (10.414 ± 0.254) 0.110 ± 0.010 (2.794 ± 0.254) Dimensions in Inches (Dimensions in Millimeters) Measurement Legend =
Pin Confi guration26-Ball fpBGA Package Outline (GA) Ball Location Function A4 SW1 C3 SW2 C4 SW1 C5 SW0 C6 V PP C7 V NN D1 SW3 D3 SW3 D4 SW2 D5 SW0 D6 R GND D7 GND D9 V DD E1 SW4 E3 SW4 E4 SW5 E5 SW7 E6 LE E7 CLK E9 D IN F3 SW5 F4 SW6 F5 SW7 F6 D OUT F7 CLR H4 SW6 Top View Bottom View Enlarged Side View 0.80±0.05 1.0±0.10 0.20±0.05 Φ0.33±0.050.65 0.65 1.70 1.70 2.68 5.35±0.10 6.00±0.10 A1 Indicator
3.00 A1 Indicator
Note: All dimensions are in millimeters
Doc.# DSFP-HV230_HV232 A111006 HV230/HV232 (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Pin Description Pin Function
1 SW4
11 V NN
12 R GND
13 GND
15 D IN
16 CLK
18 CLR
20 SW7
21 SW7
22 SW6
23 SW6
24 SW5
25 SW5
26 SW4
26-Lead BCC Package Outline (B1) Top View Pad connections are on the backside of the package. Pin 1 Pin 2 4.15 6.00±0. 0.925 0.925 4.55 0.389 0.35±0.10 1.06 0.725 0.65 0.725 0.35±0.10 0.40 1.05 6.00±0.10 0.8mm Max 0.075±0.025 (Standoff ) Side View 0.10