HV2301 SUTEX | Alldatasheet
Document overview
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Technical content
Features
HVCMOS technology for high performance Integrated bleed resistors on the outputs
8 Channels of high voltage analog switch
3.3V or 5V CMOS input logic level 20MHz data shift clock frequency Very low quiescent power dissipation-10µA Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages
Applications
Medical ultrasound imaging NDT metal fl aw detection Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules General Description The Supertex HV2301 is a low charge injection, 8-channel, high voltage analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching, controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. The built-in bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. The HV2301 is an enhanced version of the HV232. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feed- through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram D LE CL SW0 D LE CL D LE CL D LE CL D LE CL LATCHES LEVEL SHIFTERS OUTPUT SWITCHES VNN VPPLE CLRVDD GND SW1 SW2 SW6 SW7 RGND CLK DIN DOUT 8-Bit Shift Register
Ordering Information
48-Lead TQFP 28-Lead PLCC 32-Lead BCC HV2301 HV2301FG-G HV2301PJ-G HV2301B1-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +7V VPP-VNN differential supply 220V VPP positive supply -0.5V to V NN+200V VNN negative supply +0.5V to -200V Logic input voltage -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation: 48-Lead TQFP 28-Lead PLCC 32-Lead BCC 1.0W 1.2W 1.0W Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP positive high voltage supply 40V to V NN +200V VNN negative high voltage supply -40V to -160V VIH High level input voltage 0.9V to V DD VIL Low-level input voltage 0V to 0.1V VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V TA Operating free air temperature 0 OC to 70OC Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up fi rst and powered down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
(Over operating conditions unless otherwise specifi ed ) RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω ISIG = 5mA VPP = +40V VNN = -160V-2 5-2 2 2 7-3 2 I SIG = 200mA -2 5-2 2 2 7-3 0 I SIG = 5mA VPP = +100V VNN = -100V- 18 - 18 24 - 27 I SIG = 200mA - 23 - 20 25 - 30 I SIG = 5mA VPP = +160V VNN = -40V-2 2-1 6 2 5-2 7 I SIG = 200mA ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5mA, VPP = +100V, VNN = - 100V RONL Large signal switch on-resistance --- 1 5 --- Ω V SIG = VPP -10V, ISIG = 1A RINT Value of output bleed resistance - - 20 35 50 - - KΩ Output switch to RGND IRINT = 0.5mA ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA V SIG = VPP -10V, VNN +10V VOS DC offset switch off - 300 - 100 300 - 300 mV No load DC offset switch on - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, I SW = 5mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches on, I SW = 5mA fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current mA VPP = +40V VNN = -160V All output switches are turning On and Off at 50kHz with no load PP = +100V VNN = -100V VNN = -40V INN Average VNN supply curent mA VPP = +40V VNN = -160V VNN = -100V VNN = -40V IDD Average VDD supply cur- rent -4 . 0- -4 . 0-4 . 0 m A f CLK = 5MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- Sym Parameter 0OC+ 2 5 OC+ 7 0 OC Units Conditions Min Max Min Typ Max Min Max
(Over recommended operating conditions: VDD = 5.0V, tR = tF ≤5ns, 50% duty cycle, CLOAD = 20pF unless otherwise specifi ed) tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - V DD = 5.0V tDO Clock delay time to data out -1 2 0- 9 5 1 4 0-1 6 7 ns VDD = 3.0V - 58 - 40 69 - 85 V DD = 5.0V tWCL Time width of CL 55 - 55 30 - 55 - ns --- tSU Set up time data to clock 39 - 47 30 - 58 - ns VDD = 3.0V 16 - 21 10 - 26 - V DD = 5.0V tH Hold time data from clock 2 - 2 - - 2 - ns V DD = 3.0 or 5.0V fCLK Clock frequency - TBD - - 7.5 - TBD MHz VDD = 3.0V - 20 - - 20 - 20 V DD = 5.0V tR, tF Clock rise and fall times - 50 - 50 - 50 ns --- tON Turn on time - 5.0 - - 5.0 - 5.0 μs V SIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time - 5.0 - - 5.0 - 5.0 μs V SIG = VPP -10V, RLOAD = 10kΩ dv/dt Maximun V SIG slew rate -2 0- -2 0-2 0 V/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 V PP = +100V, VNN = -100V - 20 - - 20 - 20 V PP = +160V, VNN = -40V KO Off isolation dB f = 5.0MHz, 1kΩ/15pF load -58 - -58 - - -58 - f = 5.0MHz, 50Ω load KCR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK Output voltage spike ---- 1 5 0 -- mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK ---- 1 5 0 -- +VSPK ---- 1 5 0 -- VPP = +100V, VNN = -100V, RLOAD = 50Ω-VSPK ---- 1 5 0 -- +VSPK ---- 1 5 0 -- VPP = +160V, VNN = -40V, RLOAD = 50Ω-VSPK ---- 1 5 0 -- QC Charge injection - - - 820 - - - pC VPP = +40V, VNN = -160V, VSIG = 0V VSIG = 0V VSIG = 0V Sym Parameter 0OC+ 2 5 OC+ 7 0 OC Units Conditions Min Max Min Typ Max Min Max
D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HLL O n X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data fl ow through the latch. 4. D OUT is high when data in the register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.
(TYP) V 50% 50% 50%50% t WLE t SD t SU t h 50%50% t OFF 50% t DO t ON t WC L CLR D N–1 D N D N+1 50%50% 90% 10%
48-Lead TQFP (1.4mm) Package Outline (FG) Pin Confi guration 28-Lead PLCC Package Outline (PJ) Pin Confi guration Pin #1 B.C. of Bend Radii 0.480 ± 0.010 (12.192 ± 0.254) 0.050 ± 0.010 (1.270 ± 0.254) 0.450 ± 0.005 (11.430 ± 0.127) 0.027 ± 0.003 (0.686 ± 0.076) 0.173 ± 0.0075 (4.382 ± 0.191) min.0.020 (0.508) 0.410 ± 0.010 (10.414 ± 0.254) 0.110 ± 0.010 (2.794 ± 0.254) Dimensions in Inches (Dimensions in Millimeters) Measurement Legend = BSC 0.354 ± 0.01 (8.992 ± 0.254) 0.275 ± 0.004 (6.985 ± 0.102) 0.008 ± 0.003 (0.2032 ± 0.0762) 0.020 (0.508) 0.055 ± 0.004 (1.397 ± 0.102) 0.039 (0.991) 0.059 ± 0.004 (1.498 ± 0.102) 0.354 ± 0.01 (8.992 ± 0.254) 0.024 ± 0.008 (0.610 ± 0.203) 0.275 ± 0.004 (6.985 ± 0.102) Measurement Legend = Dimensions in Inches (Dimensions in Millimeters) 0° − 7° Pin 1 Pin # Pin Name Pin # Pin Name
1 SW5 25 V NN
3 SW4 27 RGND
5 SW4 29 V
7 N C3 1N C
8 SW3 32 NC
10 SW3 34 CLK
11 NC 35 LE
12 SW2 36 CLR
13 NC 37 D
14 SW2 38 NC
15 NC 39 SW7
16 SW1 40 NC
17 NC 41 SW7
18 SW1 42 NC
19 NC 43 SW6
20 SW0 44 NC
21 NC 45 SW6
22 SW0 46 NC
23 NC 47 SW5
Pin # Pin Name Pin # Pin Name
1 SW3 15 NC
2 SW3 16 D IN
3 SW2 17 CLK
4 SW2 18 LE
5 SW1 19 CLR
6 SW1 20 D
7 SW0 21 SW7
8 SW0 22 SW7
9 NC 23 SW6
11 RGND 25 SW5
12 V NN 26 SW5
13 GND 27 SW4
14 V DD 28 SW4
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com ©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in s uch applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and spe cifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com. Doc.# DSFP - HV2301 NR032106 HV2301 (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 32-Lead BCC Package Outline (B1) Pin Confi guration 3.90 DETAIL BDETAIL A DETAIL C 0.350±0.10 0.475±0.100 Pin 1 Indicator 0.10 0.10 0.10 0.10 0.65 0.7125 5.325 6.00±0.10 6.00±0.10 Top View Note: All dimensions are in mm and angles are in degrees 0.075±0.025 (Standoff ) 0.80 Max. Detail A Detail B Detail C 0.475±0.100 0.475±0.100 CF#0.15X45° 10 11 12 13 14 15 16 17 26272829303132 251 Pin # Pin Name Pin # Pin Name