HV2221

HV2221 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Low on-resistance, 14Ω max. HVCMOS technology for high performance 3.3 or 5.0V CMOS input logic level 20MHz data shift clock frequency Very low quiescent power dissipation - 10µA Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages

Applications

NDT metal fl aw detection Medical ultrasound imaging Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules General Description The Supertex HV2221 is a low charge injection, 8-channel, unipolar, negative high voltage, analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as NDT ultrasound fl aw detection, medical ultrasound imaging, piezoelectric transducer drivers, and printers. Data is input into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. Block Diagram Low Charge Injection, 8-Channel, Unipolar, Negative High Voltage, Analog Switch D LE CLR SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW6 D LE CLR SW7 CLK 8-BIT SHIFT REGISTERDIN DOUT LATCHES LEVEL SHIFTERS OUTPUT SWITCHES VNN VPPLE CLRVDD GND

Ordering Information

7x7mm body, 1.6mm height (max), 0.50mm pitch HV2221 HV2221FG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +7.0V VPP-VNN differential supply 260V VPP positive supply -0.5V to V NN+260V VNN negative supply +0.5V to -250V Logic input voltage -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 4.5A Storage temperature -65°C to 150°C Power dissipation 1.0W Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP - VNN Supply voltage differential 240V VPP Positive driver supply +15V to +50V VNN Negative high voltage supply -100V to -225V VIH High level input voltage 0.9V DD to VDD VIL Low-level input voltage 0V to 0.1V DD VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V TA Operating free air temperature 0 OC to 70OC Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2221FG LLLLLLLLL CCCCCCCC AAA 48-Lead LQFP (FG) Pin Confi guration 48-Lead LQFP (FG) (top view) Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up fi rst and powered-down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.

(Over operating conditions unless otherwise specifi ed ) RONS Small signal switch on-resistance ---- 1 4 -- Ω ISIG = 5.0mA VPP = +50V VNN = -190V---- 1 4 -- I SIG = 200mA ---- 1 5 -- I SIG = 5.0mA VPP = +40V VNN = -200V---- 1 5 -- I SIG = 200mA ---- 2 3 -- I SIG = 5.0mA VPP = +15V VNN = -225V---- 2 3 -- I SIG = 200mA ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +40V, VNN = -200V RONL Large signal switch on-resistance --- 9 . 2 --- Ω V SIG = 0V, ISIG = -1.0A ISOL Switch off-leakage per switch - 5.0 - 1.0 10 - 15 μA V SIG = VPP -10V, VNN +10V VOS(OFF) DC offset switch off - 300 - 100 300 - 300 mV 100KΩ load VOS(ON) DC offset switch on - 500 - 100 500 - 500 IDDQ Quiescent VDD supply current - - - - 50 - - μA All switches offIPPQ Quiescent VPP supply current - - - - 50 - - INNQ Quiescent VNN supply current - - - - -50 - - IDDQ Quiescent VDD supply current - - - 50 - - μA All switches on, I SW = 5.0mAIPPQ Quiescent VPP supply current - - - - 50 - - INNQ Quiescent VNN supply current - - - - -50 - - ISW Switch output peak current --- 4 . 5 --- A VSIG duty cycle < 0.1%, 1.0μs VPP = +50V VNN = -190V VNN = -200V VNN = -225V fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current - - - 5.6 7.5 - - mA VPP = +40V VNN = -200V 50kHz output switch- ing frequency with no load PP = +50V VNN = -190V VNN = -225V INN Average VNN supply current - - - 5.8 7.5 - - mA VPP = +40V VNN = -200V VNN = -190V VNN = -225V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- Sym Parameter 0OC+ 2 5 OC +70 OC Units Conditions Min Max Min Typ Max Min Max

Min Max Min Typ Max Min Max (Over recommended operating conditions: VDD = +5.0V, tR = tF ≤5.0ns, 50% duty cycle, VPP = +40V, VNN = -200V, CLOAD = 20pF, unless otherwise specifi ed) tSD Set up time before LE rises - - 25 ---- n s - - - tWLE Time width of LE --- 5 6 --- ns VDD = 3.0V tDO Clock delay time to data out --- 7 8 --- ns VDD = 3.0V tWCL Time width of CLR - - 55 ---- n s - - - tSU Set up time data to clock --- 2 1 --- ns VDD = 3.0V fCLK Clock frequency ---- 8 . 0 -- MHz VDD = 3.0V tR, tF Clock rise and fall times - 50 - - 50 - 50 ns --- tON Turn on time - 5.0 - - 5.0 - 5.0 μs VSIG = -100V, RLOAD = 10kΩ to GNDtOFF Turn off time - 5.0 - - 5.0 - 5.0 dv/dt Maximum V SIG slew rate -2 0- -2 0-2 0 V/ns VPP = +40V, VNN = -200V -2 0- -2 0-2 0 V PP = +50V, VNN = -190V -2 0- -2 0-2 0 V PP = +15V, VNN = -225V KO Off isolation dB f = 5.0MHz, VOFFSET = -15V, 1.0KΩ/15pF load -58 - -58 - - -58 - f = 5.0MHz, VOFFSET = -15V, 50Ω load KCR Switch crosstalk - - -60 ---- d B f = 5.0MHz, VOFFSET = -15V, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND - - - 18 - - - pF f = 1.0MHz, V OFFSET = -15V CSG(ON) On capacitance SW to GND - - - 70 - - - pF f = 1.0MHz, V OFFSET = -15V +VSPK Output voltage spike --- 5 9 --- mV VPP = +40V, VNN = -200V, RLOAD = 50Ω-VSPK --- 1 1 5 --- +VSPK --- 7 1 --- VPP = +50V, VNN = -190V, RLOAD = 50Ω-VSPK --- 1 1 5 --- +VSPK --- 5 6 --- VPP = +15V, VNN = -225V, RLOAD = 50Ω-VSPK --- 1 1 5 --- QC Charge injection --- 1 9 5 0 --- pC VPP = +40V, VNN = -200V, VSIG = 0V VSIG = 0V VSIG = 0V

D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 LL L O f f HL L O n LL L O f f HL L O n LL L O f f HL L O n LL L O f f HL L O n LL L O f f HL L O n LL L O f f HL L O n LL L O f f HL L O n LLL O f f HLL O n X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data fl ow through the latch. 4. D OUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DATA IN LE CLOCK DATA OU T OFF ON OUT (TYP) V 50% 50% 50%50% t WLE t SD t SU t h 50%50% t OFF 50% t DO t ON t WC L CLR D N–1 D N D N+1 50%50% 90% 10%

+10V RL100K -125V

Pin Confi guration - 48-Lead LQFP (FG) Pin # Pin Name Pin # Pin Name

1 SW5 25 VNN

5 SW4 29 VDD

10 SW3 34 CLK

11 NC 35 LE

12 SW2 36 CLR

13 NC 37 DOUT

14 SW2 38 NC

15 NC 39 SW7

16 SW1 40 NC

17 NC 41 SW7

18 SW1 42 NC

19 NC 43 SW6

20 SW0 44 NC

21 NC 45 SW6

22 SW0 46 NC

23 NC 47 SW5

24 VPP 48 NC

(The package drawing (s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2221 NR013108 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.6mm height (max.), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specifi ed in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale.

1 Seating

θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.