HV2201

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Document overview

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Technical content

Features

► HVCMOS technology for high performance ► 8 Channels of high voltage analog switch ► 3.3 or 5.0V CMOS input logic level ► 20MHz data shift clock frequency ► Very low quiescent power dissipation (-10µA) ► Low parasitic capacitance ► DC to 50MHz analog signal frequency ► -60dB typical off-isolation at 5.0MHz ► CMOS logic circuitry for low power ► Excellent noise immunity ► Cascadable serial data register with latches ► Flexible operating supply voltages

Applications

► Medical ultrasound imaging ► NDT metal flaw detection ► Piezoelectric transducer drivers ► Inkjet printer heads ► Optical MEMS modules General Description The Supertex HV2201 is a low charge injection, 8-channel, high voltage analog switch integrated circuit (IC). The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, and printers. The HV2201 is an enhanced version of the HV20220. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feed- through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/- 40V. Block Diagram SW0 SW1 SW2 SW6 D LE CL SW7 CLK DIN DOUT Latches Level Shifters Output Switches VNNLE CLRVDD GND VPP 8-Bit Shift Register D LE CL D LE CL D LE CL D LE CL Low Charge Injection, 8-Channel, Enhanced, High Voltage Analog Switch

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +7.0V VPP - VNN differential supply 220V VPP positive supply -0.5V to VNN+200V VNN negative supply +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation: 48-Lead LQFP 28-Lead PLCC 1.0W 1.2W Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply 40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input voltage 0.9VDD to VDD VIL Low-level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V TA Operating free air temperature 0OC to 70OC Notes: 1. Power up/down sequence is arbtrary except GND must be powered-up first and powered-down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies V DD, V PP, and V NN should not be less than 1.0msec. Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2201FG LLLLLLLLL CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV2201PJ LLLLLLLLLL CCCCCCCCCCC 48-Lead LQFP (FG) 28-Lead PLCC (PJ) Pin Configuration 1 28 4 26

Ordering Information

7.00x7.00mm body 1.60mm height (max) 0.50mm pitch 28-Lead PLCC .453x.453in body .180in height (max) .050in pitch HV2201 HV2201FG-G HV2201PJ-G -G indicates the part is RoHS compliant (Green) 28-Lead PLCC (PJ) (top view) 48-Lead LQFP (FG) (top view) Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com (Over operating conditions unless otherwise specified ) RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω ISIG = 5.0mA VPP = +40V VNN = -160V- 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 ISIG = 5.0mA VPP = +100V VNN = -100V- 18 - 18 24 - 27 ISIG = 200mA - 23 - 20 25 - 30 ISIG = 5.0mA VPP = +160V VNN = -40V- 22 - 16 25 - 27 ISIG = 200mA ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = - 100V RONL Large signal switch on-resistance - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V VOS DC offset switch off - 300 - 100 300 - 300 mV 100kΩ load DC offset switch on - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches on, ISW = 5.0mA fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% I PP Average VPP supply current mA VPP = +40V VNN = -160V All output switches are turning on and off at 50kHz with no load VNN = -100V VNN = -40V INN Average VNN supply curent mA VPP = +40V VNN = -160V All output switches are turning on and off at 50kHz with no load VNN = -100V VNN = -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- Sym Parameter 0OC +25OC +70OC Units Conditions Min Max Min Typ Max Min Max

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Sym Parameter 0OC +25OC +70OC Units Conditions Min Max Min Typ Max Min Max (Over recommended operating conditions: VDD = 5.0V, tR = tF ≤5ns, 50% duty cycle, CLOAD = 20pF, unless otherwise specified) tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - VDD = 5.0V tDO Clock delay time to data out - 120 - 95 140 - 167 ns VDD = 3.0V - 58 - 40 69 - 85 VDD = 5.0V tWCL Time width of CL 55 - 55 - - 55 - ns --- tSU Set up time data to clock 39 - 47 30 - 58 - ns VDD = 3.0V 16 - 21 10 - 26 - VDD = 5.0V tH Hold time data from clock 2 - 2 - - 2 - ns VDD = 3.0 or 5.0V fCLK Clock frequency - - - 8 - - - MHz VDD = 3.0V tR, tF Clock rise and fall times - 50 - 50 - 50 ns --- tON Turn on time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ dv/dt Maximun VSIG slew rate - 20 - - 20 - 20 V/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 VPP = +100V, VNN = -100V - 20 - - 20 - 20 VPP = +160V, VNN = -40V KO Off isolation dB f = 5.0MHz, 1.0kΩ/15pF load -58 - -58 - - -58 - f = 5.0MHz, 50Ω load KCR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle C SG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK Output voltage spike - - - - 150 - - mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +100V, VNN = -100V, RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +160V, VNN = -40V, RLOAD = 50Ω-VSPK - - - - 150 - - QC Charge injection - - - 820 - - - pC VPP = +40V, VNN = -160V, VSIG = 0V VSIG = 0V VSIG = 0V

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Test Circuits Switch OFF Leakage ISOL VPP -10V DC Offset ON/OFF VOUT TON/TOFF Test Circuit VPP -10V RL 10kΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20Log VOUT VIN VIN = 10VP–P @5.0MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VSIG VOUT 1000pF Q = 1000pF x ∆VOUT ∆VOUT Output Voltage Spike VOUT 1kΩ RL 50Ω +VSPK –VSPK OFF Isolation VPP 5V VNN VPP VNN VDD GND RL VOUT Open RL VIN = 10VP–P @5.0MHz VPP 5V VNN VPP VNN VDD GND VPP 5V VNN VPP VNN VDD GND VPP 5V VNN VPP VNN VDD GND VPP 5V VNN VPP VNN VDD GND VPP 5V VNN VPP VNN VDD GND KO = 20Log VOUT VIN 100kΩ

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Typical Waveforms DATA IN LE CLOCK DATA OUT (TYP) ON VOUT OFF 50% tWLE tSD tSU th tOFF tDO tON tWCL CLR LR DN+1 DN DN-1 50% 50% 50% 50% 50% 50% 90% 10% 50% 50%

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Pin Configuration 48-Lead LQFP - (FG) Pin # Pin Name Pin # Pin Name

1 SW5 25 VNN

2 NC 26 NC

3 SW4 27 NC

4 NC 28 GND

5 SW4 29 VDD

6 NC 30 NC

7 NC 31 NC

8 SW3 32 NC

9 NC 33 DIN

10 SW3 34 CLK

11 NC 35 LE

12 SW2 36 CLR

13 NC 37 DOUT

14 SW2 38 NC

15 NC 39 SW7

16 SW1 40 NC

17 NC 41 SW7

18 SW1 42 NC

19 NC 43 SW6

20 SW0 44 NC

21 NC 45 SW6

22 SW0 46 NC

23 NC 47 SW5

24 VPP 48 NC

28-Lead PLCC (PJ) Pin # Pin Name Pin # Pin Name

1 SW3 15 NC

2 SW3 16 DIN

3 SW2 17 CLK

4 SW2 18 LE

5 SW1 19 CLR

6 SW1 20 DOUT

7 SW0 21 SW7

8 SW0 22 SW7

9 NC 23 SW6

10 VPP 24 SW6

11 NC 25 SW5

12 VNN 26 SW5

13 GND 27 SW4

14 VDD 28 SW4

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Seating Plane Gauge Plane θ L View B View B Seating Plane Top View D E b e Side View A2 A Note 1 (Index Area D1/4 x E1/4) Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV2201 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2201 B040811 28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. .150 MAX .048/.042 x 45O .075 MAX 4 26 D E1 E Top View View A A A2 A1 Seating Plane e Note 1 (Index Area) .056/.042 x 45O Base Plane .020 MIN b View A Horizontal Side View Vertical Side View Note 2 .020max (3 Places) R Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.