HV219_07 SUTEX | Alldatasheet
Document overview
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Technical content
Features
HVCMOS® technology for high performance Very low quiescent power dissipation -10µA Output ON-resistance typically 11Ω Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Serial shift register logic control with latches Flexible operating supply voltages Surface mount packages
Applications
Medical ultrasound imaging Non-destructive evaluation Block Diagram Low Charge Injection 8-Channel High Voltage Analog Switch General Description The Supertex HV219 is a low switch resistance, low charge injection 8-channel 200V analog switch integrated circuit (IC) intended primarily for medical ultrasound imaging. The device can also be used for NDE, non-destructive evaluation applications. The HV219 is a lower switch resistance, 11Ω versus 22Ω, version of the Supertex HV20220 device. The lower switch resistance will help reduce insertion loss. It has the same pin confi guration as that of the Supertex HV20220PJ and the HV20220FG. The device is manufactured using Supertex’s HVCMOS ® (high voltage CMOS) technology with high voltage bilateral DMOS structures for the outputs and low voltage CMOS logic for the input control. The outputs are confi gured as eight independent single pole single throw 11Ω analog switches. The input logic is an 8-bit serial to parallel shift register followed by an 8-bit parallel latch. The switch states are determined by the data in the latch. Logic high will correspond to a closed switch and logic low as an opened switch. The HV219 is designed to operate on various combinations of high voltage supplies. For example the V PP and V NN supplies can be: +40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or uni- polar positive. SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 Latches Level Shifters Output Switches VDD GND LE CL DIN CLK DOUT 8-Bit Shift Register D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL VNN VPP
Ordering Information
Device 28-Lead PLCC 48-Lead LQFP (7x7x1.4mm) HV219 HV219PJ HV219FG HV219PJ-G HV219FG-G -G indicates the part is RoHS compliant (Green) Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 220V VPP positive high voltage supply -0.5V to V NN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 OC to +150OC Power dissipation: 28-Lead PLCC 48-Lead LQFP (7x7x1.4mm) 1.2W 1.0W Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 4.5V to 13.2V V PP Positive high voltage supply 40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input logic voltage VDD -1.5V to VDD VIL Low-level input logic voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V TA Operating free air temperature 0OC to 70OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 28-Lead (J) PLCC (PJ) (top view) 48-Lead LQFP (FG) (7x7x1.4mm) (top view) Pin Confi gurations Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking . Top Marking Bottom Marking YYWW HV219PJ LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV219FG LLLLLLLLL CCCCCCCC AAA 28-Lead PLCC (PJ) 48-Lead LQFP (FG)
Min Max Min Typ Max Min Max RONS Small signal switch On-resistance - 15 - 13 19 - 24 Ω ISIG = 5mA VPP = +40V VNN = - 160V-1 3-1 1 1 4-1 6 I SIG = 200mA -1 3-1 1 1 4-1 5 I SIG = 5mA VPP = +100V V NN = - 100V -9-9 1 2 - 1 4 I SIG = 200mA - 12 - 10 13 - 15 I SIG = 5mA VPP = +160V V NN = -40V- 11 - 8 13 - 14 I SIG = 200mA ΔRONS Small signal switch On-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5mA, VPP = +100V, VNN = -100V RONL Large signal switch On-resistance ---8---Ω V SIG = VPP - 10V, ISIG = 1A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 µA VSIG= VPP -10V & VNN +10V DC offset switch off - 300 - 100 300 - 300 mV R LOAD = 100KΩ DC offset switch on - 500 - 100 500 - 500 mV R LOAD = 100KΩ IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5mA fSW Output switch frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current mA VPP = +40V VNN = -160V All output switches are turning ON and OFF at 50kHz with no load VNN = -100V VNN = -40V INN Average VNN supply current mA VPP = +40V VNN = -160V VNN = -100V VNN = -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA f CLK = 5MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static CIN Large input capacitance - 10 - - 10 - 10 pF ---
Min Max Min Typ Max Min Max tSD Set-up time before LE rises 150 - 150 - - 150 - ns --- tWLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out - 150 - - 150 - 150 ns --- twCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set-up time data to clock 15 - 15 8.0 - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --- fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz 50% duty cycle, fDATA = fCLK/2 tr, tf Clock rise and fall times - 50 - - 50 - 50 ns --- TON Turn-on time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ TOFF Turn-off time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ dv/dt Maximum V SIG slew rate -2 0- -2 0-2 0 V/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 V PP = +100V, VNN = -100V - 20 - - 20 - 20 V PP = +160V, VNN = -40V KO Off isolation dB F = 5MHz, 1KΩ//15pF load -58 - -58 - - - - F = 5MHz, 50Ω load KCR Switch crosstalk - - -60 - - - - dB F = 5MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2% duty cycle CSG(OFF) Off capacitance SW to GND 14 25 14 20 25 14 25 pF 0V, f = 1MHz CSG(ON) On capacitance SW to GND 40 60 40 50 60 40 60 pF 0V, f = 1MHz +VSPK Output voltage spike ---- 1 5 0 -- mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK ---- 2 0 0 -- +VSPK ---- 1 5 0 -- VPP = +100V, VNN = -100V, RLOAD = 50Ω-VSPK ---- 2 0 0 -- +VSPK ---- 1 5 0 -- VPP = +160V, VNN = -40V, RLOAD = 50Ω-VSPK ---- 2 0 0 -- Q Charge injection - - - 1450 - - - pC VPP = +40V, VNN = -160V, VSIG = 0V VNN = -100V, VSIG = 0V VNN = -40V, VSIG = 0V
(TYP) V 50% 50% 50%50% t WLE t SD t SU t h 50%50% t OFF 50% t DO t ON t WCL CLR D N + 1 D N D N - 1 50%50% 90% 10% Logic Timing Waveforms Truth Table Data in 8-Bit Shift Register LE CL Output Switch State D0 D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N XXXXXXXX H L Hold Previous State XXXXXXXX X HO F F O F F O F F O F F O F F O F F O F F O F F Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition clock. 3. The switches go to a state retaining their present condition at the rising edge of the LE. 4. When LE is low, the shift register data fl ows through the latch. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The clear input overrides all other inputs.
100KΩ RL TON/TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP -10V RL 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20Log VOUT VIN VIN = 10 VP-P @5MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x VOUT VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ RL 50Ω +VSPK -VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP-P @5MHz VPP 5V VNN VPP VNN VDD GND RL VOUT
48-Lead LQFP (7x7x1.4mm) (FG) Pin Function
1 SW5
3 SW4
5 SW4
8 SW3
10 SW3
12 SW2
14 SW2
16 SW1
18 SW1
20 SW0
22 SW0
25 V NN
28 GND
29 V DD
34 CLK
36 CLR
37 D OUT
39 SW7
41 SW7
43 SW6
45 SW6
47 SW5
28-Lead (J-Lead) PLCC (PJ) Pin Function
1 SW3
2 SW3
3 SW2
4 SW2
5 SW1
6 SW1
7 SW0
8 SW0
12 V NN
13 GND
17 CLK
21 SW7
22 SW7
23 SW6
24 SW6
25 SW5
26 SW5
27 SW4
28 SW4
1) Power up/down sequence is arbitrary except GND must be powered up fi rst and powered down last. This applies for applications powering GND of the IC with different voltages. 2) V SIG must always be at or in between VPP and VNN or fl oating during power up/down transition. 3) Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b D D1 E E1 e Dimension (inches) .050 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.
0.150 MAX
.048/.042 x 45O
0.075 MAX
D E1 E Top View Side View View B A A2A1 Seating Plane e b Note 1 (Index Area) .056/.042 x 45O 0.20max
3 Places
.020 MIN
(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV219 NR050807 48-Lead LQFP (7x7x1.4mm) Package Outline (FG) Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.
1 Seating
θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.