HV214PJ-G

HV214_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS® technology for high performance Very low quiescent power dissipation -10µA Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies Surface mount packages

Applications

Medical ultrasound imaging Non-destructive evaluation Inkjet printer heads Optical MEMS modules Block Diagram 250V Low Charge Injection 8-Channel High Voltage Analog Switch General Description The Supertex HV214 is a low charge injection 8-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical MEMS modules. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-210V, +125V/-125V, +210V/-40V. SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 Latches Level Shifters Output Switches VDD LE CL DIN CLK DOUT 8-Bit Shift Register D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL VNN VPP

Ordering Information

Device 28-Lead PLCC 48-Lead LQFP/ TQFP(1.4mm) HV214 HV214PJ HV214FG HV214PJ-G HV214FG-G -G indicates the part is RoHS compliant (Green) Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 260V VPP positive high voltage supply -0.5V to V NN +250V VNN negative high voltage supply +0.5V to -260V Logic input voltages -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 2.5A Storage temperature -65 OC to +150OC Power dissipation: 28-Lead PLCC 48-Lead LQFP/ TQFP (1.4mm) 1.2W 1.0W Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 4.5V to 13.2V V PP Positive high voltage supply 40V to VNN +250V VNN Negative high voltage supply -40V to -210V VIH High level input logic voltage VDD -1.5V to VDD VIL Low-level input logic voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V TA Operating free air temperature 0OC to 70OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 28-Lead (J) PLCC (PJ) (top view) 48-Lead LQFP (FG) (7x7x1.4mm) (top view) Pin Confi gurations Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV214PJ LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV214FG LLLLLLLLL CCCCCCCC AAA 28-Lead PLCC (PJ) 48-Lead LQFP (FG)

Sym Parameter Min Typ Max Units Conditions RONS Small signal switch on-resistance -- 5 5 Ω ISIG = 5.0mA VPP = +40V VNN = -160V- - 49 I SIG = 200mA - - 42 I SIG = 5.0mA VPP = +125V VNN = -100V-- 3 6 I SIG = 200mA - - 38 I SIG = 5.0mA VPP = +210V VNN = -40V- - 32 I SIG = 200mA ΔRONS Small signal switch On-resistance matching -- 2 0 % I SIG = 5mA, VPP = +125V, VNN = -125V RONL Large signal switch On-resistance -2 3- Ω V SIG = VPP - 10V, ISIG = 1A ISOL Switch off leakage per switch - - 10 µA V SIG = VPP -10V & VNN +10V DC offset switch off - - 300 mV R LOAD = 100KΩ DC offset switch on - - 500 mV R LOAD = 100KΩ IPPQ Quiescent VPP supply current - - 50 µA All switches off INNQ Quiescent VNN supply current - - -50 µA All switches off IPPQ Quiescent VPP supply current - - 50 µA All switches on, I SW = 5.0mA INNQ Quiescent VNN supply current - - -50 µA All switches on, I SW = 5.0mA Switch output peak current - - 2.0 A V SIG duty cycle 0.1% fSW Output switch frequency - - 50 kHz Duty cycle = 50% IPP Average VPP supply current - - 7.0 mA VPP = +40V VNN = -160V All output switches are turning ON and OFF at 50kHz with no load -- 5 . 0 VPP = +100V VNN = -100V -- 5 . 0 VPP = +160V VNN = -40V INN Average VNN supply current - - -7.0 mA VPP = +40V VNN = -160V VNN = -100V VNN = -40V IDD Average VDD supply current - - 10 mA f CLK = 5MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - - 4.0 µA --- ISOR Data out source current 45 - - mA V OUT = VDD - 0.7V ISINK Data out sink current 45 - - mA V OUT = 0.7V CIN Large input capacitance - - 10 pF --- TA Ambient temperature range 0 - 70 OC ---

Sym Parameter Min Typ Max Units Conditions tSD Set-up time before LE rises 150 - - ns --- tWLE Time width of LE 150 - - ns --- tDO Clock delay time to data out - - 150 ns --- tWCL Time width of CL 150 - - ns --- tSU Set-up time data to clock 15 8.0 - ns --- tH Hold time data from clock 35 - - ns --- fCLK Clock frequency - - 5.0 MHz 50% duty cycle, f DATA = fCLK/2 tR, tF Clock rise and fall times - - 50 ns --- TON Turn-on time - - 5.0 µs V SIG = VPP -10V, RLOAD = 10KΩ TOFF Turn-off time - - 5.0 µs V SIG = VPP -10V, RLOAD = 10KΩ dv/dt Maximum V SIG slew rate -- 2 0 V/ns VPP = +40V, VNN = -160V -- 2 0 V PP = +125V, VNN = -100V -- 2 0 V PP = +210V, VNN = -40V KO Off isolation -30 - - dB F = 5MHz, 1KΩ//15pF load -58 - - F = 5MHz, 50Ω load KCR Switch crosstalk -60 - - dB F = 5MHz, 50Ω load IID Output switch isolation diode current - - 300 mA 300ns pulse width, 2% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 12 17 pF 0V, f = 1MHz CSG(ON) On capacitance SW to GND 25 38 50 pF 0V, f = 1MHz +VSPK Output voltage spike -- 2 0 0 mV VPP = +40V, VNN = -210V, RLOAD = 50Ω-VSPK -- 2 0 0 +VSPK -- 2 0 0 VPP = +100V, VNN = -125V, RLOAD = 50Ω-VSPK -- 2 0 0 +VSPK -- 2 0 0 VPP = +160V, VNN = -40V, RLOAD = 50Ω-VSPK -- 2 0 0

Data in 8-Bit Shift Register LE CL Output Switch State D0 D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N XXXXXXXX H L Hold Previous State XXXXXXXX X HO F F O F F O F F O F F O F F O F F O F F O F F Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data fl ows through the latch. 4. D OUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. DATA IN LE CLOCK DATA OUT OFF ON OUT (TYP) V 50% 50% 50%50% t WLE t SD t SU t h 50%50% t OFF 50% t DO t ON t WCL CLR D N + 1 D N D N - 1 50%50% 90% 10%

100KΩ RL TON/TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP -10V RL 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20Log VOUT VIN VIN = 10 VP-P @5MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x VOUT VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ RL 50Ω +VSPK -VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP-P @5MHz VPP 5V VNN VPP VNN VDD GND RL VOUT

28-Lead (J-Lead) PLCC (PJ) Pin Description Pin Function

1 SW3

2 SW3

3 SW2

4 SW2

12 V NN

13 GND

14 V DD

17 CLK

21 SW7

22 SW7

23 SW6

24 SW6

25 SW5

26 SW5

27 SW4

28 SW4

3 SW4

5 SW4

8 SW3

10 SW3

12 SW2

14 SW2

16 SW1

18 SW1

20 SW0

22 SW0

25 V NN

28 GND

34 CLK

36 CLR

37 D OUT

39 SW7

41 SW7

43 SW6

45 SW6

47 SW5

48-Lead LQFP/TQFP (FG) Pin Description Power Up/Down Sequence: 1. Power up/down sequence is arbitrary except GND must be powered-up fi rst and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transistion. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.

28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b D D1 E E1 e Dimension (inches) .050 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.

0.150 MAX

.048/.042 x 45O

0.075 MAX

D E1 E Top View Side View View B A A2A1 Seating Plane e b Note 1 (Index Area) .056/.042 x 45O 0.20max

3 Places Base

.020 MIN

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV214 NR050807 48-Lead LQFP/TQFP (1.4mm) Package Outline (FG) Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) MIN 1.40 0.05 1.35 0.17 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 1.00 REF 0.25 BSC NOM - - 1.40 0.22 0.60 3.5 O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.

1 Seating

θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.