HV214FG

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Document overview

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PDF pages: 7

Technical content

Features

❏ HVCMOS ® technology for high performance ❏ Very low quiescent power dissipation – 10µA ❏ Low parasitic capacitances ❏ DC to 10MHz analog signal frequency ❏ -60dB typical output off isolation at 5MHz ❏ CMOS logic circuitry for low power ❏ Excellent noise immunity ❏ On-chip shift register, latch and clear logic circuitry ❏ Flexible high voltage supplies ❏ Surface mount package available General Description The Supertex HV214 is a low charge injection 8-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical MEMS modules. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS ® technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V 07/26/02 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Initial Release

Applications

❏ Medical ultrasound imaging ❏ Piezoelectric transducer drivers ❏ Inkjet printer heads ❏ Optical MEMS modules Block Diagram D LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 VNN V PP CLVDD D OUT CLK D IN

8 BIT

D LE D LE D LE D LE D LE D LE D LE LE

Electrical Characteristics

lobmySr etemaraPn iMp yTx aMs tinUs noitidnoC scitsiretcarahClacirtcelECD T( A )detonesiwrehtosselnusnoitidnocgnitarepodednemmocerrevo,C°52= R SNO ecnatsiser-nohctiwslangisllamS Ω I GIS Am0.5= V PP ,V04+= V NN V012-=94I GIS Am002= 24I GIS Am0.5= V PP ,V521+= V NN V521-=63I GIS Am002= 83I GIS Am0.5= V PP ,V012+= V NN V04-=23I GIS Am002= ∆R SNO ecnatsiser-nohctiwslangisllamS0 2% I GIS V,Am5= PP V,V521+= NN V521-= R LNO ecnatsiser-nohctiwslangisegraL3 2 Ω V GIS V= PP I,V01- GIS A1= I LOS hctiwsrepegakaelffohctiwS0 1 µA V GIS V= PP VdnaV01- NN V01+ ffohctiwstesffoCD0 03V mR DAOL K001= Ω nohctiwstesffoCD0 05V mR DAOL K001= Ω I QPP VtnecseiuQ PP tnerrucylppus0 5 µA ffosehctiwsllA I QNN VtnecseiuQ NN tnerrucylppus0 5- µA ffosehctiwsllA I QPP VtnecseiuQ PP tnerrucylppus0 5 µA I,nosehctiwsllA WS Am5= I QPP VtnecseiuQ NN tnerrucylppus0 5- µA I,nosehctiwsllA WS Am5= tnerruckaeptuptuohctiwS0 .2A V GIS %1.0elcycytud fWS ycneuqerfhctiwstuptuO0 5z HK% 05=elcycytuD IPP VegarevA PP tnerrucylppus 0.7 Am V PP V,V04+= NN V012-= sehctiwstuptuollA dnanOgninrutera htiwzhK05taffO .daolon

0.5 V PP V,V521+= NN V521-=

0.5 V PP V,V012+= NN V04-=

I NN VegarevA NN tnerrucylppus 0.7- V PP V,V04+= NN V012-= 0.5- V PP V,V521+= NN V521-= 0.5- V PP V,V012+= NN V04-= I QDD VtnecseiuQ DD tnerrucylppus0 1 µA I DD tnerruCylppusDDVegarevA0 .4A mf KLC V,zHM5= DD V0.5= I ROS tnerrucecruostuoataD5 4.0A mV TUO V= DD V7.0- I KNIS tnerrucknistuoataD5 4.0A mV TUO V7.0= C NI ecnaticapactupnicigoL0 1F p TA egnarerutarepmettneibmA0 0 7C ° VPP – VNN 250V HV214PJ HV214FG HV214X

Ordering Information

28-lead plastic 48-lead TQFP Die chip carrier

lobmySr etemaraPn iMp yTx aMs tinUs noitidnoC scitsiretcarahClacirtcelECA V( DD T,V5= A )detonesiwrehtosselnusnoitidnocgnitarepodednemmocerrevo,C°52= tDS sesiR*ELerofebemitputeS0 51s n t ELW *ELfohtdiwemiT0 51s n t OD tuoatadotemityaledkcolC0 51s n t LCW LCfohtdiwemiT0 51s n tUS kcolcotatademitputeS5 10 .8s n tH kcolCmorfatademitdloH5 3s n f KLC ycneuqerfkcolC0 .5z HMf ,elcycytud%05 ATAD f= KLC 2/ tR t, F semitllafdnaesirkcolC0 5s n T NO emitnonruT0 .5 µs V GIS V= PP R,V01- DAOL k01= Ω T FFO emitffonruT0 .5 µs V GIS V= PP R,V01- DAOL k01= Ω td/vdV mumixaM GIS etarwels sn/V V PP V,V04+= NN V012-= 02V PP V,V521+= NN V521-= 02V PP V,V012+= NN V04-= OKn oitalosiffO 03- Bd K1,zHM0.5=f Ω daolFp51/ 85-0 5,zHM0.5=f Ω daol K RC klatssorchctiwS0 6-B d0 5,zHM0.5=f Ω daol IDI tnerrucedoidnoitalosihctiwstuptuO0 03A me lcycytud%0.2,htdiweslupsn003 C )FFO(GS dnGotWSecnaticapacffO0 .52 17 1F pz HM1=f,V0 C )NO(GS dnGotWSecnaticapacnO5 28 30 5F pz HM1=f,V0 V+ KPS ekipSegatloVtuptuO 002 VmV PP V,V04+= NN R,V012-= DAOL 05= Ω V- KPS 002 V+ KPS 002 VmV PP V,V521+= NN R,V521-= DAOL 05= Ω V- KPS 002 V+ KPS 002 VmV PP V,V012+= NN R,V04-= DAOL 05= Ω V- KPS 002 Absolute Maximum Ratings* VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage 260V VPP Positive high voltage supply -0.5V to V NN +250V VNN Negative high voltage supply +0.5V to -260V Logic input voltages -0.5V to V DD +0.3V Analog Signal Range V NN to VPP Peak analog signal current/channel 2.5A Storage temperature -65 °C to +150°C Power dissipation 28-pin PLCC 1.2W 48 lead TQFP 1.0W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability.

VDD Logic power supply voltage 4.5V to 13.2V VPP Positive high voltage supply 40V to V NN + 250V VNN Negative high voltage supply -40V to -210V VIH High-level input voltage V DD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak to peak V NN +10V to VPP -10V TA Operating free air-temperature 0 °C to 70°C Power Up/Down Sequence: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2V SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD , VPP , and VNN should not be less than 1.0msec. Operating Conditions Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→ H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LL L OFF HL L O N LLL OFF HLL O N X XX XX XXX HL HOLD PREVIOUS STATE X XXXXXXX XH OFF OFF OFF OFF OFF OFF OFF OFF Truth Table

(TYP) V 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR D N – 1 D N D N + 1 50%50% 90% 10% Logic Timing Waveforms Block Diagram D LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 VNN V PP CLVDD D OUT CLK D IN D LE D LE D LE D LE D LE D LE D LE LE

VPP –10 DC Offset ON/OFF VPP 5V VNN VPP VNN VDD GND VOUT 100KΩ R L TON /TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP –10V R L 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20LogVOUT VIN VIN = 10 VP–P @5MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x ∆VOUT ∆VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ R L 50Ω +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP–P @5MHz VPP 5V VNN VPP VNN VDD GND R L VOUT Test Circuits

Pin Configurations Package Outlines HV214 28 Pin J-Lead Pin Function Pin Function

1 SW3 15 N/C

2 SW3 16 D IN

3 SW2 17 CLK

4 SW2 18 LE

5 SW1 19 CL

6 SW1 20 D OUT

7 SW0 21 SW7

8 SW0 22 SW7

9 N/C 23 SW6

10 V PP 24 SW6

11 N/C 25 SW5

13 GND 27 SW4

HV202, HV203 25 19 top view 28-pin J-Lead Package 24 23 22 21 20 5 116789 1 0 Package Outlines HV214 48-Pin TQFP Pin Function

Read HV214FG online.

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

Technical content

Features

Applications

8 BIT

Electrical Characteristics

0.5 V PP V,V521+= NN V521-=

0.5 V PP V,V012+= NN V04-=

Ordering Information

1 SW3 15 N/C

2 SW3 16 D IN

3 SW2 17 CLK

4 SW2 18 LE

5 SW1 19 CL

6 SW1 20 D OUT

7 SW0 21 SW7

8 SW0 22 SW7

9 N/C 23 SW6

10 V PP 24 SW6

11 N/C 25 SW5

13 GND 27 SW4

1 SW5

2 N/C

3 SW4

4 N/C

5 SW4

6 N/C

7 N/C

8 SW3

9 N/C

10 SW3

11 N/C

12 SW2

13 N/C

14 SW2

15 N/C

16 SW1

17 N/C

18 SW1

19 N/C

20 SW0

21 N/C

22 SW0

23 N/C

26 N/C

27 N/C

28 GND

30 N/C

31 N/C

32 N/C

34 CLK

36 CLR

38 N/C

39 SW7

40 N/C

41 SW7

42 N/C

43 SW6

44 N/C

45 SW6

46 N/C

47 SW5

48 N/C

1235 Bordeaux Drive, Sunnyvale, CA 94089

HV214FG specifications and overview.

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