HV214FG-G

HV214_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► HVCMOS® technology for high performance ► Very low quiescent power dissipation (-10µA) ► Low parasitic capacitances ► DC to 50MHz small signal frequency response ► -60dB typical output off isolation at 5.0MHz ► CMOS logic circuitry for low power ► Excellent noise immunity ► On-chip shift register, latch and clear logic circuitry ► Flexible high voltage supplies ► Surface mount packages

Applications

► Medical ultrasound imaging ► Non-destructive evaluation ► Inkjet printer heads ► Optical MEMS modules Block Diagram 250V Low Charge Injection, 8-Channel, High Voltage Analog Switch General Description The Supertex HV214 is a low charge injection, 8-channel, high voltage, analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical MEMS modules. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS ® technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-210V, +125V/-125V, +210V/-40V. SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 Latches Level Shifters Output Switches VDD LE CL DIN CLK DOUT 8-Bit Shift Register D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL VNN VPP

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 260V VPP positive high voltage supply -0.5V to VNN +250V VNN negative high voltage supply +0.5V to -260V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 2.5A Storage temperature -65OC to +150OC Power dissipation: 48-Lead LQFP 28-Lead PLCC 1.0W 1.2W Operating Conditions Sym Parameter Value VDD Logic power supply voltage 4.5V to 13.2V VPP Positive high voltage supply 40V to VNN +250V VNN Negative high voltage supply -40V to -210V VIH High level input logic voltage VDD -1.5V to VDD VIL Low-level input logic voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V TA Operating free air temperature 0OC to 70OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 1 28 4 26 Pin Configuration Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV214PJ LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV214FG LLLLLLLLL CCCCCCCC AAA 28-Lead PLCC 48-Lead LQFP 28-Lead PLCC (top view) 48-Lead LQFP (top view) Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or

Ordering Information

Part Number Package Option Packing HV214FG-G 48-Lead LQFP 250/Tray HV214FG-G M931 1000/Reel HV214PJ-G 28-Lead PLCC 38/Tube HV214PJ-G M904 500/Reel Typical Thermal Resistance Package θja 48-Lead LQFP 52OC/W 28-Lead PLCC 48OC/W -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 Sym Parameter Min Typ Max Units Conditions RONS Small signal switch on-resistance - - 55 Ω ISIG = 5.0mA VPP = +40V VNN = -210V- - 49 ISIG = 200mA - - 42 ISIG = 5.0mA VPP = +125V VNN = -125V- - 36 ISIG = 200mA - - 38 ISIG = 5.0mA VPP = +210V VNN = -40V- - 32 ISIG = 200mA ΔRONS Small signal switch on-resistance matching - - 20 % I SIG = 5.0mA, VPP = +125V, VNN = -125V RONL Large signal switch on-resistance - 23 - Ω VSIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - - 10 µA VSIG = VPP -10V & VNN +10V VOS DC offset switch off - - 300 mV RLOAD = 100kΩ DC offset switch on - - 500 mV RLOAD = 100kΩ IPPQ Quiescent VPP supply current - - 50 µA All switches off INNQ Quiescent VNN supply current - - -50 µA All switches off IPPQ Quiescent VPP supply current - - 50 µA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - -50 µA All switches on, ISW = 5.0mA ISW Switch output peak current - - 2.0 A VSIG duty cycle 0.1% fSW Output switch frequency - - 50 kHz Duty cycle = 50% IPP Average VPP supply current - - 7.0 mA VPP = +40V VNN = -210V All output switches are turning on and off at 50kHz with no load VNN = -125V VNN = -40V INN Average VNN supply current - - -7.0 mA VPP = +40V VNN = -210V All output switches are turning on and off at 50kHz with no load VNN = -125V VNN = -40V IDD Average VDD supply current - - 10 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - - 4.0 µA --- ISOR Data out source current 45 - - mA VOUT = VDD -0.7V ISINK Data out sink current 45 - - mA VOUT = 0.7V CIN Large input capacitance - - 10 pF --- TA Ambient temperature range 0 - 70 OC ---

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 Sym Parameter Min Typ Max Units Conditions tSD Set-up time before LE rises 150 - - ns --- tWLE Time width of LE 150 - - ns --- tDO Clock delay time to data out - - 150 ns --- tWCL Time width of CL 150 - - ns --- tSU Set-up time data to clock 15 8.0 - ns --- tH Hold time data from clock 35 - - ns --- fCLK Clock frequency - - 5.0 MHz 50% duty cycle, fDATA = fCLK/2 tR, tF Clock rise and fall times - - 50 ns --- TON Turn-on time - - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ TOFF Turn-off time - - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ dv/dt Maximum VSIG slew rate - - 20 V/ns VPP = +40V, VNN = -160V - - 20 VPP = +125V, VNN = -100V - - 20 VPP = +210V, VNN = -40V KO Off isolation -30 - - dB f = 5.0MHz, 1kΩ//15pF load -58 - - f = 5.0MHz, 50Ω load KCR Switch crosstalk -60 - - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - - 300 mA 300ns pulse width, 2% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 12 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 38 50 pF 0V, f = 1.0MHz +VSPK Output voltage spike - - 200 mV VPP = +40V, VNN = -210V, RLOAD = 50Ω-VSPK - - 200 +VSPK - - 200 VPP = +125V, VNN = -125V, RLOAD = 50Ω-VSPK - - 200 +VSPK - - 200 VPP = +210V, VNN = -40V, RLOAD = 50Ω-VSPK - - 200 Power Up/Down Sequence: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 Logic Timing Waveforms Truth Table Data in 8-Bit Shift Register LE CL Output Switch State D0 D1 D2 D3 D4 D5 D6 D7 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON X X X X X X X X H L Hold Previous State X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. DATA IN LE CLOCK DATA OUT OFF ON VOUT (typ) 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR DN+1 DN DN-1 50%50% 90% 10%

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 Test Circuits Switch OFF Leakage ISOL VPP 5V VNN VPP - 10V DC Offset ON/OFF VOUT TON/TOFF Test Circuit VPP -10V VOUT Isolation Diode Current IID VNN VSIG NC 50Ω 50Ω Output Voltage Spike VOUT 1.0KΩ +VSPK -VSPK VIN = 10VP-P @5.0MHz VOUT RLOAD 50Ω RLOAD 100kΩ VNN + 10V VPP 5V VNN VPP VNN VDD GND VPP 5V VNN VPP 5V VNN VPP 5V VNN VPP 5V VNN RLOAD 100kΩ VIN = 10VP-P @5.0MHz KO = 20 Log VOUT VIN OFF Isolation KCR = 20Log VOUT VIN Crosstalk VPP 5V VNN VPP VNN VDD GND VPP VNN VDD GND VPP VNN VDD GND VPP VNN VDD GND VPP VNN VDD GND VPP VNN VDD GND

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 28-Lead PLCC Pin Description Pin Function

1 SW3

2 SW3

3 SW2

4 SW2

5 SW1

6 SW1

7 SW0

8 SW0

10 VPP

12 VNN

13 GND

14 VDD

16 DIN

17 CLK

20 DOUT

21 SW7

22 SW7

23 SW6

24 SW6

25 SW5

26 SW5

27 SW4

28 SW4

1 SW5

3 SW4

5 SW4

8 SW3

10 SW3

12 SW2

14 SW2

16 SW1

18 SW1

20 SW0

22 SW0

24 VPP

25 VNN

28 GND

29 VDD

33 DIN

34 CLK

36 CLR

37 DOUT

39 SW7

41 SW7

43 SW6

45 SW6

47 SW5

48-Lead LQFP Pin Description

Supertex inc. www.supertex.com Doc.# DSFP-HV214 C070713 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Seating Plane Gauge Plane θL View B View B Seating Plane Top View Side View Note 1 (Index Area D1/4 x E1/4) A2A b D EE1 e Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV214 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV214 C070713 28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. .150max .048/.042 x 45O .075max D E Top View View B A A2A1 Seating Plane Note 1 (Index Area) .056/.042 x 45O Base Plane .020min b View B Horizontal Side View Vertical Side View Note 2 .020max (3 Places) R e 4 26281 Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.