HV209_13 SUTEX | Alldatasheet
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Technical content
Features
► HVCMOS® technology for high performance ► Operating voltage of up to 200V ► Output on-resistance typically 22Ω ► Integrated bleed resistors on the outputs ► 5.0V to 12.0V CMOS logic compatibility ► Very low quiescent current consumption (-10µA) ► -58dB typical off isolation at 5.0MHz ► Low parasitic capacitance ► Excellent noise immunity ► Flexible high voltage supplies General Description The Supertex HV209 is a 200V low charge injection 12-channel high voltage analog switch configured as 6 SPDT analog switches intended for medical ultrasound applications. Bleed resistors are integrated on the output switches to eliminate charge built up on the piezo electric transducers.The bleed resistors are at a nominal value of 35kΩ. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The outputs are configured as single-pole double- throw analog switches. Data is shifted into a 6-bit shift register using an external clock. The LE latches the shift register data into the individual switch latches. A logic HI connects a switch common Y X to SWX. A logic LOW connects YX to SWX. A logic HI in CL resets all switches to SWX simultaneously. 12-Channel High Voltage Analog Switch SW2 SW3 SW4 SW5 SW0 SW0 SW1 CL CLK VDD DOUT DIN GND
6 BIT
D LE CL SW1 SW2 SW3 SW4 SW5 RGND1/RGND2 High Voltage Level Translator D LE CL D LE CL D LE CL D LE CL D LE CL High Voltage Level Translator High Voltage Level Translator High Voltage Level Translator High Voltage Level Translator High Voltage Level Translator Block Diagram
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Recommended Operating Conditions Sym Parameter Value VPP Positive high voltage supply1 +40V to VNN +200V VNN Negative high voltage supply1 -10V to -160V VDD Logic power supply voltage1 +4.5V to +13.2V VIH High-level input voltage 0.8VDD to VDD VIL Low-level input voltage 0V to 0.2VDD VSIG Analog signal voltage peak-to-peak2 VNN +10V to VPP -10V TA Operating free air-temperature 0°C to 70°C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be within VPP and VNN voltage range or floating during power up/down transition. Absolute Maximum Ratings Parameter Value VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage +220V VPP Positive high voltage supply -0.5V to +200V VNN Negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V VSIG Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to +150°C Power dissipation: 48-lead LQFP 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration 48-Lead LQFP (top view) Product Marking 48-Lead LQFP YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV209FG LLLLLLLLL CCCCCCCC AAA Package may or may not include the following marks: Si or
Ordering Information
Part Number Package Option Packing HV209FG-G 48-Lead LQFP 250/Tray HV209FG-G M931 1000/Reel -G indicates package is RoHS compliant (‘Green’) Typical Thermal Resistance Package θja 48-Lead LQFP 52OC/W
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Sym Parameter 0OC +25OC +70OC Units Conditionsmin max min typ max min max RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω I SIG = 5.0mA VPP = 40V VNN = -160V- 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 ISIG = 5.0mA VPP = 100V VNN = -100V- 18 - 18 24 - 27 ISIG = 200mA - 23 - 20 25 30 ISIG = 5.0mA VPP = 190V VNN = -10V- 22 - 16 25 27 ISIG = 200mA ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % I SW = 5.0mA, VPP = 100V, VNN = -100V RONL Large signal switch on-resistance - - - 15 - - - Ω V SIG = VPP -10V, ISIG = 1.0A RINT Output switch shunt resistance - - 20 35 50 - - KΩ Output switch to R GND IRINT = 0.5mA VOS DC offset switch off - 50 - - 50 - 50 mV No load, RGND = 0V DC offset switch on - 50 - - 50 - 50 mV No load, RGND = 0V IPPQ Pos. HV supply current - - - 10 50 - - µA All SWs off INNQ Neg. HV supply current - - - -10 -50 - - IPPQ Pos. HV supply current - - - 10 50 - - µA All SWs on, ISW = 5.0mA INNQ Neg. HV supply current - - - -10 -50 - - ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A V SIG duty cycle ≤ 0.1% fSW Output switch frequency - - - - 50 - KHz Duty cycle = 50% IPP IPP supply current mA VPP = 40V VNN = -160V 50KHz output switching frequency with no load VNN = -100V VNN = -10V INN INN supply current mA VPP = 40V, VNN = -160V 50KHz output switching frequency with no load VNN = -100V VNN = -10V IDD Logic supply average current - 4.0 - - 4.0 - 4.0 mA f CLK = 5.0MHz, VDD = 5.0V IDDQ Logic supply quiescent current - 10 - - 10 - 10 µA --- I CIN Logic input capacitance - 10 - - 10 - 10 pF --- (over recommended operating conditions unless otherwise noted)
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Sym Parameter 0OC +25OC +70OC Units Conditionsmin max min typ max min max tSD Set up time before LE rises 150 - 150 - - 150 - ns --- t WLE Time width of LE 150 - 150 - - 150 - ns --- tDO Clock delay time to data out - 150 - - 150 - 150 ns --- t WCL Time width of CL 150 - 150 - - 150 - ns --- tSU Set up time data to clock 15 15 8.0 - 20 - ns --- tH Hold time data from clock 35 - 35 - - 35 - ns --- fCLK Clock frequency - 5.0 - - 5.0 - 5.0 MHz 50% duty cycle, fDATA = fCLK/2 tON Turn on time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RL = 10kΩ tOFF Turn off time - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RL = 10kΩ dv/dt Maximum VSIG slew rate - 20 - - 20 - 20 V/ns VPP = 40V, VNN = -160V - 20 - - 20 - 20 VPP = 100V, VNN = -100V - 20 - - 20 - 20 VPP = 190V, VNN = -10V KO Off Isolation -30 - -30 -33 - -30 - dB f = 5.0MHz, 1.0kΩ//15pF load -58 - -58 - - -58 - dB f = 5.0MHz, 50Ω load KCR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle C GS(OFF) Off capacitance switch to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, 1.0MHz C GS(ON) On capacitance switch to GND 25 50 25 38 50 25 50 pF 0V, 1.0MHz SPK Output voltage spike - 150 - - 150 - 150 mV RLOAD = 50Ω -VSPK - 150 - - 150 - 150 RLOAD = 50Ω (over recommended operating conditions VDD = 5.0V unless otherwise noted)
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Test Circuits DC Offset ON/OFF VPP 5V VNN VPP VNN VDD GND VOUT TON/TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP -10V 10kΩ VOUT Isolation Diode Current IID GND VNN VSIG Crosstalk NC GND 50Ω Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1kΩ RLOAD 50Ω +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN =10VP-P @5MHz VPP 5V VNN VPP VNN VDD GND VOUT 50Ω RLOAD RLOAD VIN =10VP-P @5MHz VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD KCR = 20Log VOUT VIN
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Logic Timing Waveforms Logic Truth Table Data Inputs LE CL Switch States D0 D1 D2 D3 D4 D5 Y0 Y1 Y2 Y3 Y4 Y5 L L L SW0 H L L SW0 L L L SW1 H L L SW1 L L L SW2 H L L SW2 L L L SW3 H L L SW3 L L L SW4 H L L SW4 L L L SW5 H L L SW5 X X X X X X H L Hold Previous State X X X X X X X H SW0 SW1 SW2 SW3 SW4 SW5 DATA IN LE CLOCK DATA OUT OFF ON VOUT (typ) 50% 50% 50%50% tWLE tSD tSU tH 50%50% tOFF 50% tDO tON tWCL CLR DN+1 DN DN-1 50% 50% 90% 10%
Supertex inc. www.supertex.com Doc.# DSFP-HV209 B070213 Pin Description Pin # Function
1 N/C
2 SW0
4 SW0
5 N/C
6 SW2
8 SW2
9 N/C
10 SW4
12 SW4
13 N/C
14 N/C
15 N/C
16 VNN
17 N/C
18 N/C
19 N/C
20 N/C
21 VPP
22 N/C
23 N/C
24 N/C
Pin # Function
25 SW5
27 SW5
28 N/C
29 SW3
31 SW3
32 N/C
33 SW1
35 SW1
36 N/C
37 RGND1
38 N/C
39 DOUT
40 VDD
41 DIN
42 CLR
44 CLK
45 GND
46 N/C
47 N/C
48 RGND2
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com HV209 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV209 B070213 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Seating Plane Gauge Plane θL View B View B Seating Plane Top View Side View Note 1 (Index Area D1/4 x E1/4) A2A b D EE1 e Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.