HV209

HV209_06 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ HVCMOS technology for high performanc e ❏ Operating voltage of up to 200V ❏ Output On-resistance typically 22Ω ❏ Integrated bleed resistors on the output s ❏ Very low quiescent power dissipation -10µA ❏ Low parasitic capacitance s ❏ -58dB typical output off isolation at 5MHz ❏ 5.0V to 12V CMOS logic circuitr y ❏ Excellent noise immunit y ❏ Flexible high voltage supplie s General Description The Supertex HV209 is a 200V low charge injection 12- channel high voltage analog switch configured as 6 SPDT analog switch intended for medical ultrasound applications . Bleed resistors are integrated on the output switches to eliminate charge built up on the piezo electric transducers . The bleed resistors are at a nominal value of 35K? ? Using HVCMOS technolog y, this device combines high voltag e bilateral DMOS switches and low power CMOS logic to pro- vide efficient control of high voltage analog signals. The outputs are configured as single pole double throw analog switches. Data is shifted into a 6-bit shift register using an external clock. The LE latches the shift register data into the individual switch latches. A logic high connects a switch common YX to SWX. A logic low connects YX to SWX. A logic hi in CL resets all switches to SWX simultaneousl y. SW2 SW3 SW4 SW5 SW0 SW0 SW1 CL CLK VDD DOUT DIN GND

6 BIT

D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL SW1 SW2 SW3 SW4 SW5 RGND1 / RGND2 Block Diagram HV209

VDD Logic power supply voltag e -0.5V to +15V VPP - VNN Supply voltag e +220V VPP Positive high voltage supply -0.5V to +200V VNN Negative high voltage supply +0.5V to -200V Logic input voltage s -0.5V to VDD +0.3V VSIG Analog Signal Range VNN to VPP Peak analog signal current/channe l 3.0A Storage temperatur e -65 C to +150OC Power dissipatio n 1.0W All voltages are referenced to ground. Absolute maximum ratings are those values which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may a ffect device reliabilit y. VPP – VNN 200V

Ordering Information

48-pin LQFP/TQFP (1.4mm) O HV209FG-G -G indicates that the package is RoHS compliant (’Green’) HV209FG

Electrical Characteristics

DC Characteristics (over recommended operating conditions unless otherwise noted) 30 26 38 48 I SIG = 5mA V PP = 40V, 25 22 27 32 I SIG = 200mA V NN = -160V Small Signal Switch (ON) RONS 25 22 27 30 ohms I SIG = 5mA V PP = 100V, Resistance 18 18 24 27 I SIG = 200mA V NN = -100V 23 20 25 30 I SIG = 5mA V PP = 190V, 22 16 25 27 I SIG = 200mA V NN = -10V Small Signal Switch (ON)∆R ONS 20 5.0 20 20 % I SW = 5mA, VPP = 100V, Resistance Matching VNN = -100V Large Signal Switch (ON) RONL 15 ohms V SIG = VPP - 10V, ISIG = 1A Resistance Output Switch Shunt R INT 20 35 50 K Ω Output switch to RGND Resistance IRINT = 0.5 mA DC Offset Switch Off 50 50 50 mV No Load, R GND = 0V DC Offset Switch On 50 50 50 mV No Load, R GND = 0V Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON ISW = 5mA Peak Current Output Switch Frequency f SW 50 KHz Duty Cycle = 50% 6.5 7.0 8.0 V PP = 40V, VNN = -160V IPP Supply Current I PP 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 190V, VNN = -10V 6.5 7.0 8.0 V PP = 40V, VNN = -160V INN Supply Current I NN 4.0 5.0 5.5 mA V PP = 100V, VNN = -100V 4.0 5.0 5.5 V PP = 190V, VNN = -10V Logic Supply I DD 4.0 4.0 4.0 mA f CLK = 5MHz, VDD = 5.0V Average Current Logic Supply I DDQ 10 10 10 µA Quiescent Current Data Out Source Current I Logic Input Capacitance CIN 10 10 10 pF 0°C +25°C +70°CCharacteristics Sym Units Test Conditionsmin max min typ max min max 50KHz Output Switching Frequency with no load

AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) 0°C +25°C +70°C Characteristics Sym min max min typ max min max Units Test Conditions Set Up Time Before LE Rises tSD 150 150 150 ns Time Width of LE t WLE 150 150 150 ns Clock Delay Time to Data Out tDO 150 150 150 ns Time Width of CL t WCL 150 150 150 ns Set Up Time Data to Clock t SU 15 15 8.0 20 ns Hold Time Data from Clock t h 35 35 35 ns Clock Freq f CLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK /2 Turn On Time t ON 5.0 5.0 5.0 µsV SIG = VPP -10V, R L = 10KΩ Turn Off Time t OFF 5.0 5.0 5.0 µsV SIG = VPP -10V, R L = 10KΩ 20 20 20 V PP = 40V, VNN = -160V Maximum V SIG Slew Rate dv/dt 20 20 20 V/ns V PP = 100V, VNN = -100V 20 20 20 V PP = 190V, VNN = -10V Off Isolation KO -30 -30 -33 -30 dB f = 5MHz, 1KΩ//15pF load -58 -58 -58 dB f = 5MHz, 50Ω load Switch Crosstalk K CR -60 -60 -70 -60 dB f = 5MHz, 50Ω load Output Switch Isolation I ID 300 300 300 mA 300ns pulse width, Diode Current 2.0% duty cycle Off Capacitance SW to GND C SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND C SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz Positive Output Voltage Spike +VSPK 150 150 150 mV R LOAD = 50Ω Negative Output Voltage Spike -VSPK 150 150 150 mV R LOAD = 50Ω

DO D1 D2 D3 D4 D5 LE CL Y0 Y1 Y2 Y3 Y4 Y5 LL L SW0 HL L SW0 LL L SW1 HL L SW1 LL L SW2 HL L SW2 LL L SW3 HL L SW3 LL L SW4 HL L SW4 LLL SW5 HLL SW5 XXX XXXHL XXX XXXXH SW0 SW1 SW2 SW3 SW4 SW5 Symbol Parameter Value VPP Positive high voltage supply1 +40V to VNN + 200V VNN Negative high voltage supply1 -10V to -160V VDD Logic power supply voltage1 +4.5V to +13.2V VIH High-level input voltage 0.8 V DD to VDD VIL Low-level input voltage 0V to 0.2V DD VSIG Analog signal voltage peak-to-peak2 VNN +10V to VPP -10V TA Operating free air-temperature 0 °C to 70°C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2V SIG must be within VPP and VNN voltage range or floating during power up/down transition. Operating Conditions* Truth Table HOLDS PREVIOUS STATE

VPP –10V R L 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20LogVOUT VIN VIN = 10 VP–P @5MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x ∆VOUT ∆VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ R L 50Ω +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP–P @5MHz VPP 5V VNN VPP VNN VDD GND R L VOUT Test Circuits

(TYP) V 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR D N + 1 D N D N - 1 50%50% 90% 10% Logic Timing Waveforms

D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL SW1 SW2 SW3 SW4 SW5 R GND1 / RGND2 HV209

HV209 48-Lead LQFP/ TQFP (1.4mm) Pin Function

1 N/C

2 SW0

4 SW0

5 N/C

6 SW2

8 SW2

9 N/C

10 SW4

12 SW4

13 N/C

14 N/C

15 N/C

16 VNN

17 N/C

18 N/C

19 N/C

20 N/C

21 VPP

22 N/C

23 N/C

24 N/C

25 SW5

27 SW5

28 N/C

29 SW3

31 SW3

32 N/C

33 SW1

35 SW1

36 N/C

37 RGND1

38 N/C

39 DOUT

40 VDD

41 DIN

42 CLR

44 CLK

45 GND

46 N/C

47 N/C

48 RGND2

48-Lead LQFP/ TQFP (1.4mm) A062906 Linear dimensions in millimeters. Angular dimensions in degrees  Pin 1 identifier located within the area indicated  Corner shape may differ from drawing.. 0.22 ± 0.05

0.50 BSC

9.00 ± 0.20 7.00 ± 0.20 9.00 ± 0.20 7.00 ± 0.20 1.60 max 0.45 - 0.750.05 - 0.15 0O - 7O 1.75 nom  1.75 nom  1 Side View Top View (4 places)