HV20420 SUTEX | Alldatasheet
Document overview
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Technical content
Features
nn HVCMOS ® technology for high performance nn Low charge injection nn Very low quiescent power dissipation – 10µA nn Output On-resistance typically 22 ohms nn Low parasitic capacitances nn DC to 10MHz analog signal frequency nn -60dB typical output off isolation at 5MHz nn CMOS logic circuitry for low power nn Excellent noise immunity nn On-chip shift register, latch and clear logic circuitry nn Flexible high voltage supplies nn Surface mount package available Absolute Maximum Ratings* VDD Logic power supply voltage -0.5V to +18V VPP - VNN Supply voltage 220V VPP Positive high voltage supply -0.5V to V NN +200V VNN Negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V DD +0.3V Analog Signal Range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 °C to +150°C Power dissipation 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability.
Electrical Characteristics
DC Characteristics (over recommended operating conditions unless otherwise noted) +25°C +70°C 50KHz Output Switching Frequency with no load 0°C Characteristics Sym Units Test Conditionsmin max min typ max min max Small Signal Switch (ON) 30 26 32 35 I SIG = 5mA V PP = + 50V, Resistance R ONS 25 22 27 32 I SIG = 200mA V NN = -150V 25 22 27 30 ohms I SIG = 5mA V PP = +100V, 18 18 20 23 I SIG = 200mA V NN = -100V Small Signal Switch (ON)ΔR ONS 20 5.0 20 20 % I SW = 5mA, VPP = +100V, Resistance Matching VNN = -100V Large Signal Switch (ON) RONL 15 ohms V SIG = VPP - 10V, ISIG = 1.0A Resistance Switch Off Leakage I SOL 5.0 1.0 10 15 µAV SIG = VPP - 10V Per Switch to VNN +10V DC Offset Switch Off 300 100 300 300 mV R L = 100KΩ DC Offset Switch On 500 100 500 500 mV R L = 100KΩ Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON I SW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON I SW = 5mA Peak Current Output Switch Frequency fSW 50 KHz Duty Cycle = 50% 8.1 8.8 10.0 V PP = +50V, VNN = -150V IPP Supply Current I PP 5.0 6.3 6.9 mA V PP = +100V, VNN = -100V 8.1 8.8 10.0 V PP = +50V, VNN = -150V INN Supply Current I NN 5.0 6.3 6.9 mA V PP = +100V, VNN = -100V Logic Supply I DD 6.0 4.0 6.0 6.0 mA f CLK = 3MHz Average Current Logic Supply I DDQ 10 10 10 µA Quiescent Current Logic Input Capacitance CIN 10 10 10 pF
Time to Turn Off VSIG*t SIG(OFF) 0n s Set Up Time Before LE Rises t SD 150 150 150 ns Time Width of LE t WLE 150 150 150 ns Clock Delay Time to Data Out tDO 175 175 190 ns Time Width of CL t WCL 150 150 150 ns Set Up Time Data to Clock t SU 15 15 8.0 20 ns Hold Time Data from Clock t H 35 35 35 ns Clock Freq f CLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK /2 Turn On Time t ON 5.0 5.0 5.0 µsV SIG = VPP - 10V Turn Off Time t OFF 5.0 5.0 5.0 µsV SIG = VPP - 10V
13 V PP = +50V
Maximum V SIG Slew Rate dv/dt VNN = -150V
13 V/ns V PP = +100V
VNN = -100V -30 -30 -33 -30 dB f = 5.0 MHz, Off Isolation KO 1KΩ //15pF load -45 -45 -60 -45 dB f = 5MHz, 50Ω load Switch Crosstalk K CR -60 -60 -70 -60 dB f = 5MHz, 50Ω load Output Switch Isolation I ID 300 300 300 mA 300ns pulse width, Diode Current 2.0% duty cycle Off Capacitance SW to GND C SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND C SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz Output Voltage Spike +V SPK 150 V PP = +100V mV V NN = -100V -VSPK 150 R L = 50Ω 0°C +25°C +70°C Characteristics Sym min max min typ max min max Units Test Condition *Time required for analog signal to turn off before output switch turns off. Operating Conditions* Symbol Parameter Value VDD Logic power supply voltage1,3 10.0V to 15.5 V VPP Positive high voltage supply1,3 50V to VNN + 200V VNN Negative high voltage supply1,3 -100V to -150V VIH High-level input voltage V DD -2V to VDD VIL Low-level input voltage 0V to 2.0V VSIG Analog signal voltage peak to peak2 VNN +10V to VPP -10V TA Operating free air-temperature 0 °C to 70°C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD , VPP , and VNN should not be less than 1.0msec. AC Characteristics (over operating conditions VDD = 15V, unless otherwise noted)
KCR = 20LogVOUT VIN VIN = 10 VP–P @5MHz NC 50Ω VPP 15V VNN VPP VNN VDD GND 50Ω Output Voltage Spike VPP 15V VNN VPP VNN VDD GND VOUT 50Ω +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP–P @5MHz VPP 15V VNN VPP VNN VDD GND R L VOUT TON /TOFF Test Circuit VPP 15V VNN VPP VNN VDD GND VPP –10V R L 10KΩ VOUT DC Offset ON/OFF VPP 15V VNN VPP VNN VDD GND VOUT 100KΩ R L Switch OFF Leakage ISOL VPP 15V VNN VPP VNN VDD GND VNN +10 VPP –10 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HLL O N X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→ H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. D OUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. Test Circuits
ON(TYP) VOUT 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR D N – 1 D N D N + 1 50%50% 90% 10% D LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 VNN V PP CLVDD D OUT CLK D IN
8 BIT
D LE D LE D LE D LE D LE D LE D LE LE Logic Timing Waveforms Logic Diagram
1 SW3 15 N/C
2 SW3 16 D
3 SW2 17 CLK
4 SW2 18 LE
5 SW1 19 CL
6 SW1 20 D
7 SW0 21 SW7
8 SW0 22 SW7
9 N/C 23 SW6
11 N/C 25 SW5
13 GND 27 SW4
HV204, HV206 HV204 Package Outlines HV204 28-Pin J-Lead Pin Function Pin Function