HV20220PJ-G

HV220_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS® technology for high performance Very low quiescent power dissipation – 10µA Output on-resistance typically 22 ohms Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies

Applications

Medical ultrasound imaging Piezoelectric transducer drivers General Description These devices are low charge injection 8-channel high-voltage analog switch integrated circuits (ICs) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and print- ers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, these switches combine high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. These ICs are suitable for various combinations of high voltage supplies, e.g., V PP/VNN : +50V/–150V, or +100V/–100V.B Block Diagram D LE CL LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL LEVEL SHIFTERS OUTPUT SWITCHESLATCHES SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 V PP VNNVDD DOUT DIN CLK 8-Bit Shift Register

Ordering Information

28-Lead PLCC 48-Lead LQFP/TQFP (1.4mm) 25-Ball fpBGA HV220 - - HV220GA HV220GA-G HV20220 HV20220PJ HV20220FG -HV20220PJ-G HV20220FG-G HV20320 HV20320PJ --HV20320PJ-G -G indicates the part is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 220V VPP positive high voltage supply -0.5V to V NN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65 OC to +150OC Power dissipation: 28-Lead PLCC 48-Lead LQFP/ TQFP(1.4mm) 25-Ball fpBGA 1.2W 1.0W 1.0W Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 1,3 4.5V to 13.2V VPP positive high voltage supply 1,3 40V to VNN +200V VNN negative high voltage supply 1,3 -40V to -160V VIH High level input voltage V DD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V 2 TA Operating free air temperature 0 OC to 70OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up fi rst and powered down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Product Marking HV20220 FG YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV20220FG LLLLLLLLL CCCCCCCC AAA HV20220 PJ HV20320 PJ HV20220 GA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV20220PJ LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV20320PJ LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW HV220GA LLLLLLLLL Top Marking

(Over operating conditions unless otherwise specifi ed ) RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω ISIG = 5mA VPP = +40V VNN = -160V- 25 - 22 27 - 32 I SIG = 200mA - 25 - 22 27 - 30 I SIG = 5mA VPP = +100V VNN = -100V- 18 - 18 24 - 27 I SIG = 200mA - 23 - 20 25 - 30 I SIG = 5mA VPP = +160V VNN = -40V- 22 - 16 25 - 27 I SIG = 200mA ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = - 100V RONL Large signal switch on-resistance --- 1 5 --- Ω V SIG = VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA V SIG = VPP -10V, VNN +10V VOS DC offset switch off - 300 - 100 300 - 300 mV R L = 100Ω DC offset switch on - 500 - 100 500 - 500 mV R L = 100kΩ IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, I SW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches on, I SW = 5.0mA fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Supply current mA VPP = +40V VNN = -160V All output switches are turning On and Off at 50kHz with no load PP = +100V VNN = -100V VNN = -40V INN Supply curent mA VPP = +40V VNN = -160V VNN = -100V VNN = -40V IDD Logic supply average IDDQ Logic supply Quiescent current - 10 - - 10 - 10 μA --- CIN Logic input capacitance - 10 - - 10 - 10 pF --- Sym Parameter 0OC +25 OC +70 OC Units Conditions Min Max Min Typ Max Min Max

Min Max Min Typ Max Min Max (Over recommended operating conditions: VDD = 5.0V, unless otherwise specifi ed) tSD Set up time before LE rises 150 150 150 ns --- tWLE Time width of LE 150 150 150 ns --- tDO Clock delay time to data out 150 150 150 ns --- tWCL Time width of CL 150 150 150 ns --- tSU Set up time data to clock 15 15 8.0 20 ns --- tH Hold time data from clock 35 35 35 ns --- fCLK Clock frequency 5.0 5.0 5.0 MHz 50% Duty cycle, f DATA= fCLK/2 tR, tF Clock rise and fall times 50 50 50 ns --- tON Turn on time 5.0 5.0 5.0 μs V SIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time 5.0 5.0 5.0 μs V SIG = VPP -10V, RLOAD = 10kΩ dv/dt Maximun V SIG slew rate 20 20 20 V/ns VPP = +160V, VNN = -40V 20 20 20 V PP = +100V, VNN = -100V 20 20 20 V PP = +40V, VNN = -160V KO Off isolation -30 -30 -33 -30 dB f = 5.0MHz, 1kΩ/15pF load -58 -58 -58 f = 5.0MHz, 50Ω load KCR Switch crosstalk -60 -60 -70 -60 dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current 300 300 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK Output voltage spike - - - - 150 - - mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +100V, VNN = -100V, RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +160V, VNN = -40V, RLOAD = 50Ω-VSPK - - - - 150 - - QC Charge injection - - - 820 - - - pC VPP = +40V, VNN = -160V, VSIG = 0V VSIG = 0V VSIG = 0V

50% 50% 50% 50% 50% 50%50% 50% 50% OUT (TYP) V OFF ON CLR t WCL 90% 10% t OFF DD SD ON t tt t t h WLE SU t LE Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HL L O n L L L Off HLL O n X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data fl ow through the latch. 4. D OUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.

100KΩ RL TON/TOFF Test Circuit VPP 5V VNN VPP VNN VDD GND VPP -10V RL 10KΩ VOUT Isolation Diode Current IID VPP 5V VNN VPP VNN VDD GND VNN VSIG Crosstalk KCR = 20Log VOUT VIN VIN = 10 VP-P @5MHz NC 50Ω VPP 5V VNN VPP VNN VDD GND 50Ω Charge Injection VPP 5V VNN VPP VNN VDD GND VSIG VOUT 1000pF Q = 1000pF x V OUT VOUT Output Voltage Spike VPP 5V VNN VPP VNN VDD GND VOUT 1KΩ RL 50Ω +VSPK -VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10 VP-P @5MHz VPP 5V VNN VPP VNN VDD GND RL VOUT

Typical Performance Curves CLK Frequency (KHz) TDO vs. Ambient Temperature TA Ambient Temp TA (°C) T OD )sn( R NO )smho( Ambient Temperature (oC) R NO Am5@ )smho( Off-Isolation vs. Signal Voltage Frequency VDD = 5.0V, VPP/VNN = ±100V )Bd( noitalosI-ffO -80.0 -75.0 -70.0 -65.0 -60.0 -55.0 -50.0 1.0 10.0 RON vs. Ambient Temperature TA VDD = 5.0V, VPP/VNN = ±100V RON vs. VPP/VNN VPP/VNN = ±100V IPP/INN vs. Output Switching Frequency I PP I/ NN )Am( tnerruC egarevA Output Switching Frequency (KHz) VDD = 5.0V VDD = 5.0V, VPP/VNN = ±100V I DD C tnerru )Am( IDD vs Clock Frequency VDD = 5.0V, VPP/VNN = ±100V, TA = 0°C to 70°C 3.0 2.0 1.0 0.0 10 1000 10000 100 Signal Voltage Frequency (MHz) VPP VNN TA = 0oC TA = 25oC TA = 70oC TA = 125oC TA = 70°C TA = 0°C -50 -25 0 25 50 75 100 125 150 10.0 20.0 30.0 40.0 ISW = 5mA ISW = 200mA 40V 60V 80V 100V 120V 140V 160V 10.0 20.0 30.0 40.0 50.0 -160V -140V -120V -100V -80V -60V -40V TA = 125°C TA = 85°C TA = 25°C TA = 0°C -50 -25 0 25 50 75 100 125 100 VDD = 5.0V VDD = 13.5V 0 2 55 07 5 1 0 0 125 150

Pin Description (HV220GA) Ball Location Function A3 SW1 B2 SW2 B3 SW1 B4 SW0 B5 SW0 B6 V NN C1 SW3 C2 SW3 C3 SW2 C4 V PP C5 GND C6 D IN C7 V DD D1 SW4 D2 SW4 D3 SW5 D4 SW7 D5 LE D6 CLK E2 SW5 E3 SW6 E4 SW7 E5 D OUT E6 CLR F3 SW6 Pin Description (HV20220PJ) Pin Function Pin Function

1 SW3 15 N/C

2 SW3 16 D

3 SW2 17 CLK

4 SW2 18 LE

5 SW1 19 CL

6 SW1 20 D

7 SW0 21 SW7

8 SW0 22 SW7

10 V NN 24 SW6

11 N/C 25 SW5

12 GND 26 SW5

14 N/C 28 SW4

9 N/C 23 SW6

12 V NN 26 SW5

13 GND 27 SW4

Pin Description (HV20320PJ) Pin Function Pin Function

1 SW5 25 V NN

2 N/C 26 N/C

3 SW4 27 N/C

4 N/C 28 GND

5 SW4 29 V

6 N/C 30 N/C

7 N/C 31 N/C

8 SW3 32 N/C

9 N/C 33 D

10 SW3 34 CLK

11 N/C 35 LE

12 SW2 36 CLR

13 N/C 37 D

14 SW2 38 N/C

15 N/C 39 SW7

16 SW1 40 N/C

17 N/C 41 SW7

18 SW1 42 N/C

19 N/C 43 SW6

20 SW0 44 N/C

21 N/C 45 SW6

22 SW0 46 N/C

23 N/C 47 SW5

Pin Description (48-Lead FG)

48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.

1 Seating

θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.

HV220GA 25-Ball fpBGA (GA) Top View Bottom View Enlarged Side View Note: All dimensions are in millimeters

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP - HV220_HV20220_HV20320 C073107 28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b D D1 E E1 e Dimension (inches) .050 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. .150 MAX .048/.042 x 45O .075 MAX 4 26 D E1 E Top View Side View View B A A2A1 Seating Plane e Note 1 (Index Area) .056/.042 x 45O .020 MAX

3 Places

.020 MIN b View B