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Technical content
Features
n HVCMOS ®\` technology n Up to 130V peak to peak output switching n Output On-resistance typically 40 ohms n Low parasitic capacitances n DC to 10MHz analog signal frequency n -45dB typical output off isolation at 5MHz n CMOS logic circuitry for low power and excellent noise immunity n On-chip shift register, latch and clear logic circuitry Absolute Maximum Ratings* VDD Logic power supply voltage -0.5V to +18V VPP - VNN supply voltage 174V VPP Positive high voltage supply -0.5V to +90V VNN Negative high voltage supply +0.5V to -90V Logic input voltages -0.5V to VDD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 1.5A Storage temperature -65 °C to +150°C Power dissipation 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability.
0°C +25°C +70°C Characteristics Sym Units Test Conditions min max min typ max min max Switch (ON) Resistance RONS 50 40 50 60 ohms I SW = 5mA, VSIG = 0V Switch (ON) Resistance RONS 35 25 35 45 ohms I SW = 200mA, VSIG = 0V Switch (ON) Resistance RONS 55 45 55 65 ohms V PP = +50V, VNN = -50V ISW = 5mA, VSIG = 0V Switch (ON) Resistance RONS 40 25 40 50 ohms V PP = +50V, VNN = -50V ISW = 200mA, VSIG = 0V Switch (ON) Resistance ΔR ONS 15 15 15 % V PP = +50V, VNN = -50V Matching ISW = 5mA, VSIG = 0V Switch Off Leakage I SOL 50 0.5 50 150 µAV SIG = VPP -10V thru 10KΩ Per Switch with 8 SWS in parallel DC Offset Switch Off 500 100 500 500 mV R L = 100KΩ DC Offset Switch On 500 100 500 500 mV R L = 100KΩ Pole to Pole C SW 10 4.5 10 10 pF DC Bias = 40V Switch Capacitance f = 1MHz Logic Input Capacitance CIN 3.5 pF Pos. HV Supply Current IPPQ 200 50 200 200 µA ALL SWS OFF Neg. HV Supply Current INNQ -200 -50 -200 -200 µA Pos. HV Supply Current IPPQ 0.8 1.6 mA 1 SW ON, I SW = 5mA Neg. HV Supply Current INNQ -0.8 -1.6 mA V SIG = 0V Pos. HV Supply Current IPPQ 0.6 1.2 mA V PP = +50V, VNN = -50V, Neg. HV Supply Current INNQ -0.6 -1.2 mA 1 SW ON, I SW = 5mA Switch Output 1.5 A V SIG ≤ 0.1% Duty Cycle, Peak Current f = 10KHz Logic Supply I DD 4 6 mA f CLK = 3MHz Average Current Logic Supply I DDQ 10 500 µA Quiescent Current Data Out Source Current I
Electrical Characteristics
(over operating conditions, VPP = +80V, VNN = -80V and VDD = 15V unless otherwise noted) DC Characteristics AC Characteristics 0°C +25°C +70°C Characteristics Sym Units Test Conditionsmin max min typ max min max Set Up Time Before LE Rises tSD 260 ns Time Width of LE tWLE 300 ns Clock Delay Time to Data Out tDO 250 330 ns Turn On Time tON 5.0 2.5 5.0 5.0 µsR L =10KΩ Turn Off Time t OFF 10 5.0 10 10 µsR L =10KΩ Time Width of CL t WCL 150 ns Off Isolation KO -35 -45 dB Signal Freq. = 5MHz Max Clock Freq fCLK 3.0 MHz 50% Duty Cycle fDATA = fCLK /2 Set Up Time Data to Clock t SU 0n s Hold Time Data from Clock t h 35 ns Switch Crosstalk KCR -45 dB Signal Freq. = 5MHz
+80V -80V 15V R L 10KΩ +80V -80V 15V OUTV 50Ω NC 50Ω Switch OFF Leakage ISOL +80V -80V 15V VPP -15V VNN +15V VDD GND VPP VNN VIN = 10 VP-P @5MHz VDD GND VPP VNN VDD GND VPP VNN VOUT TON /TOFF VPP -15V Crosstalk KCR = 20Log VOUT VIN VOUT VIN VDD GND VPP VNN VDD GND VPP VNN OFF Isolation KO = 20Log +80V -80V 15V VIN = 10 VP-P @5MHz R L DC Offset ON/OFF +80V -80V 15V R L100KΩ VOUT VOUT Symbol Parameter Value VDD Logic power supply voltage +10.0V to +15.5V VPP Positive high voltage supply +50V to +80V VNN Negative high voltage supply -50V to -80V VIH High level input voltage VDD -2V to VDD VIL Low-level input voltage 0 to 2.0V VSIG Analog signal voltage peak to peak VNN +15V to VPP -15V TA Operating free air-temperature 0° to 70°C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. V SIG must be VNN ≤ VSIG ≤VPP or floating during power up/down transition. Test Circuits Operating Conditions
ON(TYP) VOUT 50% 50% 50%50% tWLE tSD tSU th 50%50% tOFF 50% tDO tON tWCL CLR D N – 1 D N D N + 1 50%50% 90% 10% Logic Timing Waveforms Logic Diagram D LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 VNN V PP CLVDD D OUT CLK D IN
8 BIT
D LE D LE D LE D LE D LE D LE D LE LE
D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N XXXXXXXXX HO F F O F F O F F O F F O F F O F F O F F O F F XXXXXXXXH L HOLD PREVIOUS STATE Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L→ H transition CLK. 3. The clear input over rides all other inputs. 4. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 5. D OUT is high when switch 7 is on. 6. Shift register clocking has no effect on the switch states if LE is H. Truth Table
Pin Configurations Package Outlines 28-Pin DIP Pin Function Pin Function