HV111

HV111 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❑ No External Parts Required ❑ On Board 80V, 2A MOSFET ❑ No Rsense Needed ❑ ±8.0V to ±80V Input Voltage Range ❑ Two Level Current Limiting ❍ 1.2A Initial Inrush Limit ❍ 2.0A Second Inrush Limit/Circuit Breaker Triggers Servo Limit to 1.2A for Toc then shuts down ❑ Fast Response Current Limit when Over Current or Step Voltage at Input Supply (eg. Diode ‘OR’ing) ❑ UVLO/ENABL E & POR Supervisory Circuits ❑ Programma ble UVLO ❑ Over Current Protection ❑ 9.0sec Auto Retry ❑ Built in Thermal Shutdown with Hysteresis ❑ 80V Open Drain PW RGD bar Flag ❑ Thermally Rugged DPAK 5 Package

Applications

❑ Power Ethernet Systems ❑ Routers, Switches ❑ Charg ers ❑ Security Peripherals & Cameras ❑ Automotive Protection ❑ Negative Supply Rail Breaking Applications ❑ Networking Line Cards ❑ Telecom Line Cards

Description

The HV11 1 is a complete power managem ent solution for switched or pluggable backplane applications up to 1.65A, running from –8.0 to -80V, requiring no external components or programming in many applications. The HV111 is not limited to only negative input voltages. It can also be used in +8.0 to +80V system s. An internally programme d supervisor UVLO/ ENABLE may be overridden with external resistors for custom settings. Satisfying this supervisor will begin a POR phase to ensure de-bouncing. Thereafter, a servo loop controls an internal 80V, 2A pass element to limit current. The circuit uses internal mirrors to measure current, eliminating the need for a sense resistor. The HV111 includes two current modes: i) initial current limit mode limits the current to 1.2A during turn on; ii) thereafter a 2A monitor circuit will re-trigger the servo mecha nism back to 1.2A limit if it is tripped. An on-board thermal supervisor ensures that the device can never be dam aged by over current conditions. Circuit breaker functionality is obtained through a either a current limit timeout or a PW M current limiter for severe faults. If the servo limits for more than 75ms then the part will shut dow n the pass elem ent, and initiate a 9sec timer after which the turn on sequence will restart. The HV111 is available in a thermally rugged DPAK-5 package which provides improved thermal resistance when compared to SO-8 based solutions. Typical Schematics and Waveforms INRUSH PWRGD DRAIN GND* *Referred to –48V Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assume d for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.s upertex.com. For complete liability information on all Supertex products, refer to the m ost current databook or to the Legal/Disclaim er page on the Supertex website. 7/24/03

Ordering Information

A bsolute M axim um R atings Supply Voltage*, Vpp -0.5V to 90V Operating Temperature Range -40°C to +85°C Storage Temperature Range -65° to +150°C

5 Pin DPAK Thermal Resistance RθJA 80°C/W

5 Pin DPAK Thermal Resistance RθJC 11°C/W

• Relative to VNN (1) Shorted-circuit tim er starts after PO R timer. If VDS drops more than ¼(V PP -VNN ) after tSC then a shorted-circuit condition exists. Electrical Characteristics ( * means -20°C< TA < +85°C) Symb ol Param eter M in Typ M ax U nits TA Con ditions VPP Supply Voltage -80 -8.0 V * VPP – VNN IPP Supply Current 1 mA VNN = -48V, Standby Mode VUVL O Internal UVLO Threshold (High to Low ie. Turning Off) -23.5 -26.0 -28.5 V * Subtract VHYS for Low-to-High VHYS Internal UVLO Hysteresis 1.5 2.5 3.5 V * VUV UVLO Comp arator Threshold 1.10 1.20 1.30 V * Referenced to VNN VUVHYS UVLO Comp arator Hysteresis 60 100 140 mV * R UVL O UVLO Input Resistance 78 111 144 kΩ R DS MOSFET On Resistance 1 1.5 Ω * ILEAK Output Leakage Current 10 µA * MOSFET is off IINRUSH Inrush Current Limit 1.15 1.40 1.65 A * ICB Circuit Breaker Trip C urrent 1.65 2.00 2.35 * Trips then limits to ILIMIT until toc expires. ILIMIT Over Load Current Limiting 1.2 A * ISC Shorted Circuit PW M Average Current 230 m A VPP -VDRAIN < ~1V VOL PWRGD PW RGD Output Low Voltage 0.4 V I=1mA; Reference to VNN IOHPWRGD PW RGD Output leakage Current 10 µA * V=5V; Reference to VNN tSC Shorted-Circuit Timer (1) (4) 40 75 110 ms * tOC Over-Current Timer (2) (4) 40 75 110 ms * tLIMIT Current Limit Delay Time (3) 10 µs * Limits within 10µs. May take up to 100µs to reach final level. tPOR POR Timer 2.5 4.5 6.5 ms * tRESTART Restart Timer (4) 9 Sec * TOVER Over Temperature Trip Point 120 135 150 °C * Low to High TRESET Temperature Reset 70 100 °C * High to Low (2) If the output current is in an overload condition then the output immediately goes to current limit and starts the over-current timer. If IOU T does not drop back below ILIMIT before the timer expires then an over current condition exists. The timer is immediately reset when a fault is cleared. (3) Tim e for fast return to limit circuit to react. (4) Guaranteed by design.

Thermal Shutdown Auto-Retry In addition to the ab ove parameters, the HV111 will shutdown if the temperature on the die reaches ~135°C and it will not restart until the temperature drops to 100°C or less (could be significantly less). The thermal sensor is key in providing a bullet proof power m anagement solution because it ensures that the device will turn off long before dama ge can occur. This is a significant advantage over solutions that do not contain an integral M O SFET as then the temperature cann ot be easily sensed quickly and accurately. Any fault condition will cause an automatic 9sec retry to occur. This retry will occur indefinitely (as long as the thermal supervisor is satisfied). Figure 6 shows typical waveforms for the auto-retry. 50V/div 200m a/div PWRG D VPP -VNN IDS Thermal engineering using the HV 111 is key to proper system operation. The 1Ω MOSFET pass element ma y reach a value as high as 1.5Ω at high temperatures. There are numerous methods to reduce the thermal resistance of the RθJA. The following table describes some options: Method R θJA Description FR 4 70-80° C /W Straight Con vection FR4 Heat Sink 40° C/W 10cm PCB H/S FR4 + H/S 13° C/W External Sink + Holes IMS (40cm ) 9° C/W Floating in Air IMS* w/ H/S 4.5° C/W External Heatsink Timers * IMS is a metal substrate board The timer subsystems are critical to successful operation of the HV111. Timers are as follows: To determine your required thermal impedance, RθJA, is quite simple. In a parallel to Oh ms law, Pow er x R θJA = ∆T. Junction temperature, which is limited to 120°C minimum, is Tmaxambie nt + ∆T. For example, if the highest operating ambient temperature were 55°C as with m any networking applications, and the current were 1.6A, then the required thermal resistance would be calculated as follows: Tim er D uration Power-on-Reset 4.5m s Initial Inrush Timeout 75ms Shorted Inrush PW M 10µs Shorted Circuit Timer 75ms Second Inrush (Diode ‘OR’ing): ❒ Return to Limit ❒ Timeout 10µs (100µs) 75ms Auto-R etry 9sec Determine maximum ambient = 55°C. Determine max junction temp. = 120°C Determine max operating current = 1.6A. Therefore ∆T = 120-55°C = 65°C. This is the time from satisfying the undervoltage comparator. Each “bounce” will reset this tim er & therefore observed delay may be higher than this “ideal” delay. Max. Power = 1.23A *1.5Ω = 3.84W. Now ∆T / Power = RθJA = 65°/3.84W = 20°C/W. 2 Shorted-circuit tim er starts after POR timer. If VDS drops more than ¼(VPP -VNN ) after tSC then a shorted-circuit condition exists. To achieve a RθJA of 20°C/W or better the table above show s that it will be necessary to use a DPAK external heatsink or IMS substrate. Lim it within 10µs, but may take up to 100µs to settle. Current Sensing – No RSENSE Required This is the minim um value of the low to high therm al shutdow n according to the electrical specifications on pg. 2. This is the maxim um M O SFET on resistance at high temperature. The HV11 1 u ses an internal 6000:1 current mirror to eliminate the need for a sense resistor. This saves energy and eliminates the need for a power compo nent. The current mirror used by Supertex is unique in that it utilizes special circuitry to normalize for the variations in VDS between the primary pass element and the internal eleme nt which w ould otherwise cause current mismatch – and forces competitors to use internal sense resistors in similar applications. This mecha nism also pr ovides the s horted circuit PW M functionality which can help protect systems in the case of severe short circuits.

Figure 10 – Limit Timeout Initial Inrush Timeout Figure 9 – Turn on Waveforms The HV111 monitors the drain source voltage and the output current. During hotswap if the drain source does not drop below 1/4 of input voltage within a shorted-circuit timer period (tSC = 75ms), then the part will conclude that a short circuit condition exists, will turn off the internal MOSFET and auto-retry with a period of 9.0sec. This case is illustrated in Fig. 10 above (where waveform 4 is DRAIN current and waveform 1 is V PP ). Note that if the short circuit is low enough impedance to hold the DRAIN voltage within ~1V of VPP then the PW M current limit will engage as show n in Fig. 7. Further, the PWM cur rent limit will remain until VPP – VDS >~1V. Referring to Figure 9, the operation of the HV11 1 may be illustrated. On initial power application (w aveform 1 in Fig. 9) the H V111 provides a regulated supply for the internal circuitry. Until the proper internal voltage is achieved all circuits are held reset, the N-channel MOSFET is off and the PWRGD b ar pin is open (INACTIVE). Once the internal regulator is safe to operate, the under voltage lock out (UVLO) senses the input voltage. The UVLO will hold the pass eleme nt off until it is satisfied. At any time during the start up cycle or thereafter, the input voltage falling below the UVLO threshold will turn off the N-channel MOSFET and reset all internal circuitry. The IC also includes a clamp for the spurious inrush through Cload and the Cfb of the MOSFET pass eleme nt. A normal restart sequence will be initiated once the input voltage rises above the UV LO threshold. After the hotswap period is finished successfully, the internal MOSFET is turned fully on & the PWRGD b ar is pulled low (ACTIVE). PWRGD bar operation (connected to a pullup) is illustrated by Waveform 3 in Fig. 9. The UVLO supervisor works in conjunction with a pow er on reset (POR) timer. The timer is approximately 4.5ms to overcome contact bounce. During the contact bounce if input voltage falls below the UVLO threshold voltage then the POR timer will reset. In this way the card will be held off until bouncing ends. The POR timer will restart again whe n the input voltage rises above the UVLO threshold once again. After a full POR period is satisfied, the N-channel MOSFET begi ns to turn on to charge the output capacitor with a current source limited to ~1.2A (illustrated by W aveform 4 in Fig. 9). Note the PWM protection at the leading edge of the current rise in W aveform 4; this is the PW M protection limiting current because a capacitor initially appears as a dead short. Waveform 2 shows the VDS or DRAIN pin.

Package Information

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1225 Bordeaux Drive, Sunnyvale, CA 94089

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