HV110 SUTEX | Alldatasheet
Document overview
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Technical content
Features
Implements IEEE802.3af Standard for PD 400mA Inrush Current Limit 350mA Operating Current 400mA Fault Current Limit Fast Response Current Limit when Over Current or Step Voltage at Input Supply Programmable UVLO/ENABLE pin 9 seconds Auto Restart Built in Thermal Shutdown with Hysteresis 90V Open Drain PWRGD (active low) output. Optional Turn on Timeout Disable On Board 90V, 1Ω MOSFET Input Voltage Surge ratings up to 90V IOL Tested
Applications
IP Phones Wireless Access Points End-Spans and Mid-Spans PoE Routers, Switches Chargers Security Peripherals & Cameras
Description
HV110 provides complete power management and protection for Powered Devices (PDs) utilizing the IEEE802.3af protocol. As the most complete PD Power Manager available, HV110 features a 400mA inrush limit and fault current limit, as well as minimum current shutdown to ensure additional protection and reliability to expensive equipments connected to the PD switch. The internal power switch uses scaled current-mirror technology which eliminates the need for an external sense resistor and provides highly accurate current sensing at the high and low end operating conditions. HV110 uses rugged high voltage junction isolated process, which eliminates the need for any external high voltage protection devices at the input of these controllers. Circuit isolation also reduces the chance of tripping on system noise. A 90V open drain PWRGD pin provides status information and can be used to enable the DC/DC power supplies. HV110 is available in a thermally rugged DPAK-5 package that provides improved thermal resistance when compared to SO-8 based solutions. Typical Application Figure 1. Typical Application Circuit
Electrical Characteristics (at 0°C < TA < +75°C, unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions VPP Supply Voltage (1) V VPP referenced to VNN IPP Supply Current mA VPP = -48V, Standby Mode. MOSFET off. VUVLO Internal UVLO Threshold (Turn OFF) (2) V VPP referenced to VNN VUVHO Internal UVLO Threshold (Turn ON) (2) V VPP referenced to VNN VHYS UVLO Comparator Hysteresis V VUVTH UVLO Comparator Threshold 1.1 1.2 1.3 V Referenced to VNN RUVLO UVLO Input Resistance 100 kΩ RDS MOSFET On Resistance 1.6 Ω Measured at 25 oC and Ids = 200mA ILEAK Output Leakage Current µA Internal MOSFET off IOUT Operating Output Current 350 mA IINRUSH Inrush Current Limit 300 350 400 mA IOC Over Load Current Limiting 300 350 400 mA IMIN Minimum Current Threshold mA VSLEW Slew Rate to Enable Turn on Timers 4.25 V/ms Enables Timers VOLPWRGD PWRGD Output Low Voltage 0.4 V I=3mA; Referenced to VNN IOHPWRGD PWRGD Output Leakage Current µA V=5V; Referenced to VNN tSC Shorted-Circuit Timer (3) ms Measured at TA = 25°C tUC Under-Current Timer (4) 350 ms Measured at TA = 25°C tOC Over-Current Timer (5) ms Measured at TA = 25°C tLIMIT Current Limit Delay Time (6) µs Measured at TA = 25°C tPOR POR Timer 3.5 ms Measured at TA = 25°C tRESTART Restart Timer sec Measured at TA = 25°C TOT Over Temperature Trip Limit 140 oC THYS Temperature Hysteresis oC Absolute Maximum Ratings* Supply Voltage, Vpp (1) -0.5V to 90V Operating Temperature Range -40°C to +85°C Storage Temperature Range -65° to +150°C 5-Pin DPAK Thermal Resistance RθJA (minimum footprint) 110°C/W UVLO/Enable Input (1) PWRGD Open Collector Input (1) 90V
Ordering Information
- Absolute Maximum Ratings are those values beyond which damage to device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level my affect reliability. All voltages are references to VNN pin. ( 1 ): HV110 will work in both Positive and Negative voltage applications, the maximum differential voltage between the VPP and VNN pins must not be exceeded. ( 2 ): UVLO Threshold to be modified using external resistors, when a zener diode is connected to VPP pin. (See Signature Detection) ( 3 ): Shorted-circuit timer starts after POR timer. If VOUT does not charge at least 90% Vin before tSC then a shorted-circuit condition exists. ( 4 ): Under-current timer starts when IOUT goes below IMIN. If IOUT stays below IMIN longer than tUC then MOSFET is turned off due to under current condition. ( 5 ): If the output current is in an overload or shorted load condition then the output immediately goes to current limit and starts the over-current timer. If IOUT does not drop back below ILIMIT before the timer expires then an over current condition exists. The timer is immediately reset when a fault is cleared. ( 6 ): Time for fast return to limit circuit to react.
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Figure 3. Package Drawing: DPAK-5 Figure 2. HV110 Functional Block Diagram converts a conventional router into a PSE. PSE and PD devices for use in PoE applications. Interface (PI) Devices (usually the LAN cables). (e.g. the router) may not apply for the Midspan PSE. dependent on the PSE for its normal operation. maximum protection while ensuring compliance. some of the features and operation of PDs.
is limited to a continuous maximum output of 15.4W. impedance, in a voltage range from 2.8V to 10V. effect of diode level shift. classifications included in the IEEE802.3af standard. power than shown for the given Class. after the 300ms if the PSE does not react. Table 1. PD Power Classification Table 2. Classification Signature measured at PD connector
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According to the IEEE802.3af standards, the PD must operate from 36V to account for a potential 8V line drop across the impedance of the network during inrush (400mA max current x 20Ω line- impedance). The UVLO must allow a 44V max turn- on and a 30V minimum turn off. A PD device may draw a maximum power of 12.95W. The maximum power that can be expected is limited by the 20Ω line resistance carrying the 350mA current to the PD at the minimum input voltage of 44V (power delivered is 12.95W [{44 – (20*0.35)}*0.35]. Below are of the major features of HV110, some of which are usually found only in PSE devices. Provides an internal current limit for inrush, normal operation and overload conditions. Limits the input current to less than 10µA that will not interfere with Discovery from 2.6V to 10V (with Zener as shown in Figure 1). Meets the turn-on and turn-off thresholds for the PD device & has a built-in 8V hysteresis (with PNP transistor as shown in Figure 10). Protects the device from thermal run away, with thermal shut down and built in 9 sec restart timer. UVLO & POR provides hot-swapping/de-bounce capabilities and inrush current limit. PWRGD (active LOW) provides enable signal to DC/DC converter. Complies with the timing requirements for IEEE 802.3af standard. Classification can be easily implemented, as shown in Figure 9. In addition to operating as a PD controller, HV110 can function as a redundant protective element to assure reliable operation and compliance to IEEE802.3af standard for the PD, even in cases where the PD is powered from an auxiliary power source, as shown in Figure 11. Thermal Shutdown HV110 is designed with a built in Thermal Shutdown feature to assure higher levels of reliability. It will shutdown if the temperature on the die reaches 140°C and will try to restart when the temperature drops to 120°C. Auto Restart Any fault condition will cause the device to shut down and enable a 9 second auto-restart timer. This will occur indefinitely and is strong protection against PSE error when the HV110 is used in PD applications. Note that a 9 second auto-restart will disconnect the PD due to under current conditions, and will also turn off the PSE, since the PSE will not see the minimum current for greater than a period of 400ms (350ms nominal). PWRGD The PWRGD (active low) pin is an open drain active low MOSFET, (referred to VNN) which is enabled when the gate voltage on the internal power MOSFET reaches its full on voltage, provided that the slew rate (Vslew) timeout for large capacitor is not being used. Any fault condition will return PWRGD to a high impedance state, turning off the HV110 and the DC/DC converter. The PSE will also detect an undercurrent condition for a period greater than 350ms (nominal), and will shut down by itself. It will then wait for the next Discovery cycle. Programmable UVLO and Hysteresis ULVO is internally set through a 2.5Mohm and 116K resistance divider in HV110. The default values of UVLO are given in the Electrical Characteristics on Page 2. The UVLO circuit has a built in Hysteresis of 8V, to enable stable operation during a UV condition. See the section on Signature Detection for further details. Internal MOSFET with Current Mirror HV110 includes an internal 90V, 1ohm MOSFET. The MOSFET current is mirrored to a current detect circuit within the chip, utilizing a proprietary Supertex algorithm and wastes almost no power. Elimination of a sense resistor necessary with external power switches means additional energy savings, providing higher power output. Use of an on-board FET and the thermal supervisor also leads to high reliability compared to ICs that use external FETs whose temperatures cannot be easily monitored. PD Polarity According to IEEE802.3af, PD shall be insensitive to the polarity of the power supply and shall be able to operate in Mode A and Mode B (cases when the power is transferred through the signal leads and
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the pins can be different for Mode A. case with active loads like DC-DC converters). the use of the HV110’s internal UV circuit. PWRGD pin will be pulled low, to the negative rail. Figure 4 shows the turn on sequence of the HV110. maximum value of 350mA (nominal). During regular operation a fault condition can occur. Figure 4. Turn-on waveforms of the HV110 Figure 4. PD current jumps from 200mA to 400mA, Figure 5. PD Current jumps from 200mA to 400mA,
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and that they fulfill the IEEE802.3af compliance. and that they fulfill the IEEE802.3af compliance. Figure 7. Undercurrent shutdown when current falls Figure 6. Auto-restart into a shorted output Figure 8. HV110 turning on into a 300uF Cport,
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Table 3. Rclass for different classes of PD Figure 9. Classification Circuit with HV110
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undervoltage thresholds can be utilized. Discovery stage, the input voltage is less than 10V. hence there is no base current to the PNP transistor. Figure 10. Powering HV110 using a PNP transistor instead of a zener
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PD will still operate correctly. Figure 11. Powering HV110 from an Auxiliary power source most current databook or to the Legal/Disclaimer page on the Supertex website. 2004 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
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Telephone: (408) 222-8888 ¥ Fax: (408) 222-4895 Doc. #: DSPD-5TO252K4 A051804