HT0440_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► ±400V input to output isolation ► ±700V isolation between outputs ► No external voltage supply required ► Dual isolated output drivers ► Option of internal or external clock

Applications

► Telecommunications ► Modems ► Solid state relays ► High side switches ► High end audio switches ► Avionics ► ATE General Description The Supertex HT0440 is a dual, high voltage, isolated MOSFET driver utilizing Supertex’s proprietary HVCMOS ® technology. It is designed to drive discrete MOSFETs configured as bidirectional or unidirectional switches. It can drive N-channel MOSFETs as high-side switches up to 400V. The HT0440 generates two independent DC isolated voltages to the outputs, V OUTA and VOUTB when logic inputs A and B are at logic high. The internal clock of the HT0440 can be disabled by applying an external clock signal to the CLK pin. This allows the power dissipation and AC characteristics to be tailored to meet specific needs. The CLK pin should be connected to ground when not in use. The HT0440 does not require any external power supplies, the internal supply voltage is supplied by either of the two logic inputs, A or B, when they are at logic high. For detailed circuit application information, please refer to application note AN-D26. Block Diagram Dual, High Voltage, Isolated MOSFET Driver VOUTB CLK A B GND Isolation Barrier 10R R R R R 10R R = 158kΩ ± 47% Driver A Driver B Logic & Internal Clock VOUTA

Supertex inc. www.supertex.com Doc.# DSFP-HT0440 D040313

Ordering Information

Part Number Package Options Packing HT0440K6-G 10-Lead (3x4) DFN 3000/Reel HT0440LG-G 8-Lead SOIC (Narrow Body) 2500/Reel Absolute Maximum Ratings Parameter Value Input to output isolation voltage, VISO ±400V Logic input voltage, VA, VB -0.5 to +7.0V Maximum junction temperature +125°C Storage temperature -55°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configurations Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW HT04 LLLL 8-Lead SOIC (Narrow Body) (top view) 8-Lead SOIC (Narrow Body Recommended Operating Conditions Sym Parameter Min Typ Max Units Conditions CLK External clock frequency 0.5 - 2.0 MHz --- VIHCLK Clock input high voltage 3.15 - 5.5 V --- VILCLK Clock input low voltage 0 - 0.5 V --- VIH Logic input high voltage 3.15 - 5.5 V --- VIL Logic input low voltage 0 - 0.5 V --- TA Operating temperature -40 - +85 OC --- Package may or may not include the following marks: Si or 10-Lead DFN 10-Lead DFN (top view) 0440 YWLL Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or A CLK -VOUTA +VOUTA B GND -VOUTB +VOUTB A CLK NC -VOUTA +VOUTA GND B GND NC OUTB +VOUTB Typical Thermal Resistance Package θja 10-Lead DFN 40OC/W 8-Lead SOIC (Narrow Body) 101OC/W -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-HT0440 D040313 Truth Table A B CLK VOUTA VOUTB Internal Clock 0 0 0 OFF OFF OFF 0 0 OFF ON ON 0 0 ON OFF ON 1 1 0 ON ON ON 0 0 CLK OFF OFF OFF

0 CLK OFF ON OFF

0 CLK ON OFF OFF

Sym Parameter Min Typ Max Units Conditions IHA + IHB Total logic high input current - - 300 µA VA = 3.5V, VB = 3.5V, CLK = 0V - - 500 µA VA = 3.5V, VB = 3.5V, CLK = 500kHz - - 2.0 mA VA = 3.5V, VB = 3.5V, CLK = 2.0MHz - - 1.0 mA VA = 5.5V, VB = 5.5V, CLK = 0V - - 2.0 mA VA = 5.5V, VB = 5.5V, CLK = 500kHz VOUTA, VOUTB Output voltage CLK = 0V, no load CLK = 500kHz, no load CLK = 2.0MHz, no load CLK = 0V, no load CLK = 500KHz, no load IILA Logic low input A current - - 10 µA VA = 0.5V, VB = high IILB Logic low input B current - - 10 µA VA = high, VB = 0.5V IILQ Quiescent current - - 10 µA VA = 0.5V, VB = 0.5V VISO Input to output isolation voltage ±400 - - V --- VCISO Output to output isolation voltage ±700 - - V --- Sym Parameter Min Typ Max Units Conditions td(ON) Turn-ON delay time - - 50 µs See timing diagram and test circuit CLK = 0V, CL = 600pF t r Rise time - - 650 µs td(OFF) Turn-OFF delay time - - 150 µs tf Fall time - - 3.0 ms

Supertex inc. www.supertex.com Doc.# DSFP-HT0440 D040313 Test Circuit VOUTA CL = 600pF VOUTB 4.5V HT0440 VOUTA + A B VOUTB + CLK GND - CL = 600pF 90% 10% 50% 50% 90% 10% 4.5V VA, VB VOUTA, VOUTB td(ON) tr td(OFF) tf Timing Diagram

Supertex inc. www.supertex.com Doc.# DSFP-HT0440 D040313 10-Lead DFN Package Outline (K6) 3.00x4.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 b D D2 E E2 e L L1 θ Dimension (mm) 0.50 BSC 0.30 0.00 0O Drawings not to scale. Supertex Doc. #: DSPD-10DFNK63X4P050, Version A072611 Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Seating Plane θ Top View Side View Bottom View A D E eb L View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Pin #1 ID R = 0.20 V iew B Note 1 (Index Area D/2 x E/2)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HT0440 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HT0440 D040313 8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Seating Plane Gauge Plane L L2EE1 D e b A A2 Seating Plane A A Top View Side View View B View B θ Note 1 (Index Area D/2 x E1/2) View A-A h h Note 1 Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.