HSNT-8

ABLIC Inc.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00

Manufacturer: ABLIC Inc.

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© ABLIC Inc., 2021-2022 Rev.2.2_00 www.ablic.com This IC is a protection IC for lithium-ion / lithium polymer rechargeable batteries, which includes high-accuracy voltage detection circuits and delay circuits. It is suitable for protec ting 2-serial-cell lithium-ion / lithium polymer rechargeable b attery packs from overcharge, overdischarge, and overcurrent. Use of an external overcurrent detection re sistor enables this IC to provide high- accuracy overcurrent protection with less impact from temperature changes. The S-82A2A/C Series has an input pin for charge-discharge control signal (CTL pin), allowing for charge-discharge control with an external signal. The S-82A2B Series has an input pin for power-saving signal (PS pin), allowing for reduction of current consumption by using an external signal to start the power-saving function.  Features

High-accuracy voltage detection circuit Overcharge detection voltage n 3.500 V to 4.800 V (5 mV step) Accuracy ±15 mV Overcharge release voltage n 3.100 V to 4.800 V *1 Accuracy ±50 mV Overdischarge detection voltage n 2. 000 V to 3.000 V (10 mV step) Accuracy ±50 mV Overdischarge release voltage n 2.000 V to 3.400 V *2 Accuracy ±75 mV Discharge overcurrent 1 detection voltage 3 mV to 100 mV (0.5 mV step) Accuracy ±1.0 mV Discharge overcurrent 2 detection voltage 10 mV to 100 mV (1 mV step) Accuracy ±3 mV Load short-circuiting detection voltage 20 mV to 100 mV (1 mV step) Accuracy ±5 mV Charge overcurrent detection voltage −100 mV to −3 mV (0.5 mV step) Accuracy ±1.0 mV
Detection delay times are generated only by an internal circuit (external capacitors are unnecessary).
Charge-discharge control function (S-82A2A/C Series) CTL pin control logic: Active "H", active "L" CTL pin internal resistance connection: Pull-up, pull-down CTL pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step)
Power-saving function (S-82A2B Series) PS pin control logic: Active "H", active "L" PS pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step)
0 V battery charge: Enabled, inhibited
Power-down function: S-82A2A/C Series: Available, unavailable S-82A2B Series: Available
High-withstand voltage: VM pin and CO pin: Absolute maximum rating 28 V
Wide operation temperature range: Ta = −40°C to +85°C
Low current consumption During operation: 3.0 μA typ., 6.0 μA max. (Ta = +25°C) During power-down: 50 nA max. (Ta = +25°C) During overdischarge: 1.0 μA max. (Ta = +25°C) During power-saving (S-82A2B Series): 50 nA max. (Ta = +25°C)
Lead-free (Sn 100%), halogen-free *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.) *2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage (Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.) Remark n = 1, 2  Applications
Lithium-ion rechargeable battery pack
Lithium polymer rechargeable battery pack  Packages
SNT-8A
HSNT-8(1616)

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Block Diagram 1. S-82A2A/C Series Control logic Delay circuit Oscillator CO DO Overcharge detection comparator 1 Overdischarge detection comparator 1 Load short-circuiting detection comparator Charge overcurrent detection comparator Discharge overcurrent 2 detection comparator Pull-up / pull-down selection circuit Charger detection comparator Overdischarge detection comparator 2 Overcharge detection comparator 2 Discharge overcurrent 1 detection comparator VINI VC VDD VM VSS CTL Figure 1

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 2. S-82A2B Series Control logic Delay circuit Oscillator CO DO Overcharge detection comparator 1 Overdischarge detection comparator 1 Load short-circuiting detection comparator Charge overcurrent detection comparator Pull-up / pull-down selection circuit Charger detection comparator Overdischarge detection comparator 2 Overcharge detection comparator 2 VINI VC VDD VM VSS PS Discharge overcurrent 2 detection comparator Discharge overcurrent 1 detection comparator Figure 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Product Name Structure 1. Product name S-82A2 x xx - xxxx U 7 Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 I8T1: SNT-8A, Tape A8T2: HSNT-8(1616), Tape Serial code Sequentially set from AA to ZZ Product type A: Charge-discharge control function (pin configuration 1 *3) B: Power-saving function C: Charge-discharge control function (pin configuration 2 *3) *1. Refer to the tape drawing. *2. Refer to "3. Product name list ". *3. Refer to " Pin Configuration". 2. Package Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD HSNT-8(1616) PY008-A-P-SD PY008-A-C-SD PY008-A-R-SD PY008-A-L-SD

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 3. Product name list 3. 1 S-82A2A Series 3. 1. 1 SNT-8A Table 2 (1 / 3) Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent 1 Detection Voltage [VDIOV1] Discharge Overcurrent 2 Detection Voltage [VDIOV2] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Table 2 (2 / 3) Product Name Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent 1 Detection Delay Time [tDIOV1] Discharge Overcurrent 2 Detection Delay Time [tDIOV2] Load Short- circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Charge-discharge Inhibition Delay Time [tCTL] S-82A2AAA-I8T1U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 48 ms Table 2 (3 / 3) Product Name CTL Pin Control Logic*1 CTL Pin Internal Resistance Connection*2 CTL Pin Internal Resistance Value*3 [RCTL] CTL Pin Voltage "H"*4 [VCTLH] CTL Pin Voltage "L"*5 [VCTLL]

0 V Battery

Charge*6 Power-down Function*7 S-82A2AAA-I8T1U7 Active "H" Pull-down 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Available *1. CTL pin control logic: Active "H", active "L" *2. CTL pin internal resistance connection: Pull-up, pull-down *3. CTL pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step) *4. CTL pin voltage "H": V SS + 0.75 V, VDD − 0.90 V *5. CTL pin voltage "L": V SS + 0.70 V, VDD − 0.95 V *6. 0 V battery charge: Enabled, inhibited *7. Power-down function: Available, unavailable Remark 1. Please contact our sales representatives for products other than the above. 2. The delay times can be changed within the range listed in Table 7. For details, please contact our sales representatives.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 3. 1. 2 HSNT-8(1616) Table 3 (1 / 3) Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent 1 Detection Voltage [VDIOV1] Discharge Overcurrent 2 Detection Voltage [VDIOV2] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Table 3 (2 / 3) Product Name Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent 1 Detection Delay Time [tDIOV1] Discharge Overcurrent 2 Detection Delay Time [tDIOV2] Load Short- circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Charge-discharge Inhibition Delay Time [tCTL] S-82A2AAA-A8T2U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 48 ms S-82A2AAF-A8T2U7 1.0 s 64 ms 128 ms − 280 μs 16 ms 48 ms Table 3 (3 / 3) Product Name CTL Pin Control Logic*1 CTL Pin Internal Resistance Connection*2 CTL Pin Internal Resistance Value*3 [RCTL] CTL Pin Voltage "H"*4 [VCTLH] CTL Pin Voltage "L"*5 [VCTLL] Charge*6 Power-down Function*7 S-82A2AAA-A8T2U7 Active "H" Pull-down 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Available S-82A2AAF-A8T2U7 Active "H" Pull-down 5 MΩ V DD − 0.90 V V SS + 0.70 V Inhibited Unavailable *1. CTL pin control logic: Active "H", active "L" *2. CTL pin internal resistance connection: Pull-up, pull-down *3. CTL pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step) *4. CTL pin voltage "H": V SS + 0.75 V, VDD − 0.90 V *5. CTL pin voltage "L": V SS + 0.70 V, VDD − 0.95 V *6. 0 V battery charge: Enabled, inhibited *7. Power-down function: Available, unavailable Remark 1. Please contact our sales representatives for products other than the above. 2. The delay times can be changed within the range listed in Table 7. For details, please contact our sales representatives.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 3. 2 S-82A2B Series 3. 2. 1 SNT-8A Table 4 (1 / 3) Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent 1 Detection Voltage [VDIOV1] Discharge Overcurrent 2 Detection Voltage [VDIOV2] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Table 4 (2 / 3) Product Name Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent 1 Detection Delay Time [tDIOV1] Discharge Overcurrent 2 Detection Delay Time [tDIOV2] Load Short- circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Power-saving Delay Time [tPS] S-82A2BAA-I8T1U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 2 ms Table 4 (3 / 3) Product Name PS Pin Control Logic*1 PS Pin Internal Resistance Value*2 [RPS] PS Pin Voltage "H"*3 [VPSH] PS Pin Voltage "L"*4 [VPSL] Charge*5 S-82A2BAA-I8T1U7 Active "H" 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited *1. PS pin control logic: Active "H", active "L" *2. PS pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step) *3. PS pin voltage "H": V SS + 0.75 V, VDD − 0.90 V *4. PS pin voltage "L": V SS + 0.70 V, VDD − 0.95 V *5. 0 V battery charge: Enabled, inhibited Remark 1. Please contact our sales representatives for products other than the above. 2. The delay times can be changed within the range listed in Table 7. For details, please contact our sales representatives.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 3. 2. 2 HSNT-8(1616) Table 5 (1 / 3) Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent 1 Detection Voltage [VDIOV1] Discharge Overcurrent 2 Detection Voltage [VDIOV2] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Table 5 (2 / 3) Product Name Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent 1 Detection Delay Time [tDIOV1] Discharge Overcurrent 2 Detection Delay Time [tDIOV2] Load Short- circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Power-saving Delay Time [tPS] S-82A2BAA-A8T2U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 2 ms Table 5 (3 / 3) Product Name PS Pin Control Logic*1 PS Pin Internal Resistance Value*2 [RPS] PS Pin Voltage "H"*3 [VPSH] PS Pin Voltage "L"*4 [VPSL] Charge*5 S-82A2BAA-A8T2U7 Active "H" 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited *1. PS pin control logic: Active "H", active "L" *2. PS pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step) *3. PS pin voltage "H": V SS + 0.75 V, VDD − 0.90 V *4. PS pin voltage "L": V SS + 0.70 V, VDD − 0.95 V *5. 0 V battery charge: Enabled, inhibited Remark 1. Please contact our sales representatives for products other than the above. 2. The delay times can be changed within the range listed in Table 7. For details, please contact our sales representatives.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 3. 3 S-82A2C Series 3. 3. 1 HSNT-8(1616) Table 6 (1 / 3) Product Name Overcharge Detection Voltage [VCU] Overcharge Release Voltage [VCL] Overdischarge Detection Voltage [VDL] Overdischarge Release Voltage [VDU] Discharge Overcurrent 1 Detection Voltage [VDIOV1] Discharge Overcurrent 2 Detection Voltage [VDIOV2] Load Short- circuiting Detection Voltage [VSHORT] Charge Overcurrent Detection Voltage [VCIOV] Table 6 (2 / 3) Product Name Overcharge Detection Delay Time [tCU] Overdischarge Detection Delay Time [tDL] Discharge Overcurrent 1 Detection Delay Time [tDIOV1] Discharge Overcurrent 2 Detection Delay Time [tDIOV2] Load Short- circuiting Detection Delay Time [tSHORT] Charge Overcurrent Detection Delay Time [tCIOV] Charge-discharge Inhibition Delay Time [tCTL] S-82A2CAA-A8T2U7 1.0 s 64 ms 3.0 s 16 ms 280 μs 16 ms 48 ms S-82A2CAB-A8T2U7 1.0 s 64 ms 3.0 s 16 ms 280 μs 16 ms 48 ms Table 6 (3 / 3) Product Name CTL Pin Control Logic*1 CTL Pin Internal Resistance Connection*2 CTL Pin Internal Resistance Value*3 [RCTL] CTL Pin Voltage "H"*4 [VCTLH] CTL Pin Voltage "L"*5 [VCTLL] Charge*6 Power-down Function*7 S-82A2CAA-A8T2U7 Active "H" Pull-down 5 MΩ V DD − 0.90 V V SS + 0.70 V Enabled Unavailable S-82A2CAB-A8T2U7 Active "H" Pull-down 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Unavailable *1. CTL pin control logic: Active "H", active "L" *2. CTL pin internal resistance connection: Pull-up, pull-down *3. CTL pin internal resistance value: 1 M Ω to 10 MΩ (1 MΩ step) *4. CTL pin voltage "H": V SS + 0.75 V, VDD − 0.90 V *5. CTL pin voltage "L": V SS + 0.70 V, VDD − 0.95 V *6. 0 V battery charge: Enabled, inhibited *7. Power-down function: Available, unavailable Remark 1. Please contact our sales representatives for products other than the above. 2. The delay times can be changed within the range listed in Table 7. For details, please contact our sales representatives. Table 7 Delay Time Symbol Selection Range Remark Overcharge detection delay time tCU 256 ms 512 ms 1.0 s − − − Select a value from the left. Overdischarge detection delay time tDL 32 ms 64 ms 128 ms − − − Select a value from the left. Discharge overcurrent 1 detection delay time tDIOV1 8 ms 16 ms 32 ms 64 ms 128 ms 256 ms Discharge overcurrent 2 detection delay time tDIOV2 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms Select a value from the left. Load short-circuiting detection delay time tSHORT 280 μs 530 μs − − − − Select a value from the left. Charge overcurrent detection delay time tCIOV 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms Select a value from the left. Charge-discharge inhibition delay time t CTL 2 ms 4 ms 48 ms 64 ms 128 ms 256 ms Select a value from the left. Power-saving delay time t PS 2 ms 4 ms 48 ms 64 ms 128 ms 256 ms Select a value from the left.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Pin Configuration 1. SNT-8A Figure 3 Table 8 S-82A2A Series (Pin Configuration 1) Pin No. Symbol Description

1 CTL Input pin for charge-discharge control signal

2 VM Input pin for external negative voltage

3 CO Connection pin of char ge control FET gate (CMOS output)

4 DO Connection pin of dischar ge control FET gate (CMOS output)

5 VINI Overcurrent detection pin

6 VSS Input pin for negative power supply,

connection pin for negative voltage of battery 2

7 VC Connection pin for negative voltage of battery 1,

connection pin for positive voltage of battery 2

8 VDD Input pin for positive power supply,

connection pin for positive voltage of battery 1 Table 9 S-82A2B Series Pin No. Symbol Description

1 PS Input pin for powe r-saving signal

connection pin for negative voltage of battery 2 connection pin for positive voltage of battery 2 connection pin for positive voltage of battery 1 Table 10 S-82A2C Series (Pin Configuration 2) Pin No. Symbol Description

5 VSS Input pin for negative power supply,

connection pin for negative voltage of battery 2

6 VINI Overcurrent detection pin

connection pin for positive voltage of battery 2 connection pin for positive voltage of battery 1 Top view

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 2. HSNT-8(1616) Figure 4 Table 11 S-82A2A Series (Pin Configuration 1) Pin No. Symbol Description connection pin for negative voltage of battery 2 connection pin for positive voltage of battery 2 connection pin for positive voltage of battery 1 Table 12 S-82A2B Series Pin No. Symbol Description connection pin for negative voltage of battery 2 connection pin for positive voltage of battery 2 connection pin for positive voltage of battery 1 Table 13 S-82A2C Series (Pin Configuration 2) Pin No. Symbol Description connection pin for negative voltage of battery 2 connection pin for positive voltage of battery 2 connection pin for positive voltage of battery 1 *1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VDD. However, do not use it as the function of electrode. Top view Bottom view

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Absolute Maximum Ratings Table 14 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin V DS VDD VSS − 0.3 to VSS + 12 V VC pin input voltage V VC VC VDD − 12 to VDD + 0.3 V VINI pin input voltage V VINI VINI VDD − 12 to VDD + 0.3 V CTL pin input voltage (S-82A2A/C Series) V CTL CTL VDD − 12 to VDD + 0.3 V PS pin input voltage (S-82A2B Series) V PS PS VDD − 12 to VDD + 0.3 V VM pin input voltage V VM VM VDD − 28 to VDD + 0.3 V DO pin output voltage V DO DO VSS − 0.3 to VDD + 0.3 V CO pin output voltage V CO CO VVM − 0.3 to VDD + 0.3 V Operation ambient temperature T opr − − 40 to +85 °C Storage temperature T stg − − 55 to +125 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions.  Thermal Resistance Value Table 15 Item Symbol Condition Min. Typ. Max. Unit Junction-to-ambient thermal resistance*1 θJA SNT-8A Board A − 211 − ° C/W Board B − 173 − ° C/W Board C − − − ° C/W Board D − − − ° C/W Board E − − − ° C/W HSNT-8(1616) Board A − 214 − ° C/W Board B − 172 − ° C/W Board C − − − ° C/W Board D − − − ° C/W Board E − − − ° C/W *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark Refer to "  Power Dissipation" and "Test Board" for details.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Electrical Characteristics 1. Ta = +25°C Table 16 (1 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n VCUn − V CU − 0.015 V CU V CU + 0.015 V 1 Overcharge release voltage n VCLn VCL ≠ VCU V CL − 0.050 V CL V CL + 0.050 V 1 VCL = VCU V CL − 0.020 V CL V CL + 0.015 V 1 Overdischarge detection voltage n VDLn − V DL − 0.050 V DL V DL + 0.050 V 2 Overdischarge release voltage n VDUn VDL ≠ VDU V DU − 0.075 V DU V DU + 0.075 V 2 VDL = VDU V DU − 0.050 V DU V DU + 0.050 V 2 Discharge overcurrent 1 detection voltage VDIOV1 − V DIOV1 − 1 V DIOV1 V DIOV1 + 1 mV 5 Discharge overcurrent 2 detection voltage VDIOV2 − V DIOV2 − 3 V DIOV2 V DIOV2 + 3 mV 2 Load short-circuiting detection voltage VSHORT − V SHORT − 5 V SHORT V SHORT + 5 mV 2 Load short-circuiting 2 detection voltage VSHORT2 − V DD − 1.2 V DD − 0.9 V DD − 0.6 V 2 Charge overcurrent detection voltage VCIOV − V CIOV − 1 V CIOV V CIOV + 1 mV 2 Discharge overcurrent release voltage VRIOV V1 = V2 = 3.4 V V DD − 1.3 V DD − 1.2 V DD − 1.1 V 5

0 V Battery Charge

0 V battery charge starting charger

voltage V0CHA 0 V battery charge enabled 0.7 1.1 1.5 V 4

0 V battery charge inhibition

battery voltage n V0INHn 0 V battery charge inhibited 1.00 1.25 1.40 V 2 Internal Resistance Resistance between VDD pin and VM pin RVMD V1 = V2 = 1.8 V, VVM = 0 V 1000 2500 5000 kΩ 3 Resistance between VDD pin and VM pin 2 RVMD2 S-82A2B Series 12 18 24 k Ω 3 Resistance between VM pin and VSS pin RVMS V1 = V2 = 3.4 V, VVM = 1.0 V 3.5 7 14 k Ω 3 CTL pin internal resistance RCTL S-82A2A/C Series R CTL × 0.5 R CTL R CTL × 2.0 M Ω 3 PS pin internal resistance RPS S-82A2B Series R PS × 0.5 R PS R PS × 2.0 M Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP1 − 1.5 − 10 V − Operation voltage between VDD pin and VM pin VDSOP2 − 1.5 − 28 V − CTL pin voltage "H" VCTLH S-82A2A/C Series VCTLH − 0.3 V CTLH V CTLH + 0.3 V 2 CTL pin voltage "L" VCTLL S-82A2A/C Series VCTLL − 0.3 V CTLL V CTLL + 0.3 V 2 PS pin voltage "H" VPSH S-82A2B Series VPSH − 0.3 V PSH V PSH + 0.3 V 2 PS pin voltage "L" VPSL S-82A2B Series VPSL − 0.3 V PSL V PSL + 0.3 V 2 Remark n = 1, 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 Table 16 (2 / 2) (Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Input Current Current consumption during operation IOPE V1 = V2 = 3.4 V, VVM = 0 V − 3.0 6.0 μA 3 VC pin current IVC V1 = V2 = 3.4 V, VVM = 0 V −0.1 0.0 0.1 μA 3 Current consumption during power-down IPDN V1 = V2 = 1.5 V, VVM = 3.0 V − − 50 nA 3 Current consumption during overdischarge IOPED V1 = V2 = 1.5 V, VVM = 3.0 V − − 1.0 μA 3 Current consumption during power-saving IPS S-82A2B Series − − 50 nA 3 Output Resistance CO pin resistance "H" RCOH − 3 6 12 k Ω 4 CO pin resistance "L" RCOL − 1.5 3 6 k Ω 4 DO pin resistance "H" RDOH − 3.5 7 14 k Ω 4 DO pin resistance "L" R DOL − 1 2 4 kΩ 4 Delay Time Overcharge detection delay time t CU − t CU × 0.7 tCU tCU × 1.3 − 5 Overdischarge detection delay time tDL − t DL × 0.7 tDL tDL × 1.3 − 5 Discharge overcurrent 1 detection delay time tDIOV1 − t DIOV1 × 0.75 tDIOV1 tDIOV1 × 1.25 − 5 Discharge overcurrent 2 detection delay time tDIOV2 − t DIOV2 × 0.7 tDIOV2 tDIOV2 × 1.3 − 5 Load short-circuiting detection delay time tSHORT − t SHORT × 0.7 tSHORT tSHORT × 1.3 − 5 Charge overcurrent detection delay time tCIOV − t CIOV × 0.7 tCIOV tCIOV × 1.3 − 5 Charge-discharge inhibition delay time tCTL S-82A2A/C Series tCTL × 0.7 tCTL tCTL × 1.3 − 5 Power-saving delay time t PS S-82A2B Series tPS × 0.7 tPS tPS × 1.3 − 5

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 2. Ta = −20°C to +60°C*1 Table 17 (1 / 2) (Ta = −20°C to +60°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n VCUn − V CU − 0.020 V CU V CU + 0.020 V 1 Overcharge release voltage n VCLn VCL ≠ VCU V CL − 0.065 V CL V CL + 0.057 V 1 VCL = VCU V CL − 0.025 V CL V CL + 0.020 V 1 Overdischarge detection voltage n VDLn − V DL − 0.060 V DL V DL + 0.055 V 2 Overdischarge release voltage n VDUn VDL ≠ VDU V DU − 0.085 V DU V DU + 0.080 V 2 VDL = VDU V DU − 0.060 V DU V DU + 0.055 V 2 Discharge overcurrent 1 detection voltage VDIOV1 − V DIOV1 − 1.5 V DIOV1 V DIOV1 + 1.5 mV 5 Discharge overcurrent 2 detection voltage VDIOV2 − V DIOV2 − 3 V DIOV2 V DIOV2 + 3 mV 2 Load short-circuiting detection voltage VSHORT − V SHORT − 5 V SHORT V SHORT + 5 mV 2 Load short-circuiting 2 detection voltage VSHORT2 − V DD − 1.3 V DD − 0.9 V DD − 0.5 V 2 Charge overcurrent detection voltage VCIOV − V CIOV − 1.5 V CIOV V CIOV + 1.5 mV 2 Discharge overcurrent release voltage VRIOV V1 = V2 = 3.4 V V DD − 1.3 V DD − 1.2 V DD − 1.1 V 5 voltage V0CHA 0 V battery charge enabled 0.5 1.1 1.7 V 4 battery voltage n V0INHn 0 V battery charge inhibited 1.00 1.25 1.40 V 2 Internal Resistance Resistance between VDD pin and VM pin RVMD V1 = V2 = 1.8 V, VVM = 0 V 500 2500 7000 kΩ 3 Resistance between VDD pin and VM pin 2 RVMD2 S-82A2B Series 8 18 30 k Ω 3 Resistance between VM pin and VSS pin RVMS V1 = V2 = 1.5 V, VVM = 3.0 V 3.5 7 14 k Ω 3 CTL pin internal resistance RCTL S-82A2A/C Series R CTL × 0.25 R CTL R CTL × 3.0 M Ω 3 PS pin internal resistance RPS S-82A2B Series R PS × 0.25 R PS R PS × 3.0 M Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP1 − 1.5 − 10 V − Operation voltage between VDD pin and VM pin VDSOP2 − 1.5 − 28 V − CTL pin voltage "H" VCTLH S-82A2A/C Series VCTLH − 0.4 V CTLH V CTLH + 0.4 V 2 CTL pin voltage "L" VCTLL S-82A2A/C Series VCTLL − 0.4 V CTLL V CTLL + 0.4 V 2 PS pin voltage "H" VPSH S-82A2B Series VPSH − 0.4 V PSH V PSH + 0.4 V 2 PS pin voltage "L" VPSL S-82A2B Series VPSL − 0.4 V PSL V PSL + 0.4 V 2 Remark n = 1, 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 Table 17 (2 / 2) (Ta = −20°C to +60°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Input Current Current consumption during operation IOPE V1 = V2 = 3.4 V, VVM = 0 V − 3.0 7.0 μA 3 VC pin current IVC V1 = V2 = 3.4 V, VVM = 0 V −0.1 0.0 0.1 μA 3 Current consumption during power-down IPDN V1 = V2 = 1.5 V, VVM = 3.0 V − − 100 nA 3 Current consumption during overdischarge IOPED V1 = V2 = 1.5 V, VVM = 3.0 V − − 1.2 μA 3 Current consumption during power-saving IPS S-82A2B Series − − 100 nA 3 Output Resistance CO pin resistance "H" RCOH − 1.5 6 18 k Ω 4 CO pin resistance "L" RCOL − 0.75 3 9 k Ω 4 DO pin resistance "H" RDOH − 1.8 7 21 k Ω 4 DO pin resistance "L" R DOL − 0.5 2 6 kΩ 4 Delay Time Overcharge detection delay time t CU − t CU × 0.6 tCU tCU × 1.4 − 5 Overdischarge detection delay time tDL − t DL × 0.6 tDL tDL × 1.4 − 5 Discharge overcurrent 1 detection delay time tDIOV1 − t DIOV1 × 0.65 tDIOV1 tDIOV1 × 1.35 − 5 Discharge overcurrent 2 detection delay time tDIOV2 − t DIOV2 × 0.6 tDIOV2 tDIOV2 × 1.4 − 5 Load short-circuiting detection delay time tSHORT − t SHORT × 0.6 tSHORT tSHORT × 1.4 − 5 Charge overcurrent detection delay time tCIOV − t CIOV × 0.6 tCIOV tCIOV × 1.4 − 5 Charge-discharge inhibition delay time tCTL S-82A2A/C Series tCTL × 0.6 tCTL tCTL × 1.4 − 5 Power-saving delay time t PS S-82A2B Series tPS × 0.6 tPS tPS × 1.4 − 5 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 3. Ta = −40°C to +85°C*1 Table 18 (1 / 2) (Ta = −40°C to +85°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection Voltage Overcharge detection voltage n VCUn − V CU − 0.045 V CU V CU + 0.030 V 1 Overcharge release voltage n VCLn VCL ≠ VCU V CL − 0.080 V CL V CL + 0.060 V 1 VCL = VCU V CL − 0.050 V CL V CL + 0.030 V 1 Overdischarge detection voltage n VDLn − V DL − 0.060 V DL V DL + 0.060 V 2 Overdischarge release voltage n VDUn VDL ≠ VDU V DU − 0.105 V DU V DU + 0.085 V 2 VDL = VDU V DU − 0.080 V DU V DU + 0.060 V 2 Discharge overcurrent 1 detection voltage VDIOV1 − V DIOV1 − 1.5 V DIOV1 V DIOV1 + 1.5 mV 5 Discharge overcurrent 2 detection voltage VDIOV2 − V DIOV2 − 3 V DIOV2 V DIOV2 + 3 mV 2 Load short-circuiting detection voltage VSHORT − V SHORT − 5 V SHORT V SHORT + 5 mV 2 Load short-circuiting 2 detection voltage VSHORT2 − V DD − 1.4 V DD − 0.9 V DD − 0.3 V 2 Charge overcurrent detection voltage VCIOV − V CIOV − 1.5 V CIOV V CIOV + 1.5 mV 2 Discharge overcurrent release voltage VRIOV V1 = V2 = 3.4 V V DD − 1.3 V DD − 1.2 V DD − 1.1 V 5 voltage V0CHA 0 V battery charge enabled 0.5 1.1 1.7 V 4 battery voltage n V0INHn 0 V battery charge inhibited 1.00 1.25 1.40 V 2 Internal Resistance Resistance between VDD pin and VM pin RVMD V1 = V2 = 1.8 V, VVM = 0 V 500 2500 7000 kΩ 3 Resistance between VDD pin and VM pin 2 RVMD2 S-82A2B Series 8 18 30 k Ω 3 Resistance between VM pin and VSS pin RVMS V1 = V2 = 1.5 V, VVM = 3.0 V 3.5 7 14 k Ω 3 CTL pin internal resistance RCTL S-82A2A/C Series R CTL × 0.25 R CTL R CTL × 3.0 M Ω 3 PS pin internal resistance RPS S-82A2B Series R PS × 0.25 R PS R PS × 3.0 M Ω 3 Input Voltage Operation voltage between VDD pin and VSS pin VDSOP1 − 1.5 − 10 V − Operation voltage between VDD pin and VM pin VDSOP2 − 1.5 − 28 V − CTL pin voltage "H" VCTLH S-82A2A/C Series VCTLH − 0.4 V CTLH V CTLH + 0.4 V 2 CTL pin voltage "L" VCTLL S-82A2A/C Series VCTLL − 0.4 V CTLL V CTLL + 0.4 V 2 PS pin voltage "H" VPSH S-82A2B Series VPSH − 0.4 V PSH V PSH + 0.4 V 2 PS pin voltage "L" VPSL S-82A2B Series VPSL − 0.4 V PSL V PSL + 0.4 V 2 Remark n = 1, 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 Table 18 (2 / 2) (Ta = −40°C to +85°C*1 unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Input Current Current consumption during operation IOPE V1 = V2 = 3.4 V, VVM = 0 V − 3.0 7.0 μA 3 VC pin current IVC V1 = V2 = 3.4 V, VVM = 0 V −0.15 0.0 0.15 μA 3 Current consumption during power-down IPDN V1 = V2 = 1.5 V, VVM = 3.0 V − − 150 nA 3 Current consumption during overdischarge IOPED V1 = V2 = 1.5 V, VVM = 3.0 V − − 1.2 μA 3 Current consumption during power-saving IPS S-82A2B Series − − 150 nA 3 Output Resistance CO pin resistance "H" RCOH − 1.5 6 18 k Ω 4 CO pin resistance "L" RCOL − 0.75 3 9 k Ω 4 DO pin resistance "H" RDOH − 1.8 7 21 k Ω 4 DO pin resistance "L" R DOL − 0.5 2 6 kΩ 4 Delay Time Overcharge detection delay time t CU − t CU × 0.4 tCU tCU × 1.6 − 5 Overdischarge detection delay time tDL − t DL × 0.4 tDL tDL × 1.6 − 5 Discharge overcurrent 1 detection delay time tDIOV1 − t DIOV1 × 0.4 tDIOV1 tDIOV1 × 1.6 − 5 Discharge overcurrent 2 detection delay time tDIOV2 − t DIOV2 × 0.4 tDIOV2 tDIOV2 × 1.6 − 5 Load short-circuiting detection delay time tSHORT − t SHORT × 0.4 tSHORT tSHORT × 1.6 − 5 Charge overcurrent detection delay time tCIOV − t CIOV × 0.4 tCIOV tCIOV × 1.6 − 5 Charge-discharge inhibition delay time tCTL S-82A2A/C Series tCTL × 0.4 tCTL tCTL × 1.6 − 5 Power-saving delay time t PS S-82A2B Series tPS × 0.4 tPS tPS × 1.6 − 5 *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Test Circuits When CTL pin or PS pin control logic is active "H", SW1 and SW3 are turned off, SW2 and SW4 are turned on. When CTL pin or PS pin control logic is active "L", SW1 and SW3 are turned on, SW2 and SW4 are turned off. Caution Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (V CO) and DO pin (VDO) are judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to VVM and the DO pin level with respect to VSS. 1. Overcharge detection voltage, overcharge release voltage (Test circuit 1) Overcharge detection voltage 1 (VCU1) is defined as the voltage V1 at which V CO goes from "H" to "L" when the voltage V1 is gradually increased after setting V1 = V2 = V CU − 0.05 V. Overcharge release voltage 1 (V CL1) is defined as the voltage V1 at which V CO goes from "L" to "H" when setting V2 = 3. 4 V and when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage 1 (VHC1) is defined as the difference between VCU1 and VCL1. Overcharge detection voltage 2 (VCU2), overcharge release voltage 2 (VCL2) and overcharge hysteresis voltage 2 (VHC2) can be determined in the same way. 2. Overdischarge detection voltage, overdischarge release voltage (Test circuit 2) Overdischarge detection voltage 1 (VDL1) is defined as the voltage V1 at which VDO goes from "H" to "L" when the voltage V1 is gradually decreased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. Overdischarge release voltage 1 (VDU1) is defined as the voltage V1 at which V DO goes from "L" to "H" when setting V3 = 0.01 V, V6 = V7 = 0 V and when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage 1 (VHD1) is defined as the difference between VDU1 and VDL1. Overdischarge detection voltage 2 (VDL2), overdischarge release voltage 2 (VDU2) and overdischarge hysteresis voltage 2 (VHD2) can be determined in the same way. 3. Discharge overcurrent 1 detection voltage, discharge overcurrent release voltage (Test circuit 5) Discharge overcurrent 1 detection voltage (V DIOV1) is defined as the voltage V6 at which delay time from when V6 is increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when V DO goes from "H" to "L" is discharge overcurrent 1 detection delay time (tDIOV1). Discharge overcurrent release voltage (VRIOV) is defined as the voltage V3 at which VDO goes from "L" to "H" when setting V3 = 6.8 V, V6 = 0 V and when the voltage V3 is then gradually decreased. When the voltage V3 falls below V RIOV, VDO will go to "H" after 1.0 ms typ. and maintain "H" during load short-circuiting detection delay time (tSHORT). 4. Discharge overcurrent 2 detection voltage (Test circuit 2) Discharge overcurrent 2 detection voltage (V DIOV2) is defined as the voltage V6 at which delay time from when V6 is increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when V DO goes from "H" to "L" is discharge overcurrent 2 detection delay time (tDIOV2). 5. Load short-circuiting detection voltage (Test circuit 2) Load short-circuiting detection voltage (V SHORT) is defined as the voltage V6 at which delay time from when V6 is increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when VDO goes from "H" to "L" is tSHORT. 6. Load short-circuiting 2 detection voltage (Test circuit 2) Load short-circuiting 2 detection voltage (V SHORT2) is defined as the voltage V3 at which delay time from when V3 is increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V to when VDO goes from "H" to "L" is tSHORT.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 7. Charge overcurrent detection voltage (Test circuit 2) Charge overcurrent detection voltage (VCIOV) is defined as the voltage V6 at which delay time from when V6 is decreased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V to when VCO goes from "H" to "L" is charge overcurrent detection delay time (tCIOV). 8. CTL pin voltage "H", CTL pin voltage "L" (S-82A2A/C Series) (Test circuit 2) 8. 1 CTL pin control logic active "H" The CTL pin voltage "H" (VCTLH) is defined as the voltage V7 at which VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. After that, the CTL pin voltage "L" (V CTLL) is defined as the voltage V7 at which V CO and VDO go from "L" to "H" after V7 is gradually decreased. 8. 2 CTL pin control logic active "L" V CTLL is defined as the voltage difference bet ween the voltage V7 and the voltage V1 + V2 (V1 + V2 − V7) at which VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. After that, VCTLH is defined as V1 + V2 − V7 at which VCO and VDO go from "L" to "H" after V7 is gradually decreased. 9. PS pin voltage "H", PS pin voltage "L" (S-82A2B Series) (Test circuit 2) 9. 1 PS pin control logic active "H" The PS pin voltage "H" (VPSH) is defined as the voltage V7 at which VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. After that, the PS pin voltage "L" (V PSL) is defined as the voltage V7 at which VCO and VDO go from "L" to "H" after V7 is gradually decreased. 9. 2 PS pin control logic active "L" V PSL is defined as the voltage difference bet ween the voltage V7 and the voltage V1 + V2 (V1 + V2 − V7) at which VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. After that, VPSH is defined as V1 + V2 − V7 at which VCO and VDO go from "L" to "H" after V7 is gradually decreased. 10. Current consumption during operation (Test circuit 3) The current consumption during operation (I OPE) is the current that fl ows through the VDD pin (I DD) under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. However, the current fl owing through the CTL pin or the PS pin internal resistance is excluded. 11. VC pin current (Test circuit 3) The VC pin current (I VC) is the current that flows through the VC pin unde r the set conditions of V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 12. Current consumption during power-down, current consumption during overdischarge (Test circuit 3) 12. 1 With power-down function The current consumption during power-down (IPDN) is IDD under the set conditions of V1 = V2 = 1.5 V, V3 = 3.0 V, V6 = V7 = 0 V. 12. 2 Without power-down function The current consumption during overdischarge (I OPED) is IDD under the set conditions of V1 = V2 = 1.5 V, V3 = 3.0 V, V6 = V7 = 0 V. 13. Current consumption during power-saving (S-82A2B Series) (Test circuit 3) The current consumption during power-saving (IPS) is IDD under the set conditions of V1 = V2 = 3.4 V, V3 = 6.8 V, V6 = 0 V, V7 = 6.8 V. 14. Resistance between VDD pin and VM pin (Test circuit 3) RVMD is the resistance between VDD pin and VM pin under the set conditions of V1 = V2 = 1.8 V, V3 = V6 = V7 = 0 V. 15. Resistance between VDD pin and VM pin 2 (S-82A2B Series) (Test circuit 3) RVMD2 is the resistance between VDD pin and VM pin under the se t conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7 = 6.8 V. 16. Resistance between VM pin and VSS pin (Test circuit 3) RVMS is the resistance between VM pin and VSS pin when the voltage V6 is decreased to 0 V after setting V1 = V2 = 3.4 V, V3 = V6 = 1.0 V, V7 = 0 V. 17. CTL pin internal resi stance (S-82A2A/C Series) (Test circuit 3) 17. 1 CTL pin internal resi stance connection "pull-up" The CTL pin internal resistance (RCTL) is the resistance between CTL pin and VDD pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. 17. 2 CTL pin internal resist ance connection "pull-down" R CTL is the resistance between CTL pin and VSS pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7 = 6.8 V. 18. PS pin internal resistance (S-82A2B Series) (Test circuit 3) 18. 1 PS pin control logic active "H" The PS pin internal resistance (RPS) is the resistance between PS pin and VDD pin when the voltage V7 is decreased to 3.4 V after setting V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7 = 6.8 V. 18. 2 PS pin control logic active "L" R PS is the resistance between PS pin and VSS pin when the voltage V7 is increased to 3.4 V after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 19. CO pin resistance "H" (Test circuit 4) The CO pin resistance "H" (RCOH) is the resistance between VDD pin and CO pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V4 = 6.4 V. 20. CO pin resistance "L" (Test circuit 4) The CO pin resistance "L" (R COL) is the resistance between VM pin and CO pi n under the set conditions of V1 = V2 = 4.9 V, V3 = V6 = 0 V, V4 = 0.4 V. 21. DO pin resistance "H" (Test circuit 4) The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V5 = 6.4 V. 22. DO pin resistance "L" (Test circuit 4) The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pi n under the set conditions of V1 = V2 = 1.8 V, V3 = V6 = 0 V, V5 = 0.4 V. 23. Overcharge detection delay time (Test circuit 5) After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V1 is increased. The time interval from when the voltage V1 exceeds VCU until VCO goes to "L" is the overcharge detection delay time (tCU). 24. Overdischarge detection delay time (Test circuit 5) After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V1 is decreased. The time interval from when the voltage V1 falls below VDL until VDO goes to "L" is the overdischarge detection delay time (tDL). 25. Discharge overcurrent n detection delay time (Test circuit 5) After setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V, the voltage V6 is increased. The time interval from when the voltage V6 exceeds VDIOVn until VDO goes to "L" is the discharge overcurrent n detection delay time (tDIOVn). 26. Load short-circuiting detection delay time (Test circuit 5) After setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V, the voltage V6 is increased. The time interval from when the voltage V6 exceeds VSHORT until VDO goes to "L" is the load short-circuiting detection delay time (tSHORT). 27. Charge overcurrent detection delay time (Test circuit 5) After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V6 is decreased. The time interval from when the voltage V6 falls below VCIOV until VCO goes to "L" is the charge overcurrent detection delay time (tCIOV). Remark n = 1, 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 28. Charge-discharge inhibition delay time (S-82A2A/C Series) (Test circuit 5) 28. 1 CTL pin control logic active "H" After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage V7 exceeds VCTLH until VCO and VDO go to "L" is the charge-discharge inhibition delay time (tCTL). 28. 2 CTL pin control logic active "L" After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage V1 + V2 − V7 falls below VCTLL until VCO and VDO go to "L" is tCTL. 29. Power-saving delay time (S-82A2B Series) (Test circuit 5) 29. 1 PS pin control logic active "H" After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage V7 exceeds VPSH until VCO and VDO go to "L" is the power-saving delay time (tPS). 29. 2 PS pin control logic active "L" After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage V1 + V2 − V7 falls below VPSL until VCO and VDO go to "L" is tPSL. 30. 0 V battery charge starting charger voltage (0 V battery charge enabled) (Test circuit 4) The 0 V battery charge starting charger voltage (V0CHA) is defined as the absolute value of voltage V3 at which the current flowing through the CO pin (ICO) exceeds 1.0 μA when the voltage V3 is gradually decreased after setting V1 = V2 = V6 31. 0 V battery charge inhibition battery vo ltage n (0 V battery charge inhibited) (Test circuit 2) The 0 V battery charge inhibition battery voltage n (V0INHn) is defined as the voltage Vn at which VCO goes to "L" (VCO = VVM) when the voltage Vn is gradually decreased after setting V1 = V2 = 1.5 V, V3 = −1.0 V, V6 = V7 = 0 V. Remark n = 1, 2

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Operation Remark Refer to "  Battery Protection IC Connection Example". 1. Normal status This IC monitors the voltage of the battery connected between VDD pin and VC pin, VC pin and VSS pin, and the voltage between VINI pin and VSS pin to control charging and discharging. When the battery voltage is in the range from overdischarge detection voltage (V DL) to overcharge detection voltage (VCU), the VINI pin voltage is in the range fr om charge overcurrent detection voltage (V CIOV) to discharge overcurrent 1 detection voltage (VDIOV1), both charge and discharge control FETs are turned on. This status is called the normal status, and in this condition charging and discharging can be carried out freely. Also, for the S-82A2A/C Series, input the voltage that releas es the charge-discharge inhibition status to the CTL pin *1, and for the S-82A2B Series, input the voltage that releases the power-saving status to the PS pin*2. The resistance between VDD pin and VM pin (R VMD), and the resistance bet ween VM pin and VSS pin (R VMS) are not connected in the normal status. *1. Refer to " 6. Charge-discharge inhibiti on status (S-82A2A/C Series) ". *2. Refer to " 7. Power-saving status (S-82A2B Series) ". Caution After the battery is connected, discharging may not be carried out. In this case, this IC returns to the normal status by connecting a charger. 2. Overcharge status 2. 1 V CL ≠ VCU (Product in which overcharge release voltage differs from overcharge detection voltage) When the battery voltage becomes higher than VCU during charging in the normal status and the condition continues for the overcharge detection delay time (tCU) or longer, the charge control FET is turned off and charging is stopped. This status is called the overcharge status. The overcharge status is released in the following two cases. (1) In the case that the VM pin voltag e is lower than 0.35 V typ., this IC re leases the overcharge status when the battery voltage falls below overcharge release voltage (V CL). (2) In the case that the VM pin voltage is equal to or higher than 0.35 V typ., th is IC releases the overcharge status when the battery voltage falls below VCU. When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the Vf voltage of the internal parasitic diode than the VSS pin voltage, because the discharge current flows through the parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than 0.35 V typ., this IC releases the overcharge status when the battery voltage is equal to or lower than VCU. Caution If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below VCU even when a heavy load is connected, discharge overcurrent detection and load short- circuiting detection do not function until the battery voltage falls below VCU. Since an actual battery has an internal impedance of tens of mΩ, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short- circuiting detection function.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 2. 2 V CL = VCU (Product in which overcharge release voltage is the same as overcharge detection voltage) When the battery voltage becomes higher than VCU during charging in the normal status and the condition continues for tCU or longer, the charge control FET is turned off and char ging is stopped. This status is called the overcharge status. In the case that the VM pin voltage is equal to or higher than 0.35 V typ. and the battery voltage falls below V CU, this IC releases the overcharge status. When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the Vf voltage of the internal parasitic diode than the VSS pin voltage, because the discharge current flows through the parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than 0.35 V typ., this IC releases the overcharge status when the battery voltage is equal to or lower than VCU. Caution 1. If the battery is charged to a voltage higher than V CU and the battery voltage does not fall below VCU even when a heavy load is connected, discharge overcurrent detection and load short- circuiting detection do not function until the battery voltage falls below V CU. Since an actual battery has an internal impedance of tens of m Ω, the battery voltage drops immediately after a heavy load that causes overcurrent is connected, and discharge overcurrent detection and load short-circuiting detection function. 2. When a charger is connected after overcharge detection, the overcharge status is not released even if the battery voltage is below V CL. The overcharge status is released when the discharge current flows and the VM pin voltage goes over 0.35 V typ. by removing the charger. 3. Overdischarge status When the battery voltage falls below V DL during discharging in the normal status and the condition continues for the overdischarge detection delay time (t DL) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the overdischarge status. Under the overdischarge status, VDD pin and VM pin are shorted by RVMD in this IC. The VM pin voltage is pulled up by RVMD. When connecting a charger in the overdischarge status, the battery voltage reaches VDL or higher and this IC releases the overdischarge status if the VM pin voltage is below 0 V typ. The battery voltage reaches the overdischarge release voltage (V DU) or higher and this IC releases the overdischarge status if the VM pin voltage is not below 0 V typ. RVMS is not connected in the overdischarge status. 3. 1 With power-down function Under the overdischarge status, when the VM pin voltage is 0.7 V typ. or higher, the power-down function works and the current consumption is reduced to the current consumption during power-down (I PDN). By connecting a battery charger, the power-down function is released when the VM pin voltage is 0.7 V typ. or lower.

When a battery is not connected to a charger and the VM pin voltage ≥ 0.7 V typ., this IC maintains the overdischarge status even when the battery voltage reaches VDU or higher.
When a battery is connected to a charger and 0.7 V typ. > the VM pin voltage > 0 V typ., the battery voltage reaches VDU or higher and this IC releases the overdischarge status.
When a battery is connected to a charger and 0 V typ. ≥ the VM pin voltage, the battery voltage reaches V DL or higher and this IC releases the overdischarge status. 3. 2 Without power-down function Under the overdischarge status, the power-down function does not work even when the VM pin voltage is 0.7 V typ. or higher.
When a battery is not connected to a charger and the VM pin voltage ≥ 0.7 V typ., the battery voltage reaches V DU or higher and this IC releases the overdischarge status.
When a battery is connected to a charger and 0.7 V typ. > the VM pin voltage > 0 V typ., the battery voltage reaches VDU or higher and this IC releases the overdischarge status.
When a battery is connected to a charger and 0 V typ. ≥ the VM pin voltage, the battery voltage reaches V DL or higher and this IC releases the overdischarge status.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 4. Discharge overcurrent status (discharge overcurrent 1, discharge overcurrent 2, load short- circuiting, load short-circuiting 2) 4. 1 Discharge overcurrent 1, discharge overcurrent 2, load short-circuiting When a battery in the normal status is in the status where the VINI pin vo ltage is equal to or higher than V DIOV1 because the discharge current is equal to or higher than the specified value and the status continues for the discharge overcurrent 1 detection delay time (tDIOV1) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the discharge overcurrent status. Under the discharge overcurrent status , VM pin and VSS pin are shorted by R VMS in this IC. However, the VM pin voltage is the VDD pin voltage due to the load as long as the load is connected. When the load is disconnected, VM pin returns to the VSS pin voltage. When the VM pin voltage returns to V RIOV or lower, this IC releases the discharge overcurrent status. RVMD is not connected in the discharge overcurrent status. 4. 2 Load short-circuiting 2 When a battery in the normal status is in the status where a load causing discharge overcurrent is connected, and the VM pin voltage is equal to or higher than VSHORT2 and the status continues for the load short-circuiting detection delay time (tSHORT) or longer, the discharge control FET is turned off and discharging is stopped. Th is status is called the discharge overcurrent status. This IC releases the discharge overcurrent status in the same way as in "4. 1 Discharge overcurrent 1, discharge overcurrent 2, load short-circuiting". 5. Charge overcurrent status When a battery in the normal status is in the status where the VINI pin voltage is equal to or lower than V CIOV because the charge current is equal to or high er than the specified value and the status continues for the charge overcurrent detection delay time (tCIOV) or longer, the charge control FET is turned off and charging is stopped. This status is called the charge overcurrent status. This IC releases the charge overcurrent status when the discharge current flow s and the VM pin voltage is 0.35 V typ. or higher by removing the charger. The charge overcurrent detection does not function in the overdischarge status.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 6. Charge-discharge inhibition status (S-82A2A/C Series) 6. 1 CTL pin control logic active "H" When the CTL pin voltage is equal to or higher than CTL pin voltage "H" (V CTLH) and the status continues for the charge-discharge inhibition delay time (t CTL) or longer, the charge control FET and the discharge control FET are turned off, and charging and discharging are stopped. This status is called the charge-discharge inhibition status. This IC releases charge-discharge inhibition status when the CTL pin voltage is equal to or lower than CTL pin voltage "L" (VCTLL). 6. 2 CTL pin control logic active "L" When the CTL pin voltage is equal to or lower than VCTLL and the status continues for tCTL or longer, the charge control FET and the discharge control FET are turned off, and charging and discharging ar e stopped. This status is called the charge-discharge inhibition status. This IC releases charge-discharge inhibition status when the CTL pin voltage is equal to or higher than V CTLH. 6. 3 CTL pin internal resistance connection 6. 3. 1 CTL pin internal r esistance connection "pull-up" The CTL pin is shorted to the VDD pin by the CTL pin internal resistance (RCTL). 6. 3. 2 CTL pin internal resi stance connection "pull-down" The CTL pin is shorted to the VSS pin by RCTL. When the power-down function works, R CTL is disconnected, and the input current and the output current to the CTL pin are cut off. The charge-discharge control by the CTL pin does not function in the overdischarge status. 7. Power-saving status (S-82A2B Series) 7. 1 PS pin control logic active "H" When the PS pin voltage is equal to or higher than PS pin voltage "H" (VPSH) and the status continues for the power- saving delay time (tPS) or longer, the charge control FET and the discharge control FET are turned off, and charging and discharging are stopped. This status is called the power-saving status. In the power-saving status, PS pin internal resistance (RPS) is shorted to the VDD pin, and the VM pin is pulled-up by resistance between VDD pin and VM pin 2 (RVMD2) and is shorted to the VDD pin, reducing current consumption down to current consumption during power-saving (IPS). When PS pin voltage falls below PS pin voltage "L" (VPSL), power-saving status is released and RPS is shorted to the VSS pin. At this time, RVMD2 is not connected. 7. 2 PS pin control logic active "L" When the PS pin voltage is equal to or lower than V PSL and the status continues for tPS or longer, the charge control FET and the discharge control FET are turned off, and charging and discharging ar e stopped. This status is called the power-saving status. In the power-saving status, R PS is shorted to the VSS pin, and the VM pin is pulled-up by RVMD2 and is shorted to the VDD pin, reducing current consumption down to IPS. When PS pin voltage falls below VPSL, power-saving status is released and RPS is shorted to the VDD pin. At this time, RVMD2 is not connected. When the power-down function works, R PS is disconnected, and the input current and the output current to the PS pin are cut off. The charge-discharge control by the PS pin does not function in the overcharge status and the overdischarge status.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 8. 0 V battery charge enabled This function is used to recharge a connected battery whose voltage is 0 V due to self-discharge. When the 0 V battery charge starting charger voltage (V 0CHA) or a higher voltage is applied between the EB + and EB− pins by connecting a charger, the charge control FET gate is fixed to the VDD pin voltage. When the voltage between the gate and source of the charge control FET becomes equal to or higher than the threshold voltage due to the charger voltage, the c harge control FET is turned on to start charging. At this time, the discharge control FET is off and the charging current flows through the internal parasitic diode in the discharge control FET. When the battery voltage becomes equal to or higher than VDL, this IC returns to the normal status. Caution 1. Some battery providers do not recommend charging for a completely self-discharged lithium-ion rechargeable battery. It depends on the characteristics of the lithium-ion rechargeable battery to be used; therefore, please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge. 2. The 0 V battery charge has higher priority than the charge overcurrent detection function. Consequently, a product in which use of the 0 V battery charge is enabled charges a battery forcibly and the charge overcurrent cannot be detected when the battery voltage is lower than V DL. 9. 0 V battery charge inhibited This function inhibits charging when a battery that is internally short-circuited (0 V battery) is connected. When the battery voltage is the 0 V battery charge inhibition battery voltage (V 0INH) or lower, the charge contro l FET gate is fixed to the EB− pin voltage to inhibit charging. When the battery voltage is V0INH or higher, charging can be performed. Caution Some battery providers do not recommend charging for a completely self-discharged lithium-ion rechargeable battery. It depends on the characteristics of the lithium-ion rechargeable battery to be used; therefore, please ask the battery provider to determine whether to enable or inhibit the 0 V battery charge. 10. Delay circuit The detection delay times are determined by dividing a clock of approximately 4 kHz by the counter. Remark t DIOV1, tDIOV2 and tSHORT start when VDIOV1 is detected. When VDIOV2 or VSHORT is detected over tDIOV2 or tSHORT after the detection of VDIOV1, this IC turns the discharge control FET off within tDIOV2 or tSHORT of each detection. DO pin voltage VINI pin voltage VDD VDD Time VDIOV1 VSS VSS VSHORT tSHORT Time tD 0 ≤ tD ≤ tSHORT Figure 10

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Timing Charts 1. Overcharge detection, overdischarge detection VCUn VDUn (VDLn + VHDn) VDL VCLn (VCUn − VHCn) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Charger connection Load connection Status*1 0.35 V typ. VSS VM pin voltage VDD VEB− VDD VEB− VDIOV1 VSS VINI pin voltage VDD VCIOV Overdischarge detection delay time (tDL) Overcharge detection delay time (tCU) *1. (1): Normal status (2): Overcharge status (3): Overdischarge status Remark 1. The charger is assumed to charge with a constant current. 2. n = 1, 2 Figure 11

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 2. Discharge overcurrent detection VRIOV VDD VSS VCUn VDUn (VDLn + VHDn) VDLn VCLn (VCUn − VHCn) Battery voltage VSS CO pin voltage VDD DO pin voltage VSS Load connection Status*1 VM pin voltage VDD VSHORT VDD VSS VDIOV2 VDIOV1 VINI pin voltage (2) (1) Load short-circuiting detection delay time (tSHORT) Discharge overcurrent 1 detection delay time (tDIOV1) Discharge overcurrent 2 detection delay time (tDIOV2) *1. (1): Normal status (2): Discharge overcurrent status Remark n = 1, 2 Figure 12

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 3. Charge overcurrent detection (2) VDD VSS VDD VSS VDD VSS (3) (1) VEB− VEB− VCUn VDUn (VDLn + VHDn) VDLn VCLn (VCUn − VHCn) (1) (1) (2) Battery voltage DO pin voltage CO pin voltage VM pin voltage Charger connection Load connection Status VDD VSS VCIOV VINI pin voltage VDIOV1 0.35 V typ. Charge overcurrent detection delay time (tCIOV) Overdischarge detection delay time (tDL) Charge overcurrent detection delay time (tCIOV) *1. (1): Normal status (2): Charge overcurrent status (3): Overdischarge status Remark 1. The charger is assumed to charge with a constant current. 2. n = 1, 2 Figure 13

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 4. Charge-discharge inhibition operation (S-82A2A/C Series) VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (1) (1) Charger connection VEB− VEB− VCUn VDUn (VDLn + VHDn) VDLn VCLn (VCUn − VHCn) Battery voltage (2) Load connection (3) (2) VDD VSS CTL pin voltage (Active "H") VDIOV1 (1) VCTLH VCTLL VDD VCTLH VCTLL VSS CTL pin voltage (Active "L") Charge-discharge inhibition delay time (tCTL) Overdischarge detection delay time (tDL) Charge-discharge inhibition delay time (tCTL) *1. (1): Normal status (2): Charge-discharge inhibition status (3): Overdischarge status Remark 1. The charger is assumed to charge with a constant current. 2. n = 1, 2 Figure 14

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 5. Power-saving operation (S-82A2B Series) VDD DO pin voltage VSS VDD VSS CO pin voltage VDD VSS VM pin voltage VCIOV Status*1 (1) (1) Charger connection VEB− VEB− VCUn VDUn (VDLn + VHDn) VDLn VCLn (VCUn − VHCn) Battery voltage (2) Load connection (3) (2) VDD VSS PS pin voltage (Active "H") VDIOV1 (1) VPSH VPSL VDD VPSH VPSL VSS PS pin voltage (Active "L") Power-saving delay time (tPS) Power-saving delay time (tPS) Overdischarge detection delay time (tDL) *1. (1): Normal status (2): Power-saving status (3): Overdischarge status Remark 1. The charger is assumed to charge with a constant current. 2. n = 1, 2 Figure 15

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Battery Protection IC Connection Example DO CO VM FET1 FET2 VSS VINI VDD EB+ BAT1 EB− VC BAT2 External Input CTL / PS Figure 16 Table 19 Constants for External Components Symbol Part Purpose Min. Typ. Max. Remark FET1 N-channel MOS FET Discharge control − − − Threshold voltage ≤ Overdischarge detection voltage*1 FET2 N-channel MOS FET Charge control − − − Threshold voltage ≤ Overdischarge detection voltage*1 R1, R2 Resistor ESD protection, For power fluctuation 100 Ω 100 Ω 150 Ω*2 − C1, C2 Capacitor For power fluctuation 0.068 μF 0.1 μF 1.0 μF − R3 Resistor ESD protection, Protection for reverse connection of a charge r 300 Ω 1.0 k Ω 1.5 k Ω − R4 Resistor Overcurrent detection − 1 m Ω − − R5 Resisto r CTL / PS pin input protection − 1 k Ω − − *1. If a FET with a threshold voltage equal to or higher than the overdischarge detection voltage is used, discharging may be stopped before overdischarge is detected. *2. Accuracy of overcharge detection voltage is guaranteed by R1 = 100 Ω. Connecting resistors with other values will worsen the accuracy. Caution 1. The constants may be changed without notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the connection example. In addition, the connection example and the constants do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constants.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Precautions

The application conditions for the input voltage, output voltage, and load current should not exceed the power dissipation.
Do not apply an electrostatic discharge to this IC that e xceeds the performance ratings of the built-in electrostatic protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connec tion with any infringement by products including this IC of patents owned by a third party.

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Characteristics (Typical Data) 1. Current consumption 1. 1 I OPE vs. Ta 1. 2 I VC vs. Ta 1. 3 I PDN vs. Ta 1. 4 I OPED vs. Ta 1. 5 I OPE vs. VDD 1. 5. 1 With power-down function 1. 5. 2 Without power-down function 1. 6 I PS vs. Ta (S-82A2B Series) 1. 7 I PS vs. VDD (S-82A2B Series) 857550250-40 -25 Ta [°C] IOPE [µA] 857550250-40 -25 Ta [°C] 0.10 -0.10 0.05 0.00 -0.05 IVC [µA] 857550250-40 -25 Ta [°C] 100 IPDN [nA] 857550250-40 -25 Ta [°C] 1.2 0.9 0.6 0.3 IOPED [µA] 1068024 VDD [V] IOPE [µA] 1068024 VDD [V] IOPE [µA] 857550250-40 -25 Ta [°C] 100 IPS [nA] VDD [V] 100 IPS [nA]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 2. Detection voltage, release voltage 2. 1 V CUn vs. Ta 2. 2 V CLn vs. Ta 2. 3 V DLn vs. Ta 2. 4 V DUn vs. Ta 2. 5 V DIOV1 vs. VDD 2. 6 V DIOV1 vs. Ta 2. 7 V DIOV2 vs. VDD 2. 8 V DIOV2 vs. Ta Remark n = 1, 2 857550250-40 -25 Ta [°C] 4.485 4.405 4.465 4.445 4.425VCUn [V] 857550250-40 -25 Ta [°C] 4.375 4.215 4.335 4.295 4.255VCLn [V] 857550250-40 -25 Ta [°C] 2.43 2.27 2.39 2.35 2.31 VDLn [V] 857550250-40 -25 Ta [°C] 2.63 2.47 2.59 2.55 2.51 VDUn [V] VDD [V] VDIOV1 [mV] 857550250-40 -25 Ta [°C] VDIOV1 [mV] VDD [V] VDIOV2 [mV] 857550250-40 -25 Ta [°C] VDIOV2 [mV]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 2. 9 V SHORT vs. VDD 2. 10 V SHORT vs. Ta 2. 11 V CIOV vs. VDD 2. 12 V CIOV vs. Ta VDD [V] VSHORT [mV] 857550250-40 -25 Ta [°C] VSHORT [mV] VDD [V] VCIOV [mV] 857550250-40 -25 Ta [°C] VCIOV [mV]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 3. Delay time 3. 1 t CU vs. Ta 3. 2 t DL vs. Ta 3. 3 t DIOV1 vs. VDD 3. 4 t DIOV1 vs. Ta 3. 5 t DIOV2 vs. VDD 3. 6 t DIOV2 vs. Ta 3. 7 t SHORT vs. VDD 3. 8 t SHORT vs. Ta 857550250-40 -25 Ta [°C] 2.0 1.5 1.0 0.5 tCU [s] 857550250-40 -25 Ta [°C] 120 tDL [ms] VDD [V] tDIOV1 [s] 857550250-40 -25 VDD [V] tDIOV1 [s] VDD [V] tDIOV2 [ms] 857550250-40 -25 VDD [V] tDIOV2 [ms] VDD [V] 560 420 280 140 tSHORT [µs] 857550250-40 -25 Ta [°C] 560 420 280 140 tSHORT [µs]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series 3. 9 t CIOV vs. VDD 3. 10 t CIOV vs. Ta 3. 11 t CTL vs. VDD (S-82A2A/C Series) 3. 12 t CTL vs. Ta (S-82A2A/C Series) 3. 13 t PS vs. VDD (S-82A2B Series) 3. 14 t PS vs. Ta (S-82A2B Series) VDD [V] tCIOV [ms] 857550250-40 -25 Ta [°C] tCIOV [ms] VDD [V] tCTL [ms] 857550250-40 -25 Ta [°C] tCTL [ms] VDD [V] tPS [ms] 857550250-40 -25 Ta [°C] tPS [ms]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00 4. Output resistance 4. 1 R COH vs. VCO 4. 2 R COL vs. VCO 4. 3 R DOH vs. VDO 4. 4 R DOL vs. VDO 129036 VCO [V] RCOH [kΩ] 129036 VCO [V] 10.0 7.5 5.0 2.5 RCOL [kΩ] 129036 VDO [V] RDOH [kΩ] 129036 VDO [V] 6.0 4.5 3.0 1.5 RDOL [kΩ]

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00 S-82A2A/B/C Series  Marking Specifications 1. SNT-8A (1): Blank (2) to (4): Produc t code (Refer to Product name vs. Product code ) (5), (6): Blank (7) to (11): Lot numbe r Product name vs. Product code 1. 1 S-82A2A Series 1. 2 S-82A2B Series Product Name Product Code Product Name Product Code S-82A2AAA-I8T1U7 9 D A S-82A2BAA-I8T1U7 9 D H 2. HSNT-8(1616) (1): Blank (2) to (4): Produc t code (Refer to Product name vs. Product code ) (5) to (7): Lot numbe r Product name vs. Product code 2. 1 S-82A2A Series 2. 2 S-82A2B Series Product Name Product Code Product Name Product Code S-82A2AAA-A8T2U7 9 D A S-82A2BAA-A8T2U7 9 D H S-82A2AAF-A8T2U7 9 D J 2. 3 S-82A2C Series Product Name Product Code (2) (3) (4) S-82A2CAA-A8T2U7 9 D B S-82A2CAB-A8T2U7 9 D D Top view 14 32 85 67 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Top view 14 32 (1) (2) (3) (4) (5) (6) (7)

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK S-82A2A/B/C Series Rev.2.2_00  Power Dissipation Board Power Dissipation (P D) Board Power Dissipation (P D) A 0.47 W A 0.47 W B 0.58 W B 0.58 W C − C − D − D − E − E − 0 25 50 75 100 125 150 1750.0 0.2 0.4 0.6 0.8 1.0 Ambient temperature (Ta) [°C] Power dissipation (PD) [W] Tj = +125°C max. SNT-8A B A 0 25 50 75 100 125 150 1750.0 0.2 0.4 0.6 0.8 1.0 Ambient temperature (Ta) [°C] Power dissipation (PD) [W] Tj = +125°C max. HSNT-8(1616) B A

(1) (2) Board A Item Specification Size [mm] 114.3 x 76.2 x t1.6 Material FR-4 Number of copper foil layer 2 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 74.2 x 74.2 x t0.070 Thermal via - Board B Item Specification Size [mm] 114.3 x 76.2 x t1.6 Thermal via - Material FR-4 Number of copper foil layer 4 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 IC Mount Area SNT-8A Test Board No. SNT8A-A-Board-SD-1.0 ABLIC Inc.

(1) (2) Thermal via - Material FR-4 Number of copper foil layer 4 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 Thermal via - Board B Item Specification Size [mm] 114.3 x 76.2 x t1.6 Number of copper foil layer 2 Copper foil layer [mm] Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 Board A Item Specification Size [mm] 114.3 x 76.2 x t1.6 Material FR-4 IC Mount Area HSNT-8(1616) Test Board No. HSNT8-B-Board-SD-1.0 ABLIC Inc.

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Disclaimers (Handling Precautions) 1. All the information described herein (product data, specific ations, figures, tables, programs, algorithms and application circuit examples, et c.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by the reasons other than the products described herein (hereinafter "the products") or infringement o f third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, co nfirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchang e and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing o r exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who i ntends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any devi ce or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction w ith some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent acci dents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The ne cessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. H owever, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fractu re surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of t he products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright informa tion and know-how of ABL IC Inc. The information described herein does not convey any license under any intellec tual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the inf ormation from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Ja panese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com

Product Information

HSNT-8 specifications and overview.

Summary

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00

Description

BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK Rev.2.2_00

Source title HSNT-8 Datasheet(PDF) - ABLIC Inc.

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