AOD5N50 AOSMD | Alldatasheet
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500V,5A N-Channel MOSFET General Description Product Summary 600V@150℃ ID (at VGS=10V) 5A RDS(ON) (at VGS=10V) < 1.6Ω 100% UIS Tested! 100% Rg Tested! Symbol VDS VGS IDM IAR EAR EAS Peak diode recovery dv/dt dv/dt TJ, TSTG TL Symbol RθJA RθCS RθJC Maximum Junction-to-Ambient A,G TC=25°C Maximum Thermal Characteristics Units °C/W43 Parameter Typical W W/ oC Maximum lead temperature for soldering purpose, 1/8" from case for 5 seconds 300 °C Junction and Storage Temperature Range -50 to 150 °C Power Dissipation B PD V±30Gate-Source Voltage TC=100°C A ID TC=25°C 5 3.1 The AOD5N50 is fabricated using an advanced high voltage MOSFET process that is designed to deliver high levels of performance and robustness in popular AC-DC applications.By providing low R DS(on), Ciss and Crss along with guaranteed avalanche capability this device can be adopted quickly into new and existing offline power supply designs. V DS V UnitsParameter Absolute Maximum Ratings TA=25°C unless otherwise noted Maximum Drain-Source Voltage 500 17Pulsed Drain Current C Continuous Drain CurrentB mJ Avalanche Current C 118Repetitive avalanche energy C Derate above 25oC 104 0.83 A2.8 Single plused avalanche energy H 235 mJ V/ns5 Maximum Case-to-sink A Maximum Junction-to-CaseD,F °C/W °C/W 0.5 1.2 G D S G S D G S D Top View TO252 DPAK Bottom View Rev0: June 2010 Page 1 of 6
/∆TJ 0.6 V/ oC IGSS Gate-Body leakage current ±100 nΑ VGS(th) Gate Threshold Voltage 3.4 4.1 4.5 V RDS(ON) 1.2 1.6 Ω gFS 5S VSD 0.76 1 V IS Maximum Body-Diode Continuous Current 5 A ISM 17 A Ciss 430 538 670 pF Coss 40 58 80 pF Crss 2.5 4.5 7 pF Rg 1.2 2.3 3.5 Ω Qg 9 11.5 14 nC Qgs 3 3.8 4.6 nC Qgd 2 4.1 6.2 nC tD(on) 18 ns tr 32 ns tD(off) 34 ns tf 22 ns trr 145 182 220 ns Qrr 1.7 2.2 2.7 µC THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Drain-Source Breakdown Voltage ID=250µA, VGS=0V, TJ=25°C ID=250µA, VGS=0V, TJ=150°C Body Diode Reverse Recovery Charge IF=5A,dI/dt=100A/µs,VDS=100V Maximum Body-Diode Pulsed Current Input Capacitance Output Capacitance Turn-On DelayTime Turn-On Rise Time Diode Forward Voltage Turn-Off DelayTime VGS=10V, VDS=250V, ID=5A, RG=25Ω Gate resistance V GS=0V, VDS=0V, f=1MHz Turn-Off Fall Time Total Gate Charge VGS=10V, VDS=400V, ID=5AGate Source Charge Gate Drain Charge VDS=5V ID=250µA VDS=400V, TJ=125°C IS=1A,VGS=0V VDS=40V, ID=2.5AForward Transconductance DYNAMIC PARAMETERS Zero Gate Voltage Drain Current ID=250µA, VGS=0V VDS=0V, VGS=±30V IDSS Zero Gate Voltage Drain Current VDS=500V, VGS=0V Electrical Characteristics (TJ=25°C unless otherwise noted) STATIC PARAMETERS Parameter Conditions BVDSS µA V Body Diode Reverse Recovery Time Static Drain-Source On-Resistance V GS=10V, ID=2.5A Reverse Transfer Capacitance IF=5A,dI/dt=100A/µs,VDS=100V VGS=0V, VDS=25V, f=1MHz SWITCHING PARAMETERS A. The value of R θJA is measured with the device in a still air environment with T A =25°C. B. The power dissipation PD is based on TJ(MAX)=150°C in a TO252 package, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of TJ(MAX)=150°C. G.These tests are performed with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA=25°C. H. L=60mH, IAS=2.8A, VDD=150V, RG=10Ω, Starting TJ=25°C Rev0: June 2010 www.aosmd.com Page 2 of 6
Gate Charge Test Circuit & Waveform VD CDUT VddVgs Vds Vgs RL Rg Vgs Vds 10% 90% Resistive Switching Test Circuit & Waveforms tt rd(o n) t on t d(o ff ) t f toff VddVgs Id Vgs Rg DUT VDC L Vgs Vds Id Vgs BV I Unclamped Inductive Switching (UIS) Test Circuit & Waveforms Ig Vgs VD C DUT L Vds Vgs Vds IsdIsd Diode Recovery Tes t Circuit & Waveforms Vds - Vds + IF AR DSS E = 1/2 LI dI/dt IRM rr VddVdd Q = - Idt trr ARAR Rev0: June 2010 www.aosmd.com Page 6 of 6