AOD407_V01 AOSMD | Alldatasheet
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VDS (V) = -60V ID = -12A (VGS = -10V) RDS(ON) < 115mW (VGS = -10V) RDS(ON) < 150mW (VGS = -4.5V) 100% UIS tested 100% RG tested General Description The AOD407 uses advanced trench technology to provide excellent RDS(ON), low gate charge and low gate resistance. With the excellent thermal resistance of the DPAK package, this device is well suited for high current load applications. -RoHS Compliant -Halogen Free* G D S TO252 DPAK TopView Bottom View G G D D S S D Rev.8.0: August 2019 www.aosmd.com Page 1 of 6
-0.003 -1 TJ=55° C -5 IGSS ± 100 nA VGS(th) -1.5 -2.1 -3 V ID(ON) -30 A 91 115 TJ=125° C 150 114 150 mW gFS 12.8 S VSD -0.76 -1 V IS -12 A Ciss 987 pF Coss 114 pF Crss 46 pF Rg 9.5 15 W Qg(10V) 15.8 22 nC Qg(4.5V) 7.4 12 nC Qgs 3 nC Qgd 3.5 nC tD(on) 9 ns tr 10 ns tD(off) 25 ns tf 11 ns trr 27.5 ns Qrr 30 nC THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE Maximum Body-Diode Continuous Current Input Capacitance Output Capacitance Turn-On DelayTime DYNAMIC PARAMETERS VGS=0V, VDS=-30V, f=1MHz Gate Drain Charge Total Gate Charge (10V) VGS=-10V, VDS=-30V, ID=-12A Turn-On Rise Time Turn-Off DelayTime VGS=-10V, VDS=-30V, RL=2.5W, RGEN=3W Gate resistance VGS=0V, VDS=0V, f=1MHz Turn-Off Fall Time SWITCHING PARAMETERS Total Gate Charge (4.5V) Gate Source Charge Forward Transconductance Diode Forward Voltage mW VGS=-4.5V, ID=-8A IS=-1A,VGS=0V VDS=-5V, ID=-12A VDS=0V, VGS=± 20V Zero Gate Voltage Drain Current Gate-Body leakage current RDS(ON) Static Drain-Source On-Resistance IF=-12A, dI/dt=100A/ms Electrical Characteristics (TJ=25° C unless otherwise noted) STATIC PARAMETERS Parameter Conditions IDSS mA Gate Threshold Voltage VDS=VGS ID=-250mA VDS=-48V, VGS=0V Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge IF=-12A, dI/dt=100A/ms Drain-Source Breakdown Voltage On state drain current ID=-250mA, VGS=0V VGS=-10V, VDS=-5V VGS=-10V, ID=-12A Reverse Transfer Capacitance A: The value of R qJA is measured with the device mounted on 1in 2 FR -4 board with 2oz. Copper, in a still air environment with T A =25°C. The Power dissipation PDSM is based on R qJA and the maximum allowed junction temperature of 150 °C. The value in any given application depends on the user's specific board design, and the maximum temperature of 175 °C may be used if the PCB allows it. B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C: Repetitive rating, pulse width limited by junction temperature T J(MAX)=175°C. D. The R qJA is the sum of the thermal impedence from junction to case R qJC and case to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300 ms pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsin k, assuming a maximum junction temperature of T J(MAX)=175°C. G. The maximum current rating is limited by bond -wires. H. These tests are performed with the device mounted on 1 in 2 FR -4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA curve provides a single pulse rating. *This device is guaranteed green after data code 8X11 (Sep 1 ST 2008). Rev.8.0: August 2019 www.aosmd.com Page 2 of 6
Gate Charge Test Circuit & Waveform + - -10V VddVgs Id Vgs Rg DUT VDC Vgs Vds Id Vgs Unclamped Inductive Switching (UIS) Test Circuit & Waveforms Vds L E = 1/2 LIARAR BVDSS I AR Ig Vgs VDC DUT L Vgs Isd Diode Recovery Test Circuit & Waveforms Vds - Vds + dI/dt RM rr VddVdd Q = - Idt trr-Isd -Vds F-I VDCDUT VddVgs Vds Vgs RL Rg Resistive Switching Test Circuit & Waveforms Vgs Vds t t t t t t 90% 10% r on d(off) f off d(on) Rev.8.0: August 2019 www.aosmd.com Page 6 of 6