CW01

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Document overview

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Technical content

Features

► Low phase noise ► 100V open drain N-channel ► High speed D flip-flop ► High speed MOSFET gate driver ► Up to 200MHz clock input ► VDD and VLL undervoltage lockout

Applications

► Diagnostic medical ultrasound ► Fluid flow measurement General Description The Supertex CW01 is a four-channel, low phase noise, continuous wave transmit IC. A high speed D flip-flop is provided to allow the D IN frequency to be aligned to a high frequency clock. The output N-channel is turned on when a logic high is clocked into the D flip-flop. Data are clocked in during the low to high transition. VD1, VD2, VD3 and VD4 are four individual input supply voltages for the N-channel output MOSFET gate drivers. High peak currents are drawn from these gate drives when the output MOSFETs are switching. To minimize jitter caused by voltage ripples, each channel has its own gate drive voltage pin; VD1, VD2, VD3 and VD4. A series ferrite bead and a decoupling capacitor are recommended on each VDX pin to minimize output jitter and channel to channel crosstalk. Both V DD and V LL have undervoltage lockout to prevent spurious turn-on. Typical Application Circuit Four-Channel, Low Phase Noise, Low Power, Continuous Wave Transmitter HVOUT1 PGND1 Translator and Driver VD1VLL 270µH 0.1µF 0.1µF 5.0V 2.5V 2.0 to 5.0MHz 96MHz VD1 VDD OE VLL DIN1 CLK VSS DIN1 CLK BAV99 Tx PZT 8.0V BAV23 (one of four channels)

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Ordering Information

4.00x5.00mm body 1.00mm height (max) 0.50mm pitch CW01 CW01K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VLL, logic supply -0.3 to +6.0V VDD, level translator voltage -0.5 to +6.0V VDX, gate drive voltage -0.5 to +6.0V HVOUT, high voltage output drain voltage -0.5 to 120V Maximum junction temperature +125°C Storage temperature range -65°C to +150°C Power dissipation, TA = 25°C 3.0W1 θja 26.9°C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note: 1. Device mounted on a 4 layer 3” by 4” board. Pin Configuration 24-Lead QFN (K6) (top view) Product Marking 24-Lead QFN (K6) OE VSS VD1 VD2 PGND1 HVOUT1 PGND2 HVOUT2 VSS HVOUT3 PGND3 HVOUT4 VLL VSS VD4 VD3 PGND4 DIN1 DIN2 VDD CLK VSS DIN3 DIN4 Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number A = Assembler ID C = Country of Origin = “Green” Packaging CW01 YWLL AAA CCC Package may or may not include the following marks: Si or

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Symbol Parameter Min Typ Max Unit Test Conditions HVOUT High voltage output 0 - 100 V --- VDD VDD voltage range 4.5 5.0 5.5 V --- tVDD-ON VDD rise time 50 - - µs --- VLL VLL voltage range 1.65 2.5 5.5 V --- tVLL-ON VLL rise time 50 - - µs --- VDIN Logic input voltage range 0 - VLL V --- VDX Gate drive voltage 4.5 5.0 5.5 V --- tVDX-ON VDX rise time 50 - - µs --- IDDQ VDD quiescent current - 63 100 µA --- IDD VDD average current - 23.5 30 mA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active ILLQ VLL quiescent current - 8.1 20 µA --- ILL VLL average current - 380 600 µA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active IDXQ VDX quiescent current - 0 1.0 µA --- IDX VDX average current - 11.3 30 mA fCLK = 200MHz, fOUT = 5.0MHz, all 4-ch active VIH Input logic high voltage 0.8VLL - VLL V --- VIL Input logic low voltage 0 - 0.2VLL V --- IIH Input logic high current - - 1.0 µA --- IIL Input logic high current -1.0 - - µA --- RON Output on resistance - 4.7 7.0 Ω IIN = 100mA ISAT Output saturation current - 0.8 - A VDD = HVOUT = 5.0V IHVleak High voltage output leakage - - 10 µA HVOUT = 100V UVLO_VLL UVLO trip point for VLL - 1.5 - V --- UVLO_VDD UVLO trip point for VDD - 4.0 - V --- TJ Operating junction temperature -40 - +125 °C --- (VDD = VDX =5.0V, VLL = 2.5V, TJ = 25ºC unless otherwise specified)

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com (VDD = VDX =5.0V, VLL = 2.5V, TJ = 25ºC unless otherwise specified) Symbol Parameter Min Typ Max Unit Test Conditions fCLK Clock frequency 0 - 200 MHz - tr, tf Clock rise and fall times - 0.5 5.0 ns - tSU Set-up time, DIN to CLK 2.0 - - ns - tH Hold time, DIN from CLK 1.0 - - ns - tHVf HVOUT fall time - 0.8 - ns Load = 50Ω to 8.0V. See timing diagram tHVr HVOUT rise time - 3.3 - ns Load = 50Ω to 8.0V. See timing diagram t dLH Delay time from CLK to HVOUT from low to high - 5.1 - ns Load = 50Ω to 8.0V. See timing diagram t dHL Delay time from CLK to HVOUT from high to low - 2.6 - ns Load = 50Ω to 8.0V. See timing diagram dLHdelay Delay time matching for tdLH - 0.5 1.0 ns - ∆tdHLdelay Delay time matching for tdHL - 0.5 1.0 ns - tOE(ON) Output enable turn-on time - - 10 µs - tOE(OFF) Output enable turn-off time - - 0.1 µs - COUT Output capacitance - 8.0 - pF At 8.0V - 4.0 - pF At 100V Phase noise Phase noise - -171 -160 dBC/Hz dB below carrier CLK = 80MHz, D IN = 2.0MHz freq offset = 1.0kHz noise bandwidth = 140Hz See test circuit.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Block Diagram VDD VLL OE DIN1 DIN2 DIN3 DIN4 CLK VSS VLL VLL VLL VLL VDD VDD VDD VDD VLL UVLO VDD UVLO DIN1 CLK DIN2 CLK DIN3 CLK DIN4 CLK VD1 HVOUT1 PGND1 VD2 HVOUT2 PGND2 VD3 HV OUT3 PGND3 VD4 HVOUT4 PGND4 SUB Timing Diagram CLK DIN HVOUT tdLH tHVr tHVf tdHL tH tSU 50%5 0% 90%90% 10%1 0% 50%5 0%

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Test Circuits AC Timing Phase Noise HVOUT1 PGND1 HV OUT Translator and Driver VD1VLL 0.1µF 8.0V 0.1µF 0.1µF 5.0V 2.5V DIN CLK VD1 VDD OE VLL DIN1 CLK VSS DIN1 CLK 50Ω (one of four channels) HVOUT1 (one of four channels) PGND1 HVOUT Translator and Driver VD1VLL 0.1µF 50Ω 50Ω 0.1µF 390µH 3.0V 0.1µF 0.1µF 5.0V 2.5V 2.0MHz 80MHz VD1 VDD OE VLL DIN1 CLK VSS DIN1 CLK Typical Performance Curve (Test conditions: VLL = 2.5V, VDD = 5.0V, VD1 = VD2 = VD3 = VD4 = 5.0V, no load) IDD vs DIN Frequency 05 10 15 20 25 Data In Frequency (MHz) IDD (mA) fCLK = 200MHz fCLK = 100MHz fCLK = 50MHz

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Pin Configuration and Description Pin # Function Description 1 DIN1 D flip-flop logic input for HVOUT1. Logic high will turn on output N-channel. 2 DIN2 D flip-flop logic input for HVOUT2. Logic high will turn on output N-channel. 3 VDD Level translator supply. Should be at the same potential as VDX. 4 CLK Logic clock input. 5 VSS Ground. Should be externally shorted to all PGND and VSS pins. 6 DIN3 D flip-flop logic input for HVOUT3. Logic high will turn on output N-channel. 7 DIN4 D flip-flop logic input for HVOUT4. Logic high will turn on output N-channel. 8 VLL Logic input supply voltage. 9 VSS Ground. Should be externally shorted to all PGND and VSS pins. 10 VD4 Gate drive supply voltage for HVOUT4. Should be at the same potential as VDD. 11 VD3 Gate drive supply voltage for HVOUT3. Should be at the same potential as VDD. 12 PGND4 Power ground for HVOUT4. Should be externally shorted to all PGND and VSS pins. 13 HVOUT4 Drain output for HVOUT4. 14 PGND3 Power ground for HVOUT3. Should be externally shorted to all PGND and VSS pins. 15 HVOUT3 Drain output for HVOUT3. 16 VSS Ground. Should be externally shorted to all PGND and VSS pins. 17 HVOUT2 Drain output for HVOUT2. 18 PGND2 Power ground for HVOUT2. Should be externally shorted to all PGND and VSS pins. 19 HVOUT1 Drain output for HVOUT1. 20 PGND1 Power ground for HVOUT1. Should be externally shorted to all PGND and VSS pins. 21 VD2 Gate drive supply voltage for HVOUT2. Should be at the same potential as VDD. 22 VD1 Gate drive supply voltage for HVOUT1. Should be at the same potential as VDD. 23 VSS Ground. Should be externally shorted to all PGND and VSS pins. 24 OE Output enable logic input. Logic low will turn all HVOUT off. Center Pad --- Should be externally shorted to all PGND and VSS pins.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) CW01 Doc.# DSFP-CW01 A011712 24-Lead QFN Package Outline (K6) 4.00x5.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC †0.30 0.00 0O JEDEC Registration MO-220, Variation VGHD-1, Issue K, June 2006 * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-24QFNK64X5P050, Version A101111. Seating Plane Top View Side View Bottom View A D E b L View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) θ Note 1 (Index Area D/2 x E/2) e Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.