AOZ5311NQI AOSMD | Alldatasheet
Document overview
- Manufacturer or author: mina.galvan
- PDF pages: 18
Technical content
Features
2.5V to 20V power supply range 4.5V to 5.5V driver supply range 55A continuous output current - Up to 80A for 10ms on pulse - Up to 120A for 10us on pulse Up to 2MHz switching operation 3V / 5V PWM / Tri-State input compatible Under-Voltage lockout protection SMOD# control for Diode Emulation / CCM operation < 1mV detection threshold for efficient ZCD control Low profile 5x5 QFN-31L package
Applications
Memory and graphic cards VRMs for motherboards Point of load DC/DC converters Video gaming console Typical Application Circuit HS Driver VIN BOOT SMOD# CBOOT CIN VSWH L1 VOUT PWM COUT GL VCC PGND PGND5V PWM Controller Driver Logic and Delay LS Driver CPVCC 2.5V ~ 20V DISB# THWN VCC PVCC AGND CVCC PHASE
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Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration QFN5x5-31L (Top View) Part Number Ambient Temperature Range Package Environmental AOZ5311NQI -40°C to 125°C QFN5x5-31L RoHS 31 30 29 28 27 25 24 PWM PGND 10 11 12 13 14 15 SMOD# VCC NC PHASE VIN VIN VIN PGND PGND PGND PGND VSWH VSWH VSWH VSWH VSWH GL PGND PVCC THWN DISB# VIN GL BOOT VIN AGND 20
16 VSWH
Rev. 1.2 April 2021 www.aosmd.com Page 3 of 18 Pin Description Pin Number Pin Name Pin Function 1P W M PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be disconnected and this pin will be at high impedance. 2S M O D # Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. There is an internal pull-down resistor to AGND. 3V C C 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and AGND (Pin 4). 4 AGND Signal Ground. 5B O O T High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7). 6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. 7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). 8, 9, 10, 11 VIN Power stage High Voltage In put (Drain connection of High-Side MOSFET). 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16,17,18,19, 20,21,22, 23, 24, 25, 26 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main inductor terminal. 27, 33 GL Low-Side MOSFET Gate connection. This is for test purposes only. 28, 32 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29). 29 PVCC 5V power rail for High-Side and Low-Side MOSFET gate drivers. Ensure to position a 1µF MLCC directly between PVCC to PGND (Pin 28). 30 THWN Thermal warning indicator. This is an open−drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low. 31 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an internal pull−down resistor to AGND.
Rev. 1.2 April 2021 www.aosmd.com Page 4 of 18 Functional Block Diagram VSWH VCC ZCD PVCC GL PGND ZCD Select REF/BIAS UVLO Level Shifter HS Gate Driver Enable Sequencing And Propagation Delay Control Boot HS Control Logic Driver Logic HS Gate PHASE Check ZCD Detect LS PWM Tri-State Logic PWM Tri-State LS Gate LS Gate Driver SMOD# PWM VINBOOTVCC PHASE PVCC Thermal Monitor THWN AGND DISB#
Rev. 1.2 April 2021 www.aosmd.com Page 5 of 18 Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Notes: 1. Peak voltages can be applied for 10ns per switching cycle. 2. Peak voltages can be applied for 20ns per switching cycle. 3. Devices are inherently ESD sens itive, handling precautions are required. Human body model rating: 1.5k in series with 100pF. Recommended Operating Conditions The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Parameter Rating Low Voltage Supply (VCC, PVCC) -0.3V to 7V High Voltage Supply (VIN) -0.3V to 25V Control Inputs (PWM, SMOD#, DISB#) -0.3V to (VCC+0.3V) Output (THWN) -0.3V to (VCC+0.3V) Bootstrap Voltage DC (BOOT-PGND) -0.3V to 28V Bootstrap Voltage Transient (1) (BOOT-PGND) -8V to 30V Bootstrap Voltage DC (BOOT-PHASE/VSWH) -0.3V to 7V BOOT Voltage Transient(1) (BOOT-PHASE/VSWH) -0.3V to 9V Switch Node Voltage DC (PHASE/VSWH) -0.3V to 25V Switch Node Voltage Transient(1) (PHASE/VSWH) -8V to 33V Low-Side Gate Voltage DC (GL) (PGND-0.3V) to (PVCC+0.3V) Low-Side Gate Voltage Transient(2) (GL) (PGND-2.5V) to (PVCC+0.3V) VSWH Current DC 55A VSWH Current 10ms Pulse 80A VSWH Current 10us Pulse 120A Storage Temperature (T S) -65°C to +150°C Max Junction Temperature (TJ)1 5 0 ° C ESD Rating(3) 2kV Parameter Rating High Voltage Supply (VIN) 2.5V to 20V Low Voltage/ MOSFET Driver Supply (VCC, PVCC) 4.5V to 5.5V Control Inputs (PWM, SMOD#, DISB#) 0V to VCC Output (THWN) 0V to VCC Operating Frequency 200kHz to 2MHz
Rev. 1.2 April 2021 www.aosmd.com Page 6 of 18 AOZ5311NQI Electrical Characteristics(4) TJ = 0°C to 150°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units GENERAL VIN Power Stage Power Supply 2.5 20 V VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V RJC (5) Thermal Resistance Reference to High-Side MOSFET temperature rise 2.5 °C/W RJA (5) Freq = 300kHz. AOS Demo Board 12.5 °C/W INPUT SUPPLY AND UVLO VCC_UVLO Under-Voltage Lockout VCC Rising 3.5 3.9 V VCC_HYST VCC Hysteresis 400 mV IVCC Control Circuit Bias Current DISB# = 0V 1 A SMOD# = 5V, PWM = 0V 550 A SMOD# = 0V, PWM = 0V 535 A SMOD# = 0V, PWM =1.65V 430 A IPVCC Drive Circuit Operating Current PWM = 400kHz, 20% Duty Cycle 13 mA PWM = 1MHz, 20% Duty Cycle 33 mA PWM INPUT VPWM_H Logic High Input Voltage 2.7 V VPWM_L Logic Low Input Voltage 0.72 V IPWM_SRC PWM Pin Input Current PWM = 0V -150 A IPWM_SNK PWM = 3.3V 150 A VTRI PWM Input Tri-State Window 1.35 2.1 V VPMW_FLOAT PWM Tri-State Voltage Clamp PWM = Floating 1.65 V DISB# INPUT VDISB#_ON Enable Input Voltage 2.0 V VDISB#_OFF Disable Input Voltage 0.8 V RDISB# DISB# Input Resistance Pull-Down Resistor 850 k SMOD# INPUT VSMOD#_H Logic High Input Voltage 2.0 V VSMOD#_L Logic Low Input Voltage 0.8 V RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 k GATE DRIVER TIMING tPDLU PWM to High-Side Gate PWM: H→L, VSWH: H→L 24 ns tPDLL PWM to Low-Side Gate PWM: L H, GL: H L 25 ns tPDHU Low-side to High-Side Gate Deadtime GL: H L, VSWH: L H1 5 n s tPDHL High-Side to Low-side Gate Deadtime VSWH: H 1V, GL: L H1 3 ns tTSSHD Tri-State Shutdown Delay PWM: L VTRI, GL: H L and PWM: H VTRI, VSWH: H L 25 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI H, VSWH: L H PWM: VTRI L, GL: L H 35 ns
Rev. 1.2 April 2021 www.aosmd.com Page 7 of 18 AOZ5311NQI Notes: 4. All voltages are specified with re spect to the corresponding AGND pin. 5. Characterization value. Not tested in production. Electrical Characteristics(4) TJ = 0°C to 150°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units ZERO CROSS DETECTION VZCD Zero Cross Detect Threshold SMOD# = L 0.5 mV tZCD Zero Cross Detect Blanking Time SMOD# = L 350 ns THERMAL NOTIFICATION(5) TJTHWN Junction Thermal Threshold Temperature Rising 150 °C TJHYST Junction Thermal Hysteresis 30 °C VTHWN THWN Pin Output Low I THWN = 0.5mA 60 mV RTHWN THWN Pull-Down Resistance 120
Table 1. Input Control Truth Table
- Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State.Zero Cross Detection (ZCD) at IL*Rdson(LS) =
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Application Information
AOZ5311NQI is a fully integrated power module designed to work over an input voltage range of 2.5V to 20V with a separate 5V supply for gate drive and internal control circuitry. The MOSFETs are individually optimized for efficient operation on both High-Side and Low-Side for a low duty cycle synchronous buck converter. High current MOSFET Gate Drivers are integrated in the package to minimize parasitic loop inductance for optimum switching efficiency . Powering the Module and the Gate Drives An external supply PVCC = 5V is required for driving the MOSFETs. The MOSFETs are designed with optimally customized gate thresholds voltages to achieve the most advantageous compromise between fast switching speed and minimal power loss. The integrated gate driver is capable of supplying large peak current into the Low- Side MOSFET to achieve fast switching. A ceramic bypass capacitor of 1 F or higher is recommended from PVCC (Pin 29) to PGND (Pin 28). The control logic supply VCC (Pin 3) can be derived from the gate drive supply PVCC (Pin 29) through an RC filter to bypass the switching noise (See Typical Application Circuit). The boost supply for driving the High-Side MOSFET is generated by connecting a small capacitor (100nF) between the BOOT (Pin 5) and the switching node PHASE (Pin 7) . It is recommended that this capacitor C BOOT should be connected to the device across Pin 5 and Pin 7 as close as possible. A bootstrap switch is integrated into the device to reduce external component count. An optional resistor R BOOT in series with C BOOT between 1Ω to 5Ω can be used to slow down the turn on speed of the High-Side MOSF ET to achieve both short switching time and low VSWH switching node spikes at the same time. Under-Voltage Lockout AOZ5311NQI starts up to normal operation when VCC rises above the Under-Voltage Lock-Out (UVLO) threshold voltage. The UVLO release is set at 3.5V typically. Since the PWM control signal is provided from an external controller or a digital processor, extra caution must be taken during star t up. AOZ5311NQI must be powered up before PWM input is applied. Normal system operation begins with a soft start sequence by the controller to minimize in-rush current during start up. Powering the module with a full duty cycle PWM signal may lead to many undesirable consequences due to excessive power. AOZ5311NQI provides some protections such as UVLO and thermal monitor. For system level protection, the PWM controller should monitor the current output and protect the load under all possible operating and transient conditions. Disable (DISB#) Function The AOZ5311NQI can be enabled and disabled through DISB# (Pin 31). The driver output is disabled when DISB# input is connected to AGND. The module would be in standby mode with lo w quiescent cu rrent of less than 1 A. The module will be active when DISB# is connected to VCC Supply. Th e driver output will follow PWM input signal. A weak pull-down resistor is connected between DISB# and AGND. Power up sequence design must be implemented to ensure proper coordination between the module and external PWM controller for soft start and system enable/ disable. It is recommended that the AOZ5311NQI should be disabled before the PWM controller is disabled. This would make sure AOZ5311NQI will be operating under the recommended conditions. Input Voltage VIN AOZ5311NQI is rated to operate over a wide input range from 2 .5V to 20V . For high current synchronous buck converter applications, large pulse current at high frequency and high current slew rates (di/dt) will be drawn by the module during normal operation . It is strongly recommended to place a bypass capacitor very close to the package leads at the input supply (VIN). Both X7R or X5R quality surface mount ceramic capacitors are suitable. The High-Side MOSFET is optimized for fast switching by using low gate charges (Q G) device. When the module is operated at high duty cycle ratio, conduction loss from the High-Side MOSFET will be higher. The total power loss for the module is still relatively low but the High-Side MOSFET higher conduction loss may have higher temperature. The two MOSFETs have their own exposed pads and PCB copper areas for heat dissipation. It is recommended that worst case junction temperature be measured for both High-Side MOSFET and Low-Side MOSFET to ensure that they are operating within Safe Operating Area (SOA). PWM Input AOZ5311NQI is compatible with 3V and 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. AOZ5311NQI is compatible with 3V and 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. The PWM is also compatible with Tri-State input. When the PWM output from the external PWM controller is in high impedance or not connected both High-Side and Low-Side MOSFETs are turned off and VSWH is in high impedance state. Table 2 shows the thresholds level for
Table 2. PWM Input and Tri-State Thresholds Note: See Figure 2 for propagation delays and tri-state window. start up, light load or under pre-bias conditions. minimal anti-overlap delays to avoid cross conduction. for all truth table for DISB#, SMOD# and PWM inputs. PWM signal transition is illustrated as below.
- PWM from logic Low to logic High
Side Gate Driver output GH is turned on.
- PWM from logic High to logic Low
pad parasitic of the package or on PCB. layout to minimize voltage spikes and other transients. and the input bypass capacitor C IN.
Rev. 1.2 April 2021 www.aosmd.com Page 15 of 18 AOZ5311NQI RECOMMENDED LAND PATTERN UNIT: mm NOTE CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT.
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Rev. 1.2 April 2021 www.aosmd.com Page 18 of 18 Part Marking Part Number Code Assembly Lot CodeYear Code & Week Code AOZ5311NQI (QFN5x5) BLN0 YWLT As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. LEGAL DISCLAIMER Applications or uses as critical co mponents in life support devices or s ystems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice . It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.