AT9933

AT9933 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Constant current LED Driver Steps input voltage Up or Down Low EMI Variable frequency operation Internal 8 to 100V linear regulator Input and output current sensing Input current limit Enable & PWM dimming Ambient temperature rating up to 125°C Meets AEC-Q100 requirements

Applications

AEC-Q100 Rev. F, 7/18/2003 SAE J1752-3 General Description The AT9933 is a variable frequency PWM controller IC, designed to control an LED lamp driver using a low-noise boost-buck (Ćuk) topology. The AT9933 uses patent-pending hysteretic current-mode control to regulate both the input and the output currents. This enables superior input surge immunity without the necessity for complex loop compensation. Input current control enables current limiting during startup, input under-voltage and output overload conditions. The AT9933 provides a low-frequency PWM dimming input that can accept an external control signal with a duty cycle of 0 - 100% and a high dimming ratio. The AT9933 based LED driver is ideal for automotive LED lamps. The part is rated for up to 125°C ambient temperatures and is AEC-Q100-Compliant. Typical Application Circuit Hysteretic Boost-Buck (Ćuk) LED Driver IC VIN GATE CS1 CS2 VDD PWMD REFGND VDC L1 L2 Q1 D1 RCS1 RS2 RREF2RREF1 RS1 D2 (optional) VO RCS2 RD CD AT9933

Ordering Information

-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VIN to GND -0.5V to +100V CS1, CS2 -0.3V to (V DD + 0.3V) PWMD to GND -0.3V to (V DD + 0.3V) GATE to GND -0.3V to (V DD + 0.3V) VDDMAX 12V Continuous Power Dissipation (TA = +25°C) 8-Pin SOIC 700mW Junction to ambient thermal impedance (typical); using standard footprint 128 OC/W Junction temperature +150°C Storage temperature range -65°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifi cations is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Confi guration VIN CS1 GATE REF GND VDD PWMD CS2 8-Lead SOIC (top view) Symbol Parameter Min Typ Max Units Conditions Input VINDC Input DC supply voltage range1 * (2) - 100 V DC input voltage IINSD Shut-down mode supply current1 -- 0 . 5 1 . 0m A PWMD connected to GND, VIN = 12V Internal Regulator VDD Internally regulated voltage * 7.0 7.5 9.0 V VIN = 8 – 100V, IDD(ext) = 0, 500pF capacitor at GATE, PWMD = GND UVLO V DD undervoltage lockout threshold * 6.45 6.70 6.95 V V IN rising ∆UVLO VDD undervoltage lockout hysteresis - - 500 - mV ---

Electrical Characteristics

(The * denotes the specifi cations which apply over the full operating ambient temperature range of -40°C < TA < +125°C, otherwise the specifi cations are at TA = 25°C. VIN = 12V, unless otherwise noted)

Symbol Description Min Typ Max Units Conditions Reference VREF REF pin voltage V REF bypassed with a 0.1µF capacitor to GND, IREF= 0, PWMD = 5.0VREF pin voltage VREFLINE Line regulation of reference voltage -0 - 2 0 m V REF bypassed with a 0.1µF capacitor to GND, IREF = 0, VDD = 7.0 – 9.0V, PWMD = 5.0V IREF Reference output current range - -0.01 500 µA REF bypassed with a 0.1µF capacitor to GND, IREF = 0; VDD = 7.0 – 9.0V, PWMD = 5.0V VREFLOAD Load regulation of reference voltage -0 - 1 0 m V REF bypassed with a 0.1µF capacitor to GND, IREF = 0 - 5 0 0 µ A , PWMD = 5.0V PWM Dimming PWMD input low voltage * - - 0.8 V V DD = 7.0V – 9.0V VPWMD(hi) PWMD input high voltage * 2.0 - - V V DD = 7.0V – 9.0V RPWMD PWMD pull-down resistance - 50 100 150 kΩ V PWMD = 5.0V IPWMD Maximum current into PWMD pin - - - 5 mA --- GATE ISOURCE GATE short circuit current - 0.165 - - AV GATE = 0V ISINK GATE sinking current - 0.165 - - A V GATE = VDD TRISE GATE output rise time - - 30 50 ns C GATE = 500pF TFALL GATE output fall time - - 30 50 ns C GATE = 500pF Input Current Sense Comparator VTURNON1 Voltage required to turn GATE on * 85 100 115 mV CS2 = 200mV; CS1 increasing; GATE goes LOW to HIGH VTURNOFF1 Voltage required to turn GATE off * -15 0 15 mV CS2 = 200mV; CS1 decreasing; GATE goes HIGH to LOW TD1,ON Delay to output (turn on) - - 150 250 ns CS2 = 200mV; CS1 = 50mV to +200mV step TD1,OFF Delay to output (turn off) - - 150 250 ns CS2 = 200mV; CS1 = 50mV to -100mV step Output Current Sense Comparator VTURNON2 Voltage required to turn GATE on * 85 100 115 mV CS1 = 200mV; CS2 increasing; GATE goes LOW to HIGH VTURNOFF2 Voltage required to turn GATE off * -15 0 15 mV CS1 = 200mV; CS2 decreasing; GATE goes HIGH to LOW TD2,ON Delay to output (turn on) - - 150 250 ns CS1 = 200mV; CS2 = 50mV to +200mV step TD2,OFF Delay to output (turn off) - - 150 250 ns CS1 = 200mV; CS2 = 50mV to -100mV step 1 Also limited by package power dissipation limit, whichever is lower. 2 Depends on the current drawn by the part - see application section.

Pin Number Pin Description 1 VIN This pin is the input of a 8 - 100V voltage regulator. 2 CS1 These pins are used to sense the input and output currents of the boost-buck converter. They are the non-inverting inputs of the internal comparators.7 CS2 3 GND Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. 4 GATE This pin is the output gate driver for an external N-channel power MOSFET. 5 PWMD When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to a voltage greater than 2V will enable the gate drive output. 6 VDD This is a power supply pin for all internal circuits. It must be bypassed to GND with a low ESR capacitor greater than 0.1µF. 8R E F This pin provides accurate reference voltage. It must be bypassed with a 0.01 - 0.1µF capacitor to GND. Block Diagram Regulator 7.5V VIN CS1 CS2 PWMD GATE VDD REF GND 1.25V AT9933 Input Comparator Output Comparator 0mV 100mV

The AT9933 is optimized to drive a continuous conduction mode (CCM) boost-buck DC/DC converter topology com- monly referred to as “Ćuk converter” (see Circuit Diagram on page 1). This power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (HB LED). These advantages include step-up or step-down voltage conversion ratio and low input and output current ripple. The output load is decoupled from the input voltage with a capacitor making the driver inherently failure- safe for the output load. The AT9933 offers a simple and effective control technique for use with a boost-buck LED driver. It uses two hysteretic mode controllers – one for the input and one for the output. The outputs of these two hysteretic comparators are AND- ED and used to drive the external FET. This control scheme gives accurate current control and constant output current in the presence of input voltage transients without the need for complicated loop design. Input Voltage Regulator The AT9933 can be powered directly from its VIN pin that takes a voltage from 8V to 100V. When a voltage is applied at the VIN pin, the AT9933 seeks to regulate a constant 7.5V (typ) at the VDD pin. The regulator also has a built in under- voltage lockout which shuts off the IC if the voltage at the VDD pin falls below the UVLO threshold. The VDD pin must be bypassed by a low ESR capacitor (≥0.1μF) to provide a low impedance path for the high fre- quency current of the output gate driver. The input current drawn from the VIN pin is a sum of the 1mA current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switching fre- quency and the gate charge of the external FET). I IN = 1mA + QG•fS (1) In the above equation, f S is the switching frequency and Q G is the gate charge of the external FET (which can be ob- tained from the datasheet of the FET). Minimum Input Voltage at VIN pin The minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. The internal linear regulator will regu- late the voltage at the VDD pin when V IN is between 8 and 100V. However, when VIN is less than 8V, the converter will still function as long as VDD is greater than the under voltage lockout. Thus, under certain conditions, the converter will be able to start at V IN voltages of less than 8V. The start/stop voltages at the VIN pin can be determined using the maxi- mum voltage drop across the linear regulator as a function of the current drawn. This data is shown in Fig. 1 for ambient temperatures of 25ºC and 125ºC. Assume an ambient temperature of 125°C. Assuming the IC is driving a 15nC gate charge FET at 300kHz, the total input current is estimated to be 5.5mA (using Eqn. 1). At this input current, the maximum voltage drop from Fig. 1 can be ap- proximately estimated to be V DROP = 2.7V. However, before the IC starts switching the current drawn will be 1mA. At this current level, the voltage drop is approximately V DROP1 = 0.5V. Thus, the start/stop VIN voltages can be computed to be: VINSTART = UVLOMAX + VDROP1 = 6.95V + 0.5V = 7.45V VINSTOP = UVLOMAX - ΔUVLO + VDROP = 9.15V Note that in this case, since the gate drive draws too much current, VIN START is less than VINSTOP. In such cases, the con- trol IC will oscillate between ON and OFF if the input voltage is between the start and stop voltages. In these circumstanc- es, it is recommended that the input voltage be kept higher than VIN STOP (in this case the IC will operate normally if the input voltage is kept higher than 9.2V). In case of input transients that reduce the input voltage be- low 8V (like cold crank condition in an automotive system), the VIN pin of the AT9933 can be connected to the drain of the MOSFET through a switching diode with a small (1nF) capacitor between VIN and GND (as long as the drain volt- age does not exceed 100V). Since the drain of the FET is at a voltage equal to the sum of the input and output voltages, the IC will still be operational when the input goes below 8V. In these cases, a larger capacitor is needed to the VDD pin to supply power to the IC when the MOSFET is ON. Voltage Drop vs. IIN 0.5 1.5 2.5 3.5 01234567 IIN (mA) Voltage Drop (V) Fig. 1. Maximum Voltage Drop vs. Input Current 125 OC 25OC

In this case VDD UVLO cannot be relied upon to turn off the IC at low input voltages when input current levels can get too large. The input current limit must then be designed to limit the input current to safe levels during input undervoltage conditions. Reference An internally trimmed voltage reference of 1.25V is provided at the REF pin. The reference can supply a maximum output current of 500μA to drive external resistor dividers. This reference can be used to set the current thresholds of the two comparators as shown in the Typical Application Cir- cuit. Current Comparators The AT9933 features two identical comparators with a built- in 100mV hysteresis. When the GATE is low, the inverting terminal is connected to 100mV and when the GATE is high, it is connected to GND. One comparator is used for the input current control and the other for the output current control. The input side hysteretic controller is in operation during start-up, overload and input undervoltage conditions. This ensures that the input current never exceeds the designed value. During normal operation, the input current will be less than the programmed current and hence, the output of the input side comparator will be HIGH. The output of the AND gate will then be dictated by the output current controller. The output side hysteretic comparator will be in operation during the steady state operation of the circuit. This com- parator turns the MOSFET on and off based on the LED current. PWM Dimming PWM Dimming can be achieved by applying a TTL-compat- ible square wave signal at the PWM pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or con- nected to GND, the gate driver is disabled and the external MOSFET turns off. The IC is designed so that the signal at the PWMD pin inhibits the driver only and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The recommended PWM Dimming frequency range is from 100Hz to a few kilo hertz. The fl ying capacitor in the Ćuk converter (C1) is initially charged to the input Voltage VDC (through diodes D1 and D2). When the circuit is turned on and reaches steady state, the voltage across C1 will be VDC+VO. In the absence of diode D2, when the circuit is turned off, capacitor C1 will discharge through the LEDs and the input voltage source VDC. Thus, during PWM dimming, if capacitor C1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. By adding diode D2, the volt- age across capacitor C1 is held at VDC+VO even when the circuit is turned off enabling the circuit to return quickly to its steady state (and bypassing the start-up stage) upon being enabled.

Application Information

Over-voltage protection can be added by splitting the output side resistor R S2 into two components and adding a zener diode D3 (see the Design Example Circuit on the following page). When there is an open LED condition, the diode D3 will clamp the output voltage and the zener diode current will be regulated by the sum of R S2A and RCS2. Damping Circuit The Ćuk converter is inherently unstable when the output current is being controlled. An uncontrolled input current will lead to an un-damped oscillation between L1 and C1 caus- ing excessively high voltages across C1. To prevent these oscillations, a damping circuit consisting of RD and CD is applied across the capacitor C1. This damping circuit will stabilize the circuit and help in the proper operation of the AT9933 based Ćuk converter. Design and Operation of the Boost-Buck Con- verter For details on the design for a Boost-Buck converter using the AT9933 and the calculation of the damping components, please refer to Application Note AN-H51.

The choice of the resistor dividers to set the input and output current levels is illustrated by means of the design example given below. The parameters of the power circuit are: V IN MIN = 9V VIN MAX = 16V VO = 28V IO = 0.35A fS MIN = 300kHz Using these parameters, the values of the power stage in- ductors and capacitor can be computed as (see Application Note AN-H51 for details): L1 = 82µH L2 = 150µH C1 = 0.22µF The input and output currents for this design are: I IN MAX = 1.6A ΔIIN = 0.21A IO = 350mA ΔIO = 87.5mA Current Limits The current sense resistor ( RCS2), combined with the other resistors (RS2 & RREF2), determines the output current limits. The current sense resistor ( RCS1), combined with the other resistors (RS1 & RREF1), determines the input current limits. The resistors can be chosen using the following equations: ( 2 ) ( 3 ) Where I is the current (either I O or IIN) and ΔI is the peak-to- peak ripple in the current (either ΔIO or ΔIIN). For the input side, the current level used in the equations should be larger than the maximum input current so that it does not interfere with the normal operation of the circuit. The peak input current can be computed as: ( 4 ) I X RCS = 1.2V X RS RREF + 0.05V ∆I X RCS = 0.1V X RS RREF + 0.1V IIN,PK = IIN,MAX + Iin = 1.706A Design Example Circuit VIN GATE CS1 CS2 VDD PWMD REFGND VDC L1 L2 Q1 D1 RCS1 RS2A RREF2 RREF1 RS1 D2 (optional) VO RCS2 CO RD CD AT9933 RS2B

Assuming a 30% peak-to-peak ripple when the converter is in input current limit mode, the minimum value of the input current will be: I LIM,MIN = 0.85 • IIN,LIM (5) Setting I LIM,MIN = 1.05 • I IN,PK (6) The current level to limit the converter can then be com- puted. ( 7 ) Using IO = 350mA and ΔIO = 87.5mA in (1) and (2), Before the design of the output side is complete, over voltage protection has to be included in the design. For this applica- tion, choose a 33V zener diode. This is the voltage at which the output will clamp in case of an open LED condition. For a 350mW diode, the maximum current rating at 33V works out to about 10mA. Using a 2.5mA current level during open LED conditions, and assuming the same R S2/RREF2 ratio, RCS2 + RS2A = 120Ω (8) Choose the following values for the resistors: RREF2 = 10kΩ, 1/8W, 1% RS2A = 100Ω, 1/8W, 1% RS2B = 5.23kΩ, 1/8W, 1% The current sense resistor needs to be at least a 1/4W, 1% resistor. Similarly, using I IN = 2.1A and ΔIIN = 0.3xIIN = 0.63 in (1) and (2): R CS1 = 0.228Ω PRCS1 = I2 IN,LIM • RCS1 = 1W Choose the following values for the resistors: RCS1 = parallel combination of three 0.68Ω, 1/2W, 5% R REF1 = 10kΩ, 1/8W, 1% IIN LIM = • IIN PK0.85 = 2.1A 1.05 RCS2 RS2 RREF2 = 1.78Ω = 0.5625 RS1 RREF1 = 0.442

Doc.# DSFP-AT9933 NR112806 AT9933 (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 45° 5° - 15° (4 PLCS) 4.90 ± 0.10 1.27BSC 6.00 ± 0.20 3.90 ± 0.10 Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. Note 2

1.75 MAX

1.25 MIN

0.25 - 0.50 0° - 8° 0.40 - 1.27 0.17 - 0.25 Top View Side View End View Note 2 8-Lead SOIC (Narrow Body) Package Outline (LG)