74HC595 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 74HC595 8-bit shift registers with 3-state output latches in bare die form Rev 1.0 05/02/19 Output Drive Capability: 15 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS595. Features:
Ordering Information
The following part suffixes apply: The 74HC595 is an 8–bit serial-in to parallel-out shift register which drives an 8–bit D–type latch with 3–state outputs. Both register and latch have independent positive triggered clock inputs. All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register. The shift register also features asynchronous reset. Device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs
Description
Die Dimensions in µm (mils) 1030 (41) Die Size (Unsawn) 1030 x 770 41 x 30 µm mils Minimum Bond Pad Size 70 x 70 2.76 x 2.76 µm mils Die Thickness 280 (±20) 13.02 (±0.79) µm mils Top Metal Composition Al-Si-Cu 2.8 µm Back Metal Composition N/A – Bare Si No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification 770 (30) Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 280µm(11 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 9 www.siliconsupplies.com A ll data sheet.com
d High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 Pad Layout and Functions Logic Diagram 770µm (30.32 mils) 1610µm (63.38 mils) 2 3 4 5 6 101112 13 14 DIE ID 0,0 COORDINATES (µm) PAD FUNCTION X Y 1 QB -401.8 -102 2 QC -401.8 -246 3 QD -205.8 -273 4 QE -95.8 -273 5 QF 95.8 -273 6 QG 205.8 -273 7 QH 401.8 -230.2 8 GND 401.8 -84.6 9 QH’ 401.8 62.6 10 SRCLR 401.8 243.2
11 SRCLK 272 273
12 RCLK 103.2 273 13 OE -54.4 273 14 SER -233.2 273 15 QA -401.8 237.6 16 VCC -401.8 46 CONNECT CHIP BACK TO VCC OR FLOAT Page 2 of 9 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -40 +85 °C VCC = 2.0V 0 1000 ns VCC = 4.5V 0 500 ns Input Rise or Fall Times VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions4 (Voltages referenced to GND) Absolute Maximum Ratings2 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±35 mA DC VCC or GND Current ICC ±75 mA Power Dissipation in Still Air3 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 2. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 3. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. Function Table1 4. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. INPUTS OUTPUTS SRCLK RCLK OE SRCLR SER QH’ Q N FUNCTION X X L L X L NC LOW level on SRCLR only affects the shift registers X ↑ L L X L L Empty shift-register loaded into storage register X X H L X L Z Shift-register clear. Parallel outputs in high- impedance OFF- state ↑ X L H H QG’ NC Logic high level shifted into shift register stage 0. Content of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q 6’) appears on serial output(QH’) X ↑ L H X NC Qn’ Contents of shift register stages (internal Qn’) transfers to the storage register and parallel output stages ↑ ↑ L H X QG’ Q n ’ Shift register contents shifted through. Previous shift register content transfers to storage register & parallel output stages. 1. H=HIGH voltage level; L=LOW voltage level; ↑ =LOW-to-HIGH transition; Z=high-impedance OFF-state; NC=no change; X=don’t care. A ll data sheet.com
High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 V 4.2 4.2 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 VOUT = 0.1V or VCC -0.1V Maximum Low-Level Input Voltage VIL V │IOUT│≤ 20µA 6.0V 1.8 1.8 1.8 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.34 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage (QA – QH) VOH 6.0V VIN = VIH or VIL │IOUT│≤ 7.8mA 5.48 5.34 5.34 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.33 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL (QA–QH) V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL V │IOUT│≤ 20µA 5.9 5.9 5.9 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.34 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage (QH’) VOH V 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.34 Page 4 of 9 www.siliconsupplies.com A ll data sheet.com
High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C FULL RANGE5 UNITS 85°C 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 6.0 4.8 4.8 3.0V 15 10 10 4.5V 30 24 24 Maximum Clock Frequency (50% Duty Cycle) (Figure 1,7) fmax 6.0V CL = 50pF, Input tr = tf = 6ns 35 28 28 MHz 2.0V 140 175 175 3.0V 100 125 125 4.5V 28 35 35 Maximum Propagation Delay, SRCLK to QH’ (Figure 1,7) tPLH, tPHL 6.0V CL = 50pF, Input tr = tf = 6ns 24 30 30 ns 2.0V 145 180 180 3.0V 100 125 125 4.5V 29 36 36 Maximum Propagation Delay, SRCLR to QH’ (Figure 2,7) tPHL 6.0V CL = 50pF, Input tr = tf = 6ns 25 31 31 ns 2.0V 140 175 175 3.0V 100 125 125 4.5V 28 35 35 Maximum Propagation Delay, RCLK to QA – QH (Figure 3,7) tPLH, tPHL 6.0V CL = 50pF, Input tr = tf = 6ns 24 30 30 ns 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.33 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL (QH’) 6.0V VIN = VCC or GND │IOUT│≤ 5.2mA 0.26 0.33 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Three-State Leakage Current (QA–QH) IOZ 6.0V High-Impedance Output State, VIN = VIH or VIL, VOUT=VCC or GND ±0.5 ±5.0 ±5.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 4 40 40 µA 6. Not production tested in die form, characterized by chip design and tested in package. Page 5 of 9 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 150 190 190 3.0V 100 125 125 4.5V 30 38 38 Maximum Propagation Delay, OE to QA – QH (Figure 4,8) tPLZ, tPHZ 6.0V CL = 50pF, Input tr = tf = 6ns 26 33 33 ns 2.0V 135 170 170 3.0V 90 110 110 4.5V 27 34 34 Maximum Propagation Delay, OE to QA – QH (Figure 4,8) tPZL, tPZH 6.0V CL = 50pF, Input tr = tf = 6ns 23 29 29 ns 2.0V 60 75 75 3.0V 23 27 27 4.5V 12 15 15 Maximum Output Transition Time, QA – QH (Figure 3,7) tTLH, tTHL 6.0V CL = 50pF, Input tr = tf = 6ns 10 13 13 ns 2.0V 75 95 95 3.0V 27 32 32 4.5V 15 19 19 Maximum Output Transition Time, QH’ (Figure 1,7) tTLH, tTHL 6.0V CL = 50pF, Input tr = tf = 6ns 13 16 16 ns Maximum Input Capacitance CIN - - 10 10 10 pF Maximum Three-State Output Capacitance, QA – QH COUT - High- Impedance Output State 15 15 15 pF TYPICAL Power Dissipation Capacitance7 CPD - TJ = 25°C, VCC = 5.0V 300 pF Timing Requirements6 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 50 65 65 3.0V 40 50 50 4.5V 10 13 13 Minimum Setup Time, SER to SRCLK (Figure 5) tsu 6.0V Input tr = tf = 6ns 9 11 11 ns 2.0V 75 95 95 3.0V 60 70 70 4.5V 15 19 19 Minimum Setup Time, SRCLK to RCLK (Figure 6) tsu 6.0V Input tr = tf = 6ns 13 16 16 ns A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC595 Rev 1.0 05/02/19 Timing Diagram DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. A ll data sheet.com