54HC20_V01 SS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 5
Technical content
High Speed CMOS Logic – 54HC20 Die Size (Unsawn) 1200 x 1200 47 x 47 µm mils Minimum Bond Pad Size 106 x 106 4 x 4 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Dual 4-Input NAND Gate IC in bare die form High Speed: t PD = 11ns @ 6V (Typ.) Low Input Current: 1µA Output Drive Capability: 10 LSTTL loads Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS20 Full Military Temperature Range. Rev 1.0 7/5/2019 Features:
Ordering Information
The following part suffixes apply: The 54HC20 Dual 4-Input NAND Gate is made using a 2.5µm 5V CMOS process & combines the high speed of LSTTL with CMOS low power consumption. The device performs Boolean functions Y = (A • B • C • D) or Y = A + B + C + D in positive logic. Inputs accept standard CMOS outputs or LSTTL outputs using pull- up resistors. Internal circuitry comprises 3 stages & includes buffered output for high noise immunity & stability. Inputs are equipped with protection circuits against static discharge & transient excess voltage.
Description
Die Dimensions in µm (mils) 1200 (47) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. 1200 (47) www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com d High Speed CMOS Logic – 54HC20 Rev 1.0 7/5/2019 COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.151 0.364 2 1B 0.151 0.184 3 1C 0.427 0.151 4 1D 0.671 0.151 5 1Y 0.933 0.238 6 GND 0.943 0.418 7 2Y 0.943 0.706 8 2A 0.909 0.886 9 2B 0.672 0.929 10 2C 0.405 0.917 11 2D 0.151 0.853 12 VCC 0.151 0.608 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram 1200µm (47.24 mils) 1200µm (47.24 mils) 0,0 Function Table INPUTS OUTPUT A B C D Y L X X X H X L X X H X X L X H X X X L H H H H H L H = High level (steady state) L = Low level (steady state) X = don’t care 2 3 4 8 9 DIE ID PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times tr, tf VCC = 6V 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. High Speed CMOS Logic – 54HC20 Rev 1.0 7/5/2019 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2V 0.3 0.3 0.3 4.5V 0.9 0.9 0.9 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PART OBSOLETE - DISCONTINUED
High Speed CMOS Logic – 54HC20 Rev 1.0 7/5/2019 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 25°C 85°C UNITS 2V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 VIN = VIH or VIL V │IOUT│≤ 20µA 6.0V 5.9 5.9 5.9 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 V Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 2 20 40 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 90 115 135 4.5V 18 23 27 Maximum Propagation Delay, Input A, B, C, D to Output Y tPLH, tPHL CL = 50pF, tr = tf = 6ns ns 6.0V 15 20 23 2V 75 95 110 4.5V 15 19 22 Maximum Output Rise CL = 50pF, and Fall Time, Any Output tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 19 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TJ = 25°C, Capacitance Per Gate6 CPD - pF VCC =5.0V 26 5. Not production tested in die form, characterized by chip design and tested in package. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 4 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC20 Rev 1.0 7/5/2019 Switching Waveform Test Circuit DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT TEST POINT * Includes all probe and jig capacitance PART OBSOLETE - DISCONTINUED