54HC30_V01 SS | Alldatasheet
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High Speed CMOS Logic – 54HC30 8-Input NAND Gate Logic IC in bare die form Low Input Current: 1µA Output Drive Capability: 10 LSTTL loads Outputs Directly Interface to CMOS, NMOS, & TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 54LS30 Full Military Temperature Range. Rev 1.0 7/5/2019 Features:
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Description
The 54HC30 8-Input NAND Gate is made using a 2.5µm 5V CMOS process & combines the high speed of LSTTL with CMOS low power consumption. The device performs Boolean functions in positive logic: Y = A • B • C • D • E • F • G • H or Y = A + B + C + D + E + F + G + H. Device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Internal circuitry comprises 3 stages & includes buffered output for high noise immunity & stability. Die Dimensions in µm (mils) The following part suffixes apply: 1030 (40) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT 1270 (50) “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Die Size (Unsawn) 1030 x 1270 40 x 50 µm mils Minimum Bond Pad Size 108 x 108 4.25 x 4.25 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Page 1 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
d High Speed CMOS Logic – 54HC30 Rev 1.0 7/5/2019 Pad Layout and Functions Logic Diagram Function Table 1270µm (50 mils) 0,0 1030µm (40.55 mils) COORDINATES (mm) PAD FUNCTION X Y 10 9 1 A 0.1155 0.7200 11 2 B 0.1155 0.4015 3 C 0.1355 0.1465 8 4 D 0.3080 0.1160 1 5 E 0.6220 0.1160 6 F 0.8130 0.1465 7 GND 0.8130 0.4810 DIE ID 8 Y 0.8130 0.8000 2 9 G 0.6220 1.0465 10 H 0.3080 1.0465 11 VCC 0.1155 0.9670 3 6 5 4 CONNECT CHIP BACK TO VCC OR FLOAT INPUTS OUTPUT A B C D E F G H Y X X L X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L H = High level (steady state) L = Low level (steady state) X = don’t care Page 2 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times tr, tf VCC = 6V 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. High Speed CMOS Logic – 54HC30 Rev 1.0 7/5/2019 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2V 0.3 0.3 0.3 4.5V 0.9 0.9 0.9 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PART OBSOLETE - DISCONTINUED
High Speed CMOS Logic – 54HC30 Rev 1.0 7/5/2019 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 2V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 V 2V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 V Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 2 20 40 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 175 220 265 4.5V 35 44 53 Maximum Propagation Delay, Any Input to Output Y tPLH, tPHL CL = 50pF, tr = tf = 6ns 6.0V 30 37 45 ns 2V 75 95 110 4.5V 15 19 22 Maximum Output Rise and Fall Time, Any Output CL = 50pF, tTLH, tTHL tr = tf = 6ns 6.0V 13 16 19 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance Per Gate6 CPD - TJ = 25°C, VCC =5.0V 27 pF 5. Not production tested in die form, characterized by chip design and tested in package. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 4 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC30 Rev 1.0 7/5/2019 Switching Waveform DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance PART OBSOLETE - DISCONTINUED