74HC112 SS | Alldatasheet
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Technical content
R High Speed CMOS Logic – 74HC112 Dual J-K Flip-Flops with preset and clear; negative edge trigger in bare die form Rev 1.0 24/11/17 Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Die Size (Unsawn) 1500 x 1700 59 x 67 µm mils Minimum Bond Pad Size 120 x 120 4.72 x 4.72 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si CMOS High Noise Immunity Function compatible with 74LS112. Features:
Ordering Information
The following part suffixes apply: The 74HC112 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. Each flip-flop has independent J, K, preset, clear, clock inputs and Q Q outputs. A high level at the clock input enables the J and K inputs to accept data. The device changes state on the negative going transition of the clock pulse. Preset and clear are independent of the clock and are accomplished by a low logic level on the corresponding input. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Description
Die Dimensions in µm (mils) 1500 (59) No suffix - MIL-STD-883 /2010B Visual Inspection 1700 (67) For High Reliability version of this product please see 54HC112 Supply Formats: Mechanical Specification Default – Die in Waffle Pack (100 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com A ll data sheet.com
d High Speed CMOS Logic – 74HC112 Rev 1.0 24/11/17Pad Layout and Functions 1500µm (59.06 mils) 1700µm (66.93 mils) 0,0 COORDINATES (mm) PAD FUNCTION X Y 1 1CLK 0.125 0.345 2 1K 0.135 0.125 3 1J 0.585 0.135 4 1PRE 0.755 0.135 5 1Q 1.025 0.135 6 1Q 1.225 0.135 7 2Q 1.245 0.54 8 GND 1.245 0.735 9 2Q 1.26 0.995 10 2PRE 1.26 1.165 11 2J 1.25 1.47 12 2K 0.86 1.48 13 2CLK 0.48 1.48 14 2CLR 0.125 1.47 15 1CLR 0.125 0.855 16 VCC 0.125 0.615 CONNECT CHIP BACK TO VCC OR FLOAT 6 5 4 3 2 14 13 12 DIE ID Truth Table Logic Diagram INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H* H* H H ↓ L L NO CHANGE H H ↓ H L H L H H ↓ L H L H H H ↓ H H TOGGLE H H H X X NO CHANGE H = High level (steady state), L = Low level (steady state) X = Don’t care, ↓ = High-to-Low transition * Output states unpredictable if both PRE and CLR go High simultaneously after both being low at the same time. x1 Flip-Flop Page 2 of 6 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ 0 +85 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC112 Rev 1.0 24/11/17 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. Pad Descriptions CLOCK INPUTS 1CLK, 2CLK (Pads 1, 13) Clock input (HIGH-to-LOW, edge triggered) DATA INPUTS 1K, 2K, 1J, 2J (Pads 2, 12, 3, 11) Data inputs; flip-flops 1 and 2 OUTPUTS 1Q, 2Q, 1Q, 2Q (Pads 5, 9, 6, 7) True flip-flop outputs and complement flip-flop outputs 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. CONTROL INPUTS 1PRE, 2PRE (Pads 4, 10) Set inputs (active LOW) 1CLR, 2CLR ( Pads 15, 14) Reset inputs (active LOW) GROUND & POWER GND, V CC (Pads 8, 16) Ground 0V, Positive Supply Voltage A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC112 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.3 0.3 0.3 4.5V 0.9 0.9 0.9 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.2 1.2 1.2 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH │IOUT│≤ 5.2mA 5.48 5.34 5.34 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIL or VIH │IOUT│≤ 20µA 0.1 0.1 0.1 4.5V VIN = VIL or VIH │IOUT│≤ 4.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIL or VIH │IOUT│≤ 5.2mA 0.26 0.33 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 4 40 40 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 6.0 4.8 4.8 4.5V 30 24 24 Max Clock Frequency, 50% Duty Cycle (Figure 1, 4) fmax 6.0V CL = 50pF, tr = tf = 6ns 35 28 28 MHz 2.0V 125 155 155 4.5V 25 31 31 Maximum Propagation Delay, Clock to Q or Q (Figure 1, 4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 21 36 36 ns 2.0V 155 195 195 4.5V 31 39 39 Maximum Propagation Delay, Reset to Q or Q (Figure 2,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 26 33 33 ns A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC112 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 165 205 205 4.5V 33 41 41 Maximum Propagation Delay, Set to Q or Q (Figure 2,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 28 35 35 ns 2.0V 75 95 95 4.5V 15 19 19 Maximum Output Transition time, Any output (Figure 1,4) tTLH, tTHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 16 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance6 (Per Flip-Flop) CPD - - pF 5. Not production tested in die form, characterized by chip design and tested in package. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 100 125 125 4.5V 20 25 25 Maximum Setup Time, J or K to Clock (Figure 3) tSU 6.0V CL = 50pF, tr = tf = 6ns 17 21 21 ns 2.0V 3 3 3 4.5V 3 3 3 Minimum Hold Time, Clock to J or K (Figure 3) th 6.0V CL = 50pF, tr = tf = 6ns 3 3 3 ns 2.0V 100 125 125 4.5V 20 25 25 Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) trec 6.0V CL = 50pF, tr = tf = 6ns 17 21 21 ns 2.0V 80 100 100 4.5V 16 20 20 Minimum Pulse Width, Clock (Figure 1) tw 6.0V CL = 50pF, tr = tf = 6ns 14 17 17 ns 2.0V 80 100 100 4.5V 16 20 20 Minimum Pulse Width, Set or Reset (Figure 2) tw 6.0V CL = 50pF, tr = tf = 6ns 14 17 17 ns 2.0V 1000 1000 1000 4.5V 500 500 500 Maximum Input Rise and Fall times (Figure 1) tr, tf 6.0V CL = 50pF, tr = tf = 6ns 400 400 400 ns Timing Requirements5 A ll data sheet.com