74LS164_V01 SS | Alldatasheet
Document overview
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Technical content
Die Size (Unsawn) 1060 x 1690 74 x 67 µm mils Minimum Bond Pad Size 110 x 110 4.33 x 4.33 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Low Power Schottky Logic – 74LS164 8-Bit Serial-Input / Parallel-Output Shift Register in bare die form Rev 1.0 24/11/17 Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Industrial temperature range. Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection For High Reliability versions of this product please see 54LS164 Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request
Description
The 74LS164 is fabricated on a 2µm 40V Bipolar process. The device consists of x2 serial data inputs, A and B, provided so that one input can be used as a data enable. Data is entered on each rising edge of the clock. A LOW on the master reset input (CLR) clears the register, forcing all outputs LOW, independent of other inputs. All inputs are equipped with Schottky clamp diodes to limit termination effects & achieve high speed. These input circuits also protect against static discharge & transient excess voltage. Die Dimensions in µm (mils) 1880 (74) 1690 (66) Page 1 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com d Low Power Schottky Logic – 74LS164 Rev 1.0 24/11/17 Logic Diagram 1880µm (74.02 mils) 1690µm (66.53 mils) 0,0 COORDINATES (mm) PAD FUNCTION X Y 1 A 0.075 0.647 2 B 0.077 0.342 3 QA 0.203 0.075 4 QB 0.725 0.075 5 QC 1.091 0.075 6 QD 1.625 0.083 7 GND 1.691 0.331 8 CLK 1.693 0.745 9 CLR 1.691 1.504 10 QE 1.449 1.505 11 QF 1.091 1.503 12 QG 0.697 1.505 13 QH 0.085 1.412 14 VCC 0.077 0.885 CONNECT CHIP BACK TO GND OR FLOAT Pad Layout and Functions D = Data Input QAn - QGn = Data shift from preceding register on rising edge clock input 3 4 5 6 91011 12 DIE ID Function Table INPUTS OUTPUTS CLR CLK A B Q A Q B … QH L H H H H X L X X H L X X X H X L L Q H L L L Q QAN QAN QAN L QH0 QGN QGN QGn PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com Low Power Schottky Logic – 74LS164 Rev 1.0 24/11/17 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.75 5.25 V High-Level Input Voltage VIH 2 - V Low-Level Input Voltage VIL - 0.8 V High-Level Output Current IOH - -0.4 mA Low-Level Output Current IOL - 8 mA Clock Frequency fclock 0 25 MHz Pulse Width – Clock or Clear tw 20 - ns Setup time – A or B to Clock tsu 15 - ns Recovery Time trec 5 - ns Operating Temperature Range TJ -40 +85 °C Recommended Operating Conditions Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage VCC 7.0 V DC Input Voltage VIN 7.0 V Storage Temperature Range TSTG -65 to 150 °C 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. LIMITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Minimum High-Level Input Voltage VIH - 2 - - V Maximum Low-Level Input Voltage VIL - - - 0.8 V Input Clamp Diode Voltage VIK VCC = MIN IIN = -18mA - - -1.5 V Output Voltage High VOH VCC = MIN, IOH = -0.4mA VIH = 2V, VIL = MAX 2.7 3.5 - V Output Voltage Low VOL VCC = MIN, VIH = 2V, VIL = MAX IOL = 8mA - 0.35 0.5 V 2. All typical values @ VCC = 5V, TJ = 25°C. PART OBSOLETE - DISCONTINUED
Low Power Schottky Logic – 74LS164 Rev 1.0 24/11/17 LIMITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = MAX, VIN = 2.7V - - 20 µA Input High Current IIH VCC = MAX, VIN = 7.0V - - 0.1 mA Input Low Current IIL VCC = MAX, VIN = 0.4V - - -0.4 mA Short Circuit Current3 IOS VCC = MAX -20 - -100 mA Power Supply Current ICC VCC = MAX mA - 16 27 3. Not more than one output should be shorted at a time, nor for more than 1 second. LIMITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Propagation Delay, Clock to Q tPLH VCC = 5V, CL = 15pF, RL =2kOhm, tr = 15ns, tr = 6ns - - 27 ns Propagation Delay, Clock to Q tPHL VCC = 5V, CL = 15pF, RL =2kOhm, tr = 15ns, tr = 6ns - - 32 ns Propagation Delay, Reset to Q tPHL VCC = 5V, CL = 15pF, RL =2kOhm, tr = 15ns, tr = 6ns - - 36 ns Timing Requirements5 TJ = 25°C unless otherwise specified 4. Not production tested in die form, characterized by chip design and tested in package. LIMITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time, A or B to CLK tsu VCC = 5V, CL = 15pF, RL =2kOhm, tr = 15ns, tr = 6ns 15 - - ns Hold Time, CLK to A or B th VCC = 5V, CL = 15pF, RL =2kOhm, tr = 15ns, tr = 6ns 5 - - ns VCC = 5V, CL = 15pF, Pulse Width, Clock or Reset tw RL =2kOhm, tr = 15ns, tr = 6ns 20 - - ns Page 4 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED