54HC74_V02 SS | Alldatasheet
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High Speed CMOS Logic – 54HC74 Dual D-Type Flip-Flop Logic IC with Set and Reset in bare die form Rev 1.0 21/11/17 Die Size (Unsawn) 1194 x 1397 47 x 55 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1µA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacemen t for obsolete components in long term programs. Features: The following part suffixes apply:
Description
The 54HC74 is fabricated using a 2.5µm 5V CMOS process and consists of two identical, independent data type flip-flops. Each flip-flop has separate data, set, reset, clock inputs and Q,Q outputs. The device can be used in Shift Register applications and also Counter or Toggle applications by connecting Q output to the data input. The logic level present at the “D” input is transferred to the Q output during the positive- going transition of the clock pulse. Setting or resetting is clock independent and accomplished by a high level on the respective Set or Reset line. Ordering Information Die Dimensions in µm (mils) 1194 (47) 1397 (55) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
d High Speed CMOS Logic – 54HC74 Rev 1.0 21/11/17 Pad Layout and Functions Logic Diagram 1194µm (47 mils) 1397µm (55 mils) 0,0 13 14 8 7 6 2 1 DIE ID PAD FUNCTION 1 1CLR 2 1D 3 1 CLK 4 1PRESET 5 1Q 6 1Q
7 GND
14 VCC
CONNECT CHIP BACK TO VCC OR FLOAT Truth Table Page 2 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC74 Rev 1.0 21/11/17 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2.0 6.0 V DC Input Voltage, Output Voltage VIN, VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC=2.5V 0 1000 VCC=4.5V 0 500 Input Rise / Fall Time VCC=6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input or Output Voltage (Referenced to GND) VIN, VOUT -1.5 to VCC+1.5 V Storage Temperature Range TSTG -65 to 150 °C Input Current (per Pad) IIN ±20 mA Output Current (per Pad) IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0 VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0 0.5 0.5 0.5 4.5 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0 VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V 2.0 1.9 1.9 1.9 4.5 4.4 4.4 4.4 6.0 VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V
4.5 VIN = VIH or VIL
│IOUT│≤ 4.0mA 3.98 3.84 3.7 V Minimum High-Level Output Voltage VOH
6.0 VIN = VIH or VIL
│IOUT│≤ 5.2mA 5.48 5.34 5.2 V 3. This device contains protection circuitry against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of voltage higher than max rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to range 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC74 Rev 1.0 21/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0 0.1 0.1 0.1 4.5 0.1 0.1 0.1 6.0 VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V │IOUT│≤ 4.0mA 0.26 0.33 0.4 Maximum Low-Level Output Voltage VOL │IOUT│≤ 5.2mA 0.26 0.33 0.4 V Maximum Input Leakage Current IIN 6.0 VIN = GND or VCC ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0 VIN = GND or VDD IOUT = 0µA 2.0 20 80 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0 6.0 4.8 4.0 4.5 30 24 20 Maximum Clock Frequency fmax 6.0 CL = 50pF, tr = tf = 6ns 35 28 24 MHz 2.0 100 125 50 4.5 20 25 30 Propagation Delay, CLK to Q or Q (Figure 1) tPLH, tPHL 6.0 CL = 50pF, tr = tf = 6ns 17 21 26 ns 2.0 105 130 160 4.5 21 26 32 Propagation Delay, PRE or CLR to Q or Q (Figure 2) tPLH, tPHL 6.0 CL = 50pF, tr = tf = 6ns 18 22 27 ns 2.0 75 95 110 4.5 15 19 22 Output Transition Time, Any Output (Figure 1) tTLH, tTHL 6.0 CL = 50pF, tr = tf = 6ns 13 16 19 ns Input Capacitance CIN - CL = 50pF, tr = tf = 6ns 10 10 10 pF TYPICAL Power Dissipation Capacitance (Per Flip-Flop) CPD - TJ = 25°C, VCC = 5.0V 39 pF 5. Not production tested in die form, characterized by chip design and tested in package. PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com 5 Not production tested in die form, characterized by chip design and tested in package. . High Speed CMOS Logic – 54HC74 Rev 1.0 21/11/17Timing Requirements5 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0 80 100 120 4.5 16 20 24 Minimum Setup Time, D to CLK (Figure 3) tsu 6.0 CL = 50pF, tr = tf = 6ns 14 17 20 ns 2.0 3.0 3.0 3.0 4.5 3.0 3.0 3.0 Minimum Hold Time, CLK to D (Figure 3) th 6.0 CL = 50pF, tr = tf = 6ns 3.0 3.0 3.0 ns 2.0 8.0 8.0 8.0 4.5 8.0 8.0 8.0 Minimum Recovery Time, PRE or CLR Inactive to CLK (Figure 2) trec 6.0 CL = 50pF, tr = tf = 6ns 8.0 8.0 8.0 ns 2.0 60 75 90 4.5 12 15 18 Minimum Pulse Width, CLK (Figure 1) tw 6.0 CL = 50pF, tr = tf = 6ns 10 13 15 ns 2.0 60 75 90 4.5 12 15 18 Minimum Pulse Width, PRE or CLR (Figure 2) tw 6.0 CL = 50pF, tr = tf = 6ns 10 13 15 ns 2.0 1000 1000 1000 4.5 500 500 500 Maximum Input Rise and Fall Times (Figure 1) tr, tf 6.0 CL = 50pF, tr = tf = 6ns 400 400 400 ns Switching Waveforms Figure 1 – Data, Clock and Output Figure 2 – Set, Reset, Clock and Output PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com High Speed CMOS Logic – 54HC74 Rev 1.0 21/11/17 Switching Waveforms continued Figure 3 – Clock to Data DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. PART OBSOLETE - DISCONTINUED