54HCT04_V02 SS | Alldatasheet

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Technical content

www.siliconsupplies.com Die Size (Unsawn) 650 x 540 24 x 21 µm mils Minimum Bond Pad Size 76 x 76 3 x 3 µm mils Die Thickness 280 (±20) 11.02 (±0.79) µm mils Top Metal Composition Al/Si/Cu Back Metal Composition N/A – Bare Si High Speed CMOS TTL Input – 54HCT04 Hex Inverter Logic IC with LSTTL compatible inputs in bare die form  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1µA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 4.5V to 5.5V  TTL / CMOS compatible Input Levels  Function compatible with 54LS04  Full Military Temperature range. Rev 2.0 18 /08 /25 Features:

Ordering Information

Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 280µm(11 Mils) – On request  Assembled into Ceramic Package – On request The 54HCT04 Hex Inverter is fabricated using a small feature size CMOS process that combines high speed LSTTL performance with CMOS low power. The device is commonly used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs and contains six independent inverters with standard push-pull outputs which perform the Boolean function Y = Ᾱ in positive logic. All inputs are protected against ESD and excess voltage transients. Device inputs directly accept LSTTL or CMOS.

Description

Die Dimensions in µm (mils) 650 (24) 540 (21) The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification

www.siliconsupplies.com d High Speed CMOS TTL Input – 54HCT04 Rev 2.0 18/08/25 COORDINATES (µm) PAD FUNCTION X Y 1 1A -220 -55 2 1Y -220 -165 3 2A -110 -165 4 2Y 0 -165 5 3A 110 -165 6 3Y 220 -165

7 GND 220 -55

14 V CC -220 55

CONNECT CHIP BACK TO V CC OR FLOAT Pad Layout and Functions Logic Diagram 650µm (25.59 mils) 540µm (21.26 mils) Function Table INPUTS A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) Pad 14 = V CC Pad 7 = GND Y = Ᾱ 2 3 4 5 6 7 1 9 10 11 12 0,0

www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT04 Rev 2.0 18/08/25 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,V OUT 0 V CC V Operating Temperature Range TJ -55 +125 °C Input Rise or Fall Times tr, t f - 500 ns Recommended Operating Conditions 3 (Voltages referenced to GND) Absolute Maximum Ratings 1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) V CC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) V IN -0.5 to V CC +0.5 V DC Output Voltage (Referenced to GND) V OUT -0.5 to V CC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad I OUT ±25 mA DC Supply Current, V CC or GND, per pad I CC ±50 mA Power Dissipation in Still Air 2 P D 750 mW Storage Temperature Range T STG -65 to 150 °C 3. This device contains protection circuitry to guard against damage due to high static voltages or elect ric fields. However, precautions must be taken to avoid applications of any voltage higher than ma ximum rated voltages to this high-impedance circuit . For proper operation, V IN and V OUT should be constrained to the range GND ≤ (V IN or V OUT ) ≤ VCC . Unused inputs must always be tied to an appropri ate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 4.5V 2.0 2.0 2.0 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V │IOUT │≤ 20µA 2.0 2.0 2.0 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = V CC -0.1V │IOUT │≤ 20µA 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V VIN = V IL │IOUT │≤ 20µA 5.4 5.4 5.4 Minimum High-Level Output Voltage VOH 4.5V VIN = V IL │IOUT │≤ 4.0mA 3.98 3.84 3.70 V 4.5V 0.1 0.1 0.1 5.5V VIN = V IH │IOUT │≤ 20µA 0.1 0.1 0.1 Maximum Low-Level Output Voltage VOL 4.5V VIN = V IH │IOUT │≤ 4.0mA 0.26 0.33 0.40 V

www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT04 Rev 2.0 18/08/25 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Maximum Input Leakage Current IIN 5.5V VIN = V CC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current 3 ICC 5.5V VIN = V CC or GND IOUT = 0µA 1 10 40 µA ≥ -55°C 25°C to 125°C Additional Quiescent Supply Current 5 ΔICC 5.5V VIN = 2.4V, Any One Input. VIN = V CC or GND, Other Inputs I OUT = 0µA 2.9 2.4 mA LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Maximum Propagation Delay, Input A to Input Y (Figure 1,2) tPLH 5V ±10% CL = 50pF, tr = t f = 6ns 15 19 22 Maximum Propagation Delay, Input A to Input Y (Figure 1,2) tPHL 5V ±10% CL = 50pF, tr = t f = 6ns 17 21 26 ns Maximum Output Rise and Fall Time (Figure 1,2) tTLH, tTHL 5V ±10% CL = 50pF, tr = t f = 6ns 15 19 22 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance Per Gate 7 CPD - TJ = 25°C, VCC =5.0V 22 pF 5. Total Supply Current = I CC + ΣΔ ICC. 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: P D = C PD V CC f + I CC V CC .

www.siliconsupplies.com DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY : Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Switching Waveform High Speed CMOS TTL Input – 54HCT04 Rev 2.0 18/08/25 DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2