54HC139

54HC139_V02 SS | Alldatasheet

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High Speed CMOS Logic – 54HC139 Dual 1-of-4 Decoder / Demultiplexer in bare die form Rev 1.1 21/07/20 Features:  Output Drive Capability: 10 LSTTL Loads The 54HC139 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. This device consists of x2 independent 1–of–4 decoders, each decoding a 2 bit address to 1–of–4 active–low outputs. Active–low Selects facilitate the demultiplexing and cascading functions. The demultiplexing function is executed by using the Address inputs to select the desired device output and utilizing the Select as a data input.  Low Input Current: 1µA  Outputs directly inter face CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with 54LS139  Full Military Temperature Range.

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Description

Die Dimensions in µm (mils) 1300 (51)  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT 1400 (55)  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Die Size (Unsawn) 1300 x 1400 51 x 55 µm mils Minimum Bond Pad Size 106 x 106 Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request 4.17 x 4.17 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Page 1 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com d High Speed CMOS Logic – 54HC139 Rev 1.1 21/07/20Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 1G 0.152 0.366 2 1A 0.162 0.132 3 1B 0.422 0.122 4 1Y0 0.59 0.122 5 1Y1 0.772 0.122 6 1Y2 1.088 0.122 7 1Y3 1.088 0.333 8 GND 1.088 0.619 9 2Y3 1.088 0.972 10 2Y2 1.078 1.173 11 2Y1 0.722 1.183 12 2Y0 0.566 1.183 13 2B 0.396 1.153 14 2A 0.162 1.173 15 2G 0.152 0.938 16 VCC 0.122 0.591 CONNECT CHIP BACK TO VCC OR FLOAT Truth Table Logic Diagram 1300µm (51.18 mils) 1400µm (55.12 mils) 0,0 2 3 4 5 6 1011 12 13 14 DIE ID Pad 16 = VCC Pad 8 = GND PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 54HC139 Rev 1.1 21/07/20 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V PART OBSOLETE - DISCONTINUED

High Speed CMOS Logic – 54HC139 Rev 1.1 21/07/20 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 VIN = VIH or VIL │IOUT│≤ 20µA 6.0V 5.9 5.9 5.9 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH V 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.20 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 4 40 160 µA LIMITS PARAMETER 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C 2.0V 115 145 175 4.5V 23 29 35 Maximum Propagation Delay, CL = 50pF, ns tPLH, tPHL Select to Output Y tr = tf = 6ns (Figure 1, 3) 6.0V 20 25 30 2.0V 115 145 175 4.5V 23 29 35 Maximum Propagation Delay, CL = 50pF, ns tPLH, tPHL Input A to Output Y tr = tf = 6ns (Figure 2,3) 6.0V 20 25 30 2.0V 75 95 110 4.5V 15 19 22 Maximum Output Transition Time, CL = 50pF, ns tTLH, tTHL Any Output tr = tf = 6ns (Figure 1,3) 6.0V 13 16 19 Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation TJ = 25°C, Capacitance (Per Decoder)7 CPD - VCC = 5.0V 55 pF Page 4 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED

www.siliconsupplies.com High Speed CMOS Logic – 54HC139 Rev 1.1 21/07/20 DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Pad Description ADDRESS INPUTS 1A, 1B, 2A, 2B When the respective 1–of–4 decoder is enabled these inputs determine which of its four active–low outputs is selected. OUTPUTS 1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 Active–low outputs. These outputs assume a low level when addressed and the appropriate Select input is active. These outputs remain high when not addressed or the appropriate Select input is inactive. CONTROL INPUTS 1G, 2G (Pads 1, 15) Active–low select inputs. For a low level on this input, the outputs for that particular decoder follow the Address inputs. A high level on this input forces all outputs to a high level. Switching Waveforms Figure 2 Figure 1 PART OBSOLETE - DISCONTINUED

Rev 1.1 21/07/20 High Speed CMOS Logic – 54HC139 Page 6 of 6 DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.siliconsupplies.com PART OBSOLETE - DISCONTINUED