X930A INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.0 Nomenclature Overview
- 2.0 Pinout
- 3.0 Signals
- 4.0 Address Map
- 5.0 Electrical Characteristics
- 5.1 Operating Frequencies
- 5.2 DC Characteristics
- 5.3 Definition of AC Symbols
- 5.4 AC Characteristics
- 5.4.1 System Bus AC Characteristics
- 5.4.2 System Bus Timing Diagrams, Nonpage Mode
- 5.4.3 System Bus Timing Diagrams, Page Mode
- 5.4.4 Definition of Real-time Wait Symbols
- 5.4.5 Real-time Wait Function AC Characteristics
- 5.4.6 Real-Time Wait Function Timing Diagrams
- 5.5 AC Characteristics — Serial Port, Synchronous Mode
- 5.6 External Clock Drive
- 5.7 Testing Waveforms
- 6.0 Thermal Characteristics
- 7.0 Product Reference
- 7.1 External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection
- 7.2 Low Clock Mode Frequency
- 7.3 Setting FFRC Bit Clears Only the Oldest Packet in the FIFO
- 7.4 Series Resistor Requirement for Impedance Matching
- 7.5 Pullup Requirement for Full Speed Device and Low Speed Device
- 7.6 Powerdown Mode Cannot Be Invoked Before USB Suspend
- 8.0 Specification Supplement for
- 8.1 Six Endpoint Pairs Functionality
- 8.2 DC Characteristics
- 8.3 Extended Data Float (EDF) AC Timing Feature
- 9.0 Device Errata
- 10.0 Datasheet Revision History
COPYRIGHT © INTEL CORPORATION, 1997 February 1997 Order Number: 272917-003 8x930A x UNIVERSAL SERIAL BUS MICROCONTROLLER The 8x930A x USB microcontroller is based on an 8xC251S x microcontroller core. It consists of standard 8xC251Sx peripherals plus an added USB function. The 8x930A x uses the standard instruction set of the MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification. ■ Complete Universal Serial Bus Specification 1.0 Compatibility — Supports Isochronous and Non-isochronous Data — Bidirectional Half-duplex Link ■ On-chip USB Transceiver ■ Serial Bus Interface Engine (SIE) — Packet Decoding/Generation — CRC Generation and Checking — NRZI Encoding/Decoding and Bit-stuffing ■ USB Reset Interrupt ■ Four Transmit FIFOs — Three 16-byte FIFOs — One Configurable FIFO (up to
1 Kbyte)
■ Four Receive FIFOs — Three 16-byte FIFOs — One Configurable FIFO (up to ■ Automatic Transmit/Receive FIFO Management ■ Suspend/Resume Operation ■ Three New USB Interrupt Vectors — USB Function Interrupt — Start of Frame — Suspend/Resume ■ Phase-locked Loop — 12 Mbps or 1.5 Mbps Data Rate ■ Low Clock Mode ■ User-selectable Configurations — External Wait State — Address Range — Page Mode ■ Real-time Wait Function ■ 256-Kbyte External Code/Data Memory Space ■ On-chip ROM Options — 0, 8, or 16 Kbytes ■ 1 Kbyte On-chip Data RAM ■ Four Input/Output Ports — 1 Open-drain port — 3 Quasi-bidirectional Ports ■ Programmable Counter Array (PCA) — 5 Capture/Compare Modules ■ Serial I/O Port (UART) ■ Hardware Watchdog Timer ■ Three Flexible 16-bit Timer/Counters ■ Power-saving Idle and Powerdown Modes ■ Register-based MCS ® 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, or Doublewords ■ Code Compatible with MCS 51 and MCS
251 Microcontrollers
■ 6 or 12 MHz Crystal Operation
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The product may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725 COPYRIGHT © INTEL CORPORATION, 1997
8x930Ax UNIVERSAL SERIAL BUS MICROCONTROLLER iv Figures 4. 8 Tables 7. 8 20. 8
Figure 1. 8x930A x Internal Block Diagram † For details, see the USB module block diagram.
2 ADVANCE INFORMATION
Figure 2. USB Module Block Diagram
1.0 NOMENCLATURE OVERVIEW
Figure 3. Product Nomenclature Table 1. Description of Product Nomenclature
3 With ROM
Table 2. Proliferation Options
4 ADVANCE INFORMATION
2.0 PINOUT
Figure 4. 8x930A x 68-pin PLCC Package Figure 4 illustrates the 8x930Ax PLCC package. categories. Table 5 describes the signals. Note: Reserved pins must be left unconnected.
Table 3. 68-pin PLCC Pin Assignment
18 V SSP 41 RST 64 Reserved
19 V CCP 42 PLLSEL1 65 PSEN#
6 ADVANCE INFORMATION
Table 4. 68-pin PLCC Signal Assignments Arranged by Functional Category
3.0 SIGNALS
Table 5. Signal Descriptions UCONFIG0. See also RD#, PSEN#. data lines for external memory. I/O Programmable Counter Array (PCA) Input/Output Pins. the access is off-chip. The value of EA# is latched at reset. ries the upper address bits (A15:8) and the data (D7:0).
8 ADVANCE INFORMATION
data rate (see Table 8 on page 12). RD0 and RD1 in configuration byte UCONFIG0 (see RD#). tion byte UCONFIG0 (See PSEN#). mode returns the chip to normal operation. and SOF token or artificial SOF is detected. mode, it is the timer 2 clock output. Table 5. Signal Descriptions (Continued) ries the upper address bits (A15:8) and the data (D7:0).
determines the count direction: 1 = up, 0 = down. by controlling the WAIT# input signal on the port 1.6 input. ries the upper address bits (A15:8) and the data (D7:0).
10 ADVANCE INFORMATION
versal Serial Bus Microcontroller User’s Manual.
4.0 ADDRESS MAP
Table 6. Memory Signal Selections (RD1:0) Table 7. 8x930A x Address Map
- Eighteen address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
- Data in this area is accessible by indirect addressing only.
- Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
- This reserved area returns unspecified values and writes no data.
- Data is accessible by direct and indirect addressing.
- Data is accessible by direct, indirect, and bit addressing.
- The special function registers (SFRs) and the register file have separate internal address spaces.
- Data is accessible by direct, indirect, and register addressing.
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.0 ELECTRICAL CHARACTERISTICS
OPERATING CONDITIONS † TA (Ambient Temperature Under Bias): NOTE: Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. † WARNING : Stressing the device beyond the “Absolute Maximum Ratings” may cause perma- nent damage. These are stress ratings only. Oper- ation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
12 ADVANCE INFORMATION
5.1 Operating Frequencies
Figure 5. Clock Circuit Table 8. Frequency Selection and Operating Frequency
3 MHz 6 MHz 2 T OSC /state PLL Off
6 MHz (3) 12 MHz 2 T OSC /state PLL Off
12 MHz (3) 12 MHz 1 T OSC /state PLL On
- Other PLLSEL x combinations are not valid.
- The sampling rate is 4X the USB rate.
- The number of XTAL clocks in one state depends on the PLLSELx selections. When the CPU is oper-
ating at low clock mode (3 MHz), there are four TOSC per state for the PLLSEL2:1:0 = 100 and 110.
- The AC timing specification (Table 11) defines the following symbol: CPU frequency = FCLK = 1/TCLK .
3 MHz
5.2 DC Characteristics
Table 9. DC Characteristics at Operating Conditions
- Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
tion when the address lines are stabilizing.
- The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
14 ADVANCE INFORMATION
100 PLLSEL = 110
30 PLLSEL = 001
55 PLLSEL = 100
6 MHz – LS
Table 9. DC Characteristics at Operating Conditions (Continued)
- Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
tion when the address lines are stabilizing.
- The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
5.3 Definition of AC Symbols
3 MHz – FS
150 PLLSEL = 110
12 MHz – FS
45 PLLSEL = 001
3 MHz – LS
75 PLLSEL = 100
Table 10. AC Timing Symbol Definitions
- Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
to sink current greater than the listed test conditions.
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 cause the V
tion when the address lines are stabilizing.
- The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
16 ADVANCE INFORMATION
5.4 AC Characteristics
5.4.1 SYSTEM BUS AC CHARACTERISTICS
Table 11. AC Characteristics at Operating Conditions
83.33 T CLK ns
- Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies.
- XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
- M= 0,1 is the extended ALE state.
- Specifications for PSEN# are identical to those for RD#.
- N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
Table 11. AC Characteristics at Operating Conditions (Continued)
- Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies.
- XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
- M= 0,1 is the extended ALE state.
- Specifications for PSEN# are identical to those for RD#.
- N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
18 ADVANCE INFORMATION
5.4.2 SYSTEM BUS TIMING DIAGRAMS, NONPAGE MODE
Figure 6. 8x930A x Code Fetch, Nonpage Mode
20 ADVANCE INFORMATION
5.4.3 SYSTEM BUS TIMING DIAGRAMS, PAGE MODE
Figure 9. 8x930A x Code Fetch, Page Mode † During a sequence of page hits, PSEN# remains low until the end of the last page hit cycle.
22 ADVANCE INFORMATION
5.4.4 DEFINITION OF REAL-TIME WAIT SYMBOLS
5.4.5 REAL-TIME WAIT FUNCTION AC CHARACTERISTICS
Table 12. Real-time Wait Timing Symbol Definitions Table 13. Real-time Wait AC Timing Specifications
- Real-time Wait function has a critical timing for instruction read. It is not advisable to use this feature
for instruction read during page mode.
5.4.6 REAL-TIME WAIT FUNCTION TIMING DIAGRAMS
Figure 12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State)
24 ADVANCE INFORMATION
Figure 13. External Data Write (Nonpage Mode, Real-time Wait State)
Figure 14. External Data Read (Page Mode, Real-time Wait State)
26 ADVANCE INFORMATION
Figure 15. External Data Write (Page Mode, Real-time Wait State)
5.5 AC Characteristics — Serial Port, Synchronous Mode 0
Figure 16. Serial Port Waveform — Synchronous Mode 0 Table 14. Serial Port Timing — Synchronous Mode 0 †TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
28 ADVANCE INFORMATION
5.6 External Clock Drive
Figure 17. External Clock Drive Waveforms Table 15. External Clock Drive
0.7 VCC
5.7 Testing Waveforms
Figure 18. AC Testing Input, Output Waveforms Figure 19. Float Waveforms a min of VIH for a logic 1 and VOL for a logic 0.
30 ADVANCE INFORMATION
6.0 THERMAL CHARACTERISTICS
7.0 PRODUCT REFERENCE
8x930Ax Universal Serial Bus microcontroller.
7.1 External Bus Timing and
7.2 Low Clock Mode Frequency
7.3 Setting FFRC Bit Clears Only the
7.4 Series Resistor Requirement for
potentially introduce bit errors.
7.5 Pullup Requirement for Full
7.6 Powerdown Mode Cannot Be
Table 16. Thermal Characteristics
8.0 SPECIFICATION SUPPLEMENT
8.1 Six Endpoint Pairs Functionality
cleared and the 6 endpoint pair feature is disabled. interrupts for the additional endpoint pairs.
8.2 DC Characteristics
8.3 Extended Data Float (EDF) AC
Table 17. SIx Endpoint Pair Feature Table 18. Effect of “EDF#” on Wait States
32 ADVANCE INFORMATION
Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode
- Device configured with default data float timing for fast memory interface.
Table 20. 8x930A x3 and 8x930A x4 Default and Extended Data Float Timings
- Worst-case numbers based on silicon data collected to date.
- Device configured with default data float timing for fast memory interface.
- Device configured with extended data float timing for slow memory interface.
- The values listed are for 12 MHz. For 6 MHz, the value of T
CLK will double and will equal 166.6 ns.
- M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
Table 21. 8x930A x3 and 8x930A x4 Real-time Wait State AC Timing Specifications Table 20. 8x930A x3 and 8x930A x4 Default and Extended Data Float Timings (Continued)
- Worst-case numbers based on silicon data collected to date.
- Device configured with default data float timing for fast memory interface.
- Device configured with extended data float timing for slow memory interface.
- The values listed are for 12 MHz. For 6 MHz, the value of T
CLK will double and will equal 166.6 ns.
- M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
34 ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
9.0 DEVICE ERRATA
The 8x930A x may contain design defects or errors known as errata. Characterized errata that may cause the 8 x930A x’s behavior to deviate from published specifications are documented in a speci- fication update. Refer to the 8x930Ax (8x930AD, 8x930AE) Specification Update (Order Number updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
10.0 DATASHEET REVISION HISTORY
This datasheet is valid for A-2 through A-4 step devices. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This (-003) revision of the 8 x930A x datasheet replaces earlier product information. The following changes were made in this version: 1. Added “Specification Supplement for 8x930Ax3 and 8x930Ax4” on page 31. 2. The following AC Characteristics were changed: T AVLL , TAVDV 1, TAVRL , TAVWL 1. 3. I CC characteristics updated.