27C513 INTEL | Alldatasheet
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intel. 27C513 PAGE-ADDRESSED 512K (4 x 16K x 8) UV ERASABLE PROM @ Paged Organization @ 170 ns Access Time — Reduced Physical Address Requirement @ Two Line Control —No Bank Switching Logic Needed mw Low Power Software Cal Cc —30 mA max. Active . tet ae a oaneeity — 100 1A max. Standby m@ Automatic Page ir Compati Standard — Resets to Page 0 on Power Up and . EPROM be with Industry On Demand with RST Signal —Direct 27128A Compatibility @ TTL and CMOS Compatible — 28-Pin Cerdip The Intel 27C513 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only Memory. It is organized as 4 pages of 16K 8-bit words. The 27C513’s paged organization brings 64 Kbyte storage capacity to existing 128K EPROM-based designs and to popular 8-bit microprocessor or microcontrol- ler systems that have 64 Kbyte total addressing capability, The 27C513 provides an ideal means of quadru- pling current 16 Kbyte code space. The 27C513's large storage capability of 64 Kbytes and 170 ns access time enables it to function as a high density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized application software can reside in a 27C513 EPROM directly on a system's memory bus. This permits immedi- ate microprocessor access and execution of software and eliminates the need for time-consuming disk ac- cesses and downloads. The 27C513 has an automatic page clear circuit for ease of use of the page-addressed organization. The page-select latch is automatically cleared to the lowest order page upon system power up. 5 Two-line control and industry standard 28-pin packaging are features common to all Intel high-density EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding, or choosing between nonvolatile memory alternatives. The 27C513 is manufactured using Intel’s 1 micron CHMOS* III-E technology. CHMOS is a patented process of Intel Corporation. October 1901 5-23 (Order Number: 290231-003
Figure 1. Block Diagram ‘
- Intel “Universal Site” compatible EPROM pin configurations are shown in the blocks adjacent to the 27C513 pins.
intel. 270513 . EXTENDED TEMPERATURE available with 168 +8. hour, 125°C dynamic burn-in (EXPRESS) EPROMs: using Intel's standard bias configuration. This pro- cess exceeds or meets most industry specifications The Intel EXPRESS EPROM family is a series of of burn-in. The standard EXPRESS EPROM operat- electrically programmable read only memories which _ing temperature range is 0°C to 70°C. Extended op- have received additional processing to enhance — erating temperature range (—40°C to +85°C) EX- product characteristics. EXPRESS processing is © PRESS products are available: Like all.’ Intel available for several densities of EPROM, allowing EPROMs, the EXPRESS EPROM family is inspected the choice of appropriate memory size to match sys- _‘to 0.15 electrical AQL. This may allow the user to tem applications. EXPRESS EPROM products are reduce or eliminate incoming inspection testing. EXPRESS EPROM PRODUCT FAMILY EXPRESS OPTIONS PRODUCT DEFINITIONS 270513 VERSIONS: [a| octw+7c | 168+8 | | SpeedVersions | __Cerdip_—| | t | =40rcto+esc | None | READ OPERATION DC CHARACTERISTICS Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for: Lp27C513 Test Conditions | min [Max | [ies | Var Standby Curent way |__| 1.0 | C= Vn Ore = Vad loo, Voc Active Current(mA) [| 50_—| OE/Vpp = CE= Vit Veg Active Current OE/Vpp = CE = Vit, Tambiont = 85°C at High Temperature (mA) NoTE: 1. The maximum current value is with outputs Op to O7 unloaded. oO svt 2865 Vee Aa? vbw 30 ads 26ba, ue acs oo ipa ass PAs no J l J l J ade apa adds 2be pve : Yeeq Ao] to vp 0, As 7 % " ‘aed Os Binary Sequence from Ap to Ais poozsi~4 % Cy 12 = Os o, Ld is sshd o, 200281-3 OENVpp = +8VR=1KN Voc = +5V Vss = GND CE = GND Burn-in Bias and Timing Diagrams: 5-25
intel. 27¢813 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is @ production data sheet. The specifi- ting T cations are subject to change without notice. Operating Temperature” * - Dp . Maximum Ratings” may cause permanent damage. Voltage on Any Pin with may affect device reliability. Voltage on Ag with Vpp Supply Voltage with Respect to Graund . Voc Supply Voltage with . READ OPERATION DC CHARACTERISTICS TTL and NMOS Inputs lus [input Load Current | [foot] 10 | us Wn = ovtos.sv Ho [Output Leakage Current | ff 10 [na Nour = oviossv | tse NocCurent Standby || [to [ma CE =v Voc Current Active ICE = Vit = 5MHz, lout = 0 leer _epOurentread | os | Tf 0 WA NMep= Voc Mu Hinputtow vottage (+ 10% suppin| 1 | -os | | os |v | | Mini put tigh vonage (210% Sum] | 20 | Naoto v | _———*d Now foutput Low Vottage ee A Non _ Joutput High Vottage | fee | TT fon =400na | los__lOutputshortircuitCurrent | 6 | | | 100 [mal Mer __WepReadvotage | 7 \\Vco~07] | Vo |v {| |Page Latch Clear v Voc Supply Voltage NOTES: Maximum DC voltage on output pins is Voc + 0.5V which may overshoot to Voc + 2V for periods less than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Automotive versions. 3. Typical limits are at Voc = 5V, Ta = +25°C. 4. is Voc +0.2V. All other inputs can have any value within spec. 5. Maximum current value is with outputs Op to O7 unloaded. 6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100% tested. 7. Voc must be applied simultaneously or before OE/Vpp and removed simultaneously or after OE/Vpp. 8 Mebimum active power usage isthe sum of lpp and lac, The maximum curent value fs with no loading on outputs Opto 5-26
intel. 270513 DC CHARACTERISTICS CMOS Inputs : [Symboi] Parameter [Notes] min [Typi]|_Max [Units] Test Condition | ju [rpatoadOures | | oor] 10 [oA \\va=Ovessv | luo ouputteskagecuren | | | | #10 [wa Vour=ovwsaev | Tg at Oey ec ciao ec cc: [Voc Current Active CE = Vit it = 5 MHz, lout = 0 mAl ha lrpatowvenape (sion Summ | | oa | [oe [v[ i Nar [npu rgh Vonage (210% Suwem) | | O7voo | [vecroalv | Output Low Voltage [oT oe Tv f= 2tma | Won [ouputrighvorage | Nec oal [|v [w= -25ma | los oun soncreunGurent [6] | | om] | NOTES: Maximum DC voltage on output pins is Voc + 0.5V which may overshoot to Voc + 2V for periods less than 20 ns. 2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS and Automotive versions. 3. Typical mits are at Voc = 5, Ta = +25°C. 4. is Voc +0.2V. All other inputs can have any value within spec. 5. Maximum currant vaiue is with outputs Op to O7 unloaded. 6. Output shorted for no more than one second. No more than one output shorted at a time. Iog is sampled but not 100% tested. 7. Voc must be applied simultaneously or before OE/Vpp and removed simultaneously or after OE/Vpp. 8. Maximum active power usage is the sum of Ip and Iog. The maximum current value is with no loading on outputs Op to PAGE-SELECT WRITE AND PAGE-RESET OPERATION 5 | AC CHARACTERISTICS [tits Test [min [max | Conditions Cio endl We [0 [fe |e = | Wie Pe With es [wef Wate Recoveytine [2 [|= [| | [tos | DataSeuptime | so | | ms | OE NeW _| [Tie [Data timne | 20 [| ne | OE Npe= vn _| CEtowiteseuptine | _o | | re | OE pp = Vw _| WE Low from OE/Vpp High Delay Time [Tins Resettowtine oo [ip rd Resetio Adresse’ [150 | | re | —id NOTES: 1. Voc must be applied simultaneously or before OE/Vpp and removed simultaneously or after OE/Vpp. 2. Typical values are for Ta = 25°C and nominal supply voltages. 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven—see timing diagram. 4, The maximum current value is with outputs Og-O7 unloaded. 5. Packaging Options: No prefix = Cerdip. 6. RST function is available only on parts with 6-digit suttix. 5-27
intel. 270513 ee CAPACITANCE(2) Ty = +25°C,f = 1 MHz [ symbor | Parameter | typi) | Max | units | Conditions | | cw __| tnpurCapacttancs | 4 [|e | oF | v=o | Output Capacitance | 8 | 12 | pF | Vour=ov | ‘AC TESTING INPUT/OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT Iw cS, Ine = = —— Cpe INPUT rs: POINTS: OUTPUT sami —— DEVICE eas UNDER © OUT 200201-5 Test to ‘AG Testing inputs are driven at 2.4V for a Logic 1 and 0.48V for a ia 290231-6 Logic 0. Timing measurements are made at 2.0V for a Logic 1 ©. = 100 pF ‘and 0.8V for a Logic 0. Cy Includes Jig Capactance AC CHARACTERISTICS 0°C < Ta < +70°C [versions Voc #10% | 27cs13-r70v10 | 276513-200v10 | 276513-250V10 [Unite Test Conaitions cl a a Vep = Vit ltcz_ [OE tooupurdewy | ro [200 || 280 | ne [OE Vee = Vn_| fox [OEMepHighto Ourpurrioat! o | 55 [ o | s5 | 0 | 60 | ms (=m | | Output Hold from Addresses: CE = OE/ ICE or OE/Vpp, Whichever Ver = Viv Occurred First NOTES: 1. Typical values are for Ta = 25°C and nominal supply voltages. 2, This parameter is only sampled and is not 100% tested. Output Float is defined as the Point where data is no longer driven—see timing diagram. ‘3. The maximum current value is with outputs O)-O7 unloaded. 4. Packaging: No prefix = Cerdip. AC CONDITIONS OF TEST 5-28
intel. 270813 AC WAVEFORMS FOR READ OPERATION 7 uw oeee ADDRESSES WALD Vu sees vie Va ates “tog(?)- Vn OE/Vep Vu eoes on? tort tace: ton: . Vw eee ‘ourPuT Hiohz VALID OUTPUT Vie eee Vin: - 4 5 We Me . 290281-7 5-29
intel. 270513 AC WAVEFORMS FOR PAGE-SELECT WRITE OPERATION me (Es = tow! . AA tes _ two! Twn We : tot 8, ton DEN ep tos woo fF Dz Dy OUTPUTS 290231-8 AC WAVEFORMS FOR PAGE-RESET OPERATIONS _ l= 290231-9 NOTES: 1. Typical values are for T, = +25°C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE/Vpe may be delayed up to tce-toe atte the fling edge of CE without impact on toe. 4. Write may be terminated by either CE or WE, providing that the minimum tow requirement is met before bringing WE high or that the minimum twp requirement is met before bringing CE high. 5. OE/Vpp must be high during write cycle. 5-30
mode. All inputs are TTL levels except for OE/Vpp and 12V on Ag for inteligent Identifier mode. Table 1. Operating Modes
- Addresses are don't care for page selection. See Table 2 for Diy values.
- See Table 2 for Voc and Vpp voltages.
of device selection. Assuming that addresses are _ voltage (Voip), the latch clear circuit is disabled. edge of OE/Vpp, assuming that has been low . . tacc~tog. WE is held high during read operations. should be tied to an active low system reset signal. is brought to TTL Low (Vit). selected by normal random access within the . grams such that the number of page changes is min- particular memory deviee. imized. This allows maximum system performance. write, the program counter will be incremented to the ed to the WRITE system control line. Table 2. Page Selection Data The power switching characteristics of EPROMs re-
intel. 270513 properly selected decoupling capacitors. It is recom- tifier mended that a 0.1 uF ceramic capacitor be used on inteligent Iden r Mode every device between Voc and GND. This should be The inteligent Identifier Mode allows the reading out a high frequency capacitor of low inherent induc- _of a binary code from an EPROM that will identify its tance and should be placed as close to the device manufacturer and type. This mode is intended for as possible. In addition, a 4.7 2F bulk electrolytic use by programming equipment for the purpose of capacitor should be used between Vcc and GND for automatically matching the device to be pro- every eight devices. The bulk capacitor should be grammed with its corresponding programming algo- located near where the power supply is connected rithm. This mode is functional in the 25°C +5°C to the array. The purpose of the bulk capacitor is to ambient temperature range that is required when ‘overcome the voltage droop caused by the inductive programming the device. effects of PC board traces. This inductive effect should be further minimized through special layout To activate this mode, the programming equipment considerations such as larger traces and gridding must force 11.5V to 12.5V on address line Ag of the (refer to High Speed Memory System Design Using EPROM. Two identifier bytes may then be se- the 2147H, AP-74). In particular, the Vgg (Ground) quenced from the device outputs by toggling ad- plane should be as stable as possible. dress line Ag from Vi. to Vix. All other address lines must be held at Vi, during the inteligent Identifier Mode. PROGRAMMING Byte 0 (Ag = Vi.) represents the manufacturer code Caution: Exceeding 14.0V on OE/Vpp will perma- —_and:byte 1 (Ag = Vix) the device identifier code. ently damage the 270513. These two identifier bytes are given in Table 1. initially, and after each erasure, ‘all bits of the EPROM are inthe “1” state. Data is introduced by selectively programming “0s” into the dasired bit lo- Quick Pulse Programming Algorithm cations. Although only “Os” will be programmed, Intel's 27C513 EPROM can be programmed using both “1s” and “Os” can be present in the data word. the Quick-Putse Programming algorithm, developed The only way to change a “0” to a “1” is by ultravio- by Intel to substantially reduce the throughput time let light erasure. in the production programming environment. This a- gorithm allows these devices to be programmed as The EPROM is in the programming mode when the fast as fourteen seconds, almost a hundred fold im- a) ‘OE/Vpp input is raised to its programming voltage provement over previous algorithms. Actual pro- (see Table 2) and CE is at TTL-low. The data to be gramming time is a function of the PROM program- Programmed is applied 8 bits in parallel to the data mer being used. output pins. The levels required for the address and data inputs are TTL. The Quick-Pulse Programming algorithm uses initial pulses of 100 ps followed by a byte verification to determine when the address byte has been suc- Program Inhibit cessfully programmed. Up to 25 100 ps pulses per , byte are provided before a failure is recognized. A Programming of multiple 27C513s in parallel with di- flowchart of the Quick-Pulse Programming Algorithm ferent data is easily accomplished by using the Pro- is shown in Figure 3. gram Inhibit mode. A high-level CE input inhibits the other 27C513s from being programmed. For thé Quick-Pulse Programming algorithm, the en- tire sequence of programmit ises and byte verifi- Except for CE, all inputs of the parallel 270513s may cations is performed at Vor putone anc bai Ver at be common. A TTL low-level pulse applied to the CE 12,75V..When programming of the EPROM has input with OE/Vpp at its programming voltage will been completed, all bytes should be compared to program the selected 27C513. the original data with Voc = Vpp = 5.0V. Verity A verify (read) should be performed on the pro- grammed bits to determine that they have been cor- rectly progeammed The verify is performed with OE/ Vpp and at Vi_ and Voc is at its programming voltage. Data should be verified tpy after the falling edge of CE. 5-33
Figure 3. 27C513 Quick-Pulse Programming Flowchart
posed to these types of lighting conditions for ex- age. TABLE 2. DC PROGRAMMING CHARACTERISTICS 1, Voc must be applied simultaneously or before OE/Vpp and removed simultaneously or after OE/Vpp.
- The maximum current value is with outputs Op-O7 unloaded.
intel. 270513 SSE AC PROGRAMMING CHARACTERISTICS Ta = 25°C +8°C [timite TT Conattions | min | typ [| max | units | (Note) [us| AddressSeuptime | 2 [Tt ws | [tors | OEVepSeuptime | 2 [Tt ws [| [os _[ datasouptime | 2 | Ts [| C [wu | Addresstoidtime “To TT ws | C [ton | datetime Te? TTT lw | Cd | tore | OutputEnabieto OutputFiostDeley | 0 [| 190 | ns | Note) | [ves | vecseuptime Te Ts | wnoteny | | tow | CE ProgramPusewiah | 95 [100 | 105 | us [| [torn | OEVepHodTime | 2 | Ts | | tov | atavaidtomoe TT Ps [| |'wa___| OEWVepRecoverytime | 2 [Ts [| eo During Programming *AC CONDITIONS OF TEST NOTES: 1. Voc must be applied Simultaneously or before OE/Vpp 5-36
intel. 270513 Sse PROGRAMMING WAVEFORMS Vm set Xone | Va _ = TI os Lot sov Vee tore so Te sv = | | Ma oes ‘oar Vu tod Lg ° oo Ve we ve 290281-11 2. toe and torp are characteristics of the device but must be accommodated by the programmer. 3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the four 16 Kbyte pages. See Page Select Write AC and DC Characteristics for information on page selection operations.
REVISION HISTORY
[Number[ Description Removed “Advance Information” Classification. Revised twp from 50 ns to 100 ns Revised Vein (3.5V) from Min to Typ 5-37