D8755A-2 INTEL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

Table 1. Pin Description ADs_10, GE, CEA) are latched in at the trailing edge of ALE. address are applied to the bus lines when ALE is high. uring an I/O cycle, Port A or B is selected based on the latched value of ADo. buffers present data on the bus. | not affect !/O operations. comes from an 1/0 port. If itis low the output data comes from the PROM. ADo-7. The state of 1O/M is ignored. after it has been forced low by CE; low, CE high, and ALE high. and a 0 was previously latched from Dg AD}. selected by a 1 latched from ADp and a 0 from AD}. RESET RESET: In normal operation, an input high on RESET causes all pins in Ports A . and B to assume input mode (clear DDR register). should be tied to Voc ("1"). [ vss |__| GROUND: Reference. when the 87554 is being read.

e FUNCTIONAL DESCRIPTION A port can be read out when the latched Chip En- ’ ables are active and either RD goes low with |O/M high, or IOR goes low. Both input and output mode PROM Section bits of a selected port will appear on lines ADg-7. The 8755A contains an 8-bit address latch which To clarify the function of the I/O Ports and Data Di- allows it to interface directly to MCS®-48 and rection Registers, the following diagram shows the MCS®-85 processors without additional hardware. configuration of one bit of PORT A and DDR A. The same logic applies to PORT B and DDR B. The PROM section of the chip is addressed by the 11-bit address and the Chip Enables. The address, TE; and CE, are latched into the address latches on 8755A ONE BIT OF PORT A AND DDR A the falling edge of ALE. If the latched Chip Enables are active and 10/M is low when AD goes low, the oar ' 1 contents of the PROM location addressed by the Se > Hl latched address are put out on the ADo-7 lines (pro- sux i vided that Vpp is tied to Voc). \\ 1/0 Secti ee jon o> SAT ol The I/O section of the chip is addressed by the veker 1 latched value of ADo-;. Two 8-bit Data Direction vnire oon ' Registers (DDR) in 8755A determine the input/out- \\ put status of each pin in the corresponding ports. A De C7 1 “0” in a particular bit position of a DDR signifies that -— the corresponding 1/O port bit is in the input mode. A neaora pj i it posi if 231795-3 manner the |/O ports of the 8755A are bit-by-bit pro- WRITE DOR A = (IOW = 0) « (CHIP ENABLES ACTIVE) * (DDR grammable as inputs or outputs. The table summa- A ADDRESS SELECTED) =D = 0) + (OR = 0 # CHP rzes port and DDR designation. DDR’s cannot be BRAS Lek Acta mle Peoae tas ee * NOTE: [aDi[Ado| Selection || We PAS not united by 107M poe Note that hardware RESET or writing a zero to the DDR latch will cause the output latch’s output buffer Port A Data Direction Register (DDR A) to be disabled, preventing the data in the Output Port B Data Direction Register (DDR 8)! —_Latch from being passed through to the pin. This is ‘equivalent to putting the port in the input mode. Note When TOW goes low and the Chip Enables are ac- _also that the data can be written to the Output Latch tive, the data on the ADo-7 is written into 1/O port even though the Output Butfer has been disabled. selected by the latched value of ADo-;. During this This enables a port to be initialized with a value prior operation all I/O bits of the selected port are affect- to enabling the output. ed, regardless of their |/O mode and the state of |1O/ - > M. The actual output level does not change until The diagram aiso shows that the contents of PORT TOW returns high. (Glitch free output.) Aand PORT B can be read even when the ports are configured as outputs. | 1-61

ERASURE CHARACTERISTICS SYSTEM APPLICATIONS ) The erasure characteristics of the 8755A are such that erasure begins to occur when exposed to light System Interface with 8085AH with wavelengths shorter than approximately 4000 j ‘Angstroms (A). It should be noted that sunlight and A system using the 8755A can use either one of the certain types of fluorescent lamps have wavelengths _two I/O Interface techniques: in the 3000-40004 range. Data show that constant © Standard 1/0. exposure to room level fluorescent lighting could Memory Mapped I/O erase the typical 8755A in approximately 3 years while it would take approximately 1 week to cause _f a standard I/O technique is used, the system can erasure when exposed to direct sunlight. If the use the feature of both CE and CE}. By using a 8755A is to be exposed to these types of lighting __ combination of unused address lines Ay1_15 and the conditions for extended periods of time, opaque la- Chip Enable inputs, the 8085AH system can use up bels are available from Intel which should be placed —_to § 8755A's without requiring a CE decoder. See over the 8755A window to prevent unintentional era- Figure 4. sure. Ita memory mapped I/O approach is used the The recommended erasure procedure for the 8755 —_ 755A will be selected by the combination of both is exposure to shortwave ultraviolet light which has @__the Chip Enables and IO/M using ADg_15 address wavelength of 2537 Angstroms (A). The integrated ines. See Figure 3. dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 min- utes using an ultraviolet lamp with a 12000 »W/cm2 power rating. The 8755A should be placed within ‘one inch from the lamp tubes during erasure. Some = ’ lamps have a filter on their tubes and this filter rt> should be removed before erasure. Ne] Th PROGRAMMING exoa} Cy EPROM portions of the 8755A are in the “1” state. Te Information is introduced by selectively program: 2ST TT ming “0” into the desired bit locations. A pro- Ay Ae AD CUO grammed “0” can only be changed to a “1” by UV im Aue OH ntaay erasure. asa The 8755A can be programmed on the Intel Univer- 231735-4 (UP), and iUPF: rogrammin sa rporammer (UP), and IUPF87444 programming Figure 3. 8755A in 8085AH System (Memory-Mapped 1/0) The program mode itself consists of programming a single address at a time, giving a single 50 msec . pulse for every address. Generally, it is desirable to have a verify cycle after a program cycle for the same address as shown in the attached timing dia- gram. In the verify cycle (Le, normal memory read cycle) ‘Vpp’ should be at + 5V. 1-62 |

intel. 8755A a i COT, ; To a HERR Fa} § IH “ie bet] 2 ] COO 3 lain ; i 7 a) EE TTT "ag = : 5 |e |g soo Coo, | 5 z pi : Figure 4, 8755A in 8085AH System (Standard 1/0)

s75sa intel. ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- ) 1 . cations are subject to change without notice. Voltage on any Pin These are stress ratings ony. Operation beyond the with Ri ceeeeeeee = O.5VtO+7V “ ¥ fons” i La jespect to Ground to+ “Operat Conaitions [pot recommended Had nd ox. D.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = Vpp = 5V +5% [ Symbot | __ Parameter | win | Max unit_| Test Conditions Input Low Voltage | -os | os | v_ | Voo=sov Input High Voltage | 20 | vec+os | v | Voo=sov Qutput Low Voltage [| ots Tv ema Output High Voltage Pes fT to = 400 nA | Input Leakage Pf to nw | sss viv < Veo | Output Leakage Curent | [to [wa | 0.45 = Vour < Voo Voc Supply Current | | to mm PO [too | Voo Supply Current a Capacitance ofinputsutter | | 10 | oF | toe tune | Capacitance tO Butter | | 8 pF | tos tue | D.C. CHARACTERISTICS—PROGRAMMING Ta = 0°C to 70°C, Voc = 5V +5%, Vss = OV, Vop = 25V +1V [_sympot [Parameter [min [typ [Max [unit | Programming Voltage (during Write toEPROM) | 24 | 25 [ 26 |v | [too _| Prog Supply Current [| fs [0 | ma | 1-64 |

A.C. CHARACTERISTICS ! Ta = O°C to 70°C, Voc = BV +5% ee ee [ty | cK Pusewian ———SSSSCS~dSCTCd | [te [ek Pusowian ———SSS~sC Tide [muy | cixrisoanarattme | | Ts [wm | Address totatchSetuptine | _so | ——+| = | [Tux | Adan HoT ateriaen | eo | |» | fil [ue | Lateh to READ/WRITE Contr | 100 | rs _| [tao | Vat Data Out Delay romREADGonor |__| v70_~| me [mo | Adress Stabioto Data Outvais'> | +t 450 | ne _—| a [ta | _READ/WRITE ConvoltoLachénabie | 20 [| rs _| [too | _READ/WRITE Convoiwiatn | a5] | rs | [tee | Portinputsetuptime ——S~—~‘idSCiaSTSSCd | [tee | PorinputhoisTine Conver «dts | | [tan [READY HOLD TimetoCGontoi_———«t | 60 | ns | [tev | Recovery Timobetween Contos | a0] =i | [tae | READ Contolto Data usnabie [10 | | = | NOTES: Coan = 150 pF. *Or Tap — (Tat + Tic), whichever is greater. **Defines ALE to Data Out Valid in conjunction with Ta. A.C. CHARACTERISTICS—PROGRAMMING ~ Ta = 0°C to 70°C, Voc = 5V +5%, Vgg = OV, Vpp = 25V +1V [__Symbor | ___ Parameter [min | typ [Max [unit [wes | Oaaseuptine [0 | ‘|i | [ts | Prog PueeSeuptine [2 | + Sie | [uw | Prog PuiseHoatime [2 | | +d _| [tea | Prog Puiseriso Time | oor_| 2 | —+| = _| [we | _ProgPuseraiTine | oon | 2 | | ms _| [was | PregPusowias | «5 [0 | «ds | | 1-65

8755A intel ° A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT | a 7 ED os “ os 231735-7 - AC. Testing: inputs are driven at 2.4V for a Logic "1" and 0.45V = 150 pF 291735-8 re Logie Fo nna Mesaurereria ‘are made at 2.0V for a {Includes Jig Capacitance WAVEFORMS CLOCK SPECIFICATION FOR 8755A © th ty eve 201795-9 PROM READ, I/O READ AND WRITE ‘om ae | | - 7 te of | 291795-10 Please note that CE; must remain low for the entire cycle. 1-66 |

. ; WAVEFORMS (Continued) /O PORT RBOR ion \\ / jo ot tp fee te i, ne: Cin pe nas 231735-11 A. input Mode iow ‘we t+ | oureut PORT SS me XK TTT 231735-12 B. Output Mode WAIT STATE (READY = 0) REDDY = ee ee Fee ee eee ~ | 1-67

8755A intel . WAVEFORMS (Continued) ) 8755A PROGRAM MODE romeo au Jf \\ aN wom XK sone X_) () __ ~ KX XT XX “ W__ pnoarty vs ™ = = . oo “ -- = ” ne rr Ory 2a 2s1735-14 “Verify cycle is a regular Memory Read Cycle (with Vpp = +5V for 8755A). . 1-68 |