8228 INTEL | Alldatasheet
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to directly interface MCS-80 family RAM, ROM, and 1/O components. interrupt driven systems to have an unlimited number of interrupt levels. count for cost effective, reliable design of MCS-80 systems. The specifications for the 3228 are identical with those for the 8228. Figure 1. Block Diagram Figure 2. Pin Configuration
8228 intel. ABSOLUTE MAXIMUM RATINGS* “WARNING: Stressing the device beyond the “Absolute D.C. CHARACTERISTICS Ta = 0°C to +70°C, Voc = 5V +5% Pome] ree r| cman a ae perower | All Input InputLoadcurent [ststs | || soo [wa |voc=525v || [beads ||| 750 | pa |v = o4sv ae Ds & Dy [other inputs [|| 250 | pa | Input Leakage Curent|STSTB |_| «| (100 | wA [Voc = 5.25V [a otherinputs [|| 100 | pa | a. a Voltage, All Inputs licc__[Powersuppiy Curent || 140 | 190 [ma|Voo=525v Vo. [Output Low vottage [Do-O, ||| 04s |v [Voc = 4.75Vslon=2ma_| Pee eeamat | tae eae Von [Outputhigh Voltage [D-07 [36] 38 [|v [Vcc = 4.75Vilon = —10,A] ene ee mals te lios_[ShontGirouitGurent,anOupuis [4s { [90 [ma|Voo=sv lorem | Off State Output Current | | fee |etemeeseae™ | | ahr [we _[iracurent TLS [ma [see nta Test Grcuiy | NOTE: 1. Typical values are for Ta = 25°C and nominal supply voltages. 1-56 |
CAPACITANCE Vaiss = 2.5V, Voc = 5.0V, Ta = 25°C, f = 1 MHz 1. This parameter is periodically sampled and not 100% tested. Input Capacitance | | 8 | 12 | pF | Cour Output Capacitance 7 pF Control Signals Ze) 1/0 Capacitance pF (O or DB) A.C. CHARACTERISTICS T, = 0°C to +70°C, Voc = 5V 5% | tew___| Width of Status Strobe [22] [ns | | [tss__| Setup Time, Status inputs Dp-D fe] [nsf | [ts | Hold Time, Status inputs Dor | CT ns | [toc | Delay trom STSTB to any Control Signal | 20 | 60 | ns |G = 10006 | Delay from DBIN to Control Outputs | [30 [ns |, = 1006 | | tae | Delay from DBIN to Enable/Disable 8080 Bus | [45 [ns |G, = 250 | [tap | Delay from System Bus to 8080 Bus during Read [| 30 | ns [= 25pF | [twa | Delay from WR to Controt Outputs [5 [45 | ns | O, = 10008 | | twe | Delay to Enable System Bus DBp-DB7 atterSTsts_ |_| 30_|_ns_| ©, = 100° | Delay from 8080 Bus Dp-D7 to System Bus Cy = 100 pF 0B -0B; during Write Delay trom System Bus Enable to System Bus DBp-D87 |__| 30 | ns_| G = 100pF | HLDA to Read Status Outputs [| [afr [| [tos __| Setup Time, System Bus Inputs to HLDA fof [nsf | Hold Time, System Bus Inputs to HLDA [20] [ns | c= 10008 } A.C. TESTING LOAD CIRCUIT INTA Test Circult (tor RST 7) Yee ® tka # 10% . UNDER Test ‘Tr © ~ para0s-3 ‘wr For Do-D7; Ry = 4 KM, Re = oof, CL = 25 pF. 23 For all other outputs: Ay = 500M, Ro = 1 KM, C, = 100 pF. b 201465-4 | 1-57
intel. WAVEFORMS eo NI NLS LSS ‘STATUS STROBE M 040 ost us K TT) wo fe YA, TOR, WER wot wo m3 wa it SYST aus ouRme eA DX_D eee Ct i ot ae a i ea ‘we [| ten ‘ee TOW on tw
8080 BUS DURING WRITE coseeeecsecccreres
SYSTEM BUS DURING WRITE == mene nnn nnn nme nal K ad J * ‘SYSTEM BUS OUTPUTS Sl alaletatatatalatetetatatatatatetatatatetetatetalS Pea eeeceeeceeeeeeee aste-8 VOLTAGE MEASUREMENT POINTS: Do-D7 (when outputs) Logic “0” = 0.8V, Logic “1"" = 3.0V. All other signais mea- ‘sured at 1.5V. 1-58 |