TP5C032-35

5C032 INTEL | Alldatasheet

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intel. 5C032 8-MACROCELL CMOS PLD @ High-Density, Low-Power Replacement @ Programmable “Security Bit” Allows for SSI & MSI Devices and Bipolar PLDs Total Protection of Proprietary Designs @ Up to 18 Inputs (10 Dedicated & 8 1/0) ® Icc (standby) 100 »A (max) and 8 Outputs Ic¢c (10 MHz) 25 mA (max) @ Eight Macrocells with Programmable @ 100% Generically Tested EPROM Logic 1/0 Architecture Control Array @ tpp = 30 ns (max), 43.5 MHz Pipelined, @ 20-pin 0.3” Ceramic and Plastic DIP

28.5 MHz with Feedback Package

im Low Power Upgrade for All Commonly See oa #240800) Used 20-pin PLDs 100% Compatible with EP320 | CMOS EPROM Technology Based UV” Pat Erasable (CerDIP) ————SSSSSSSSSSSSSSSeSSSSSSsSSSSSSSSSSSSSSsSssssssSsSsssss wy INPUT/cLK 1 201 oc wweut 2 1911/0 input 3 1831/0 input Cy 4 vwEV/o wweur hs 1651/0 iweur 7 4B1/o wets §=¢ 13E/0 werts & 12E1/0 ono CJ 10 11 F/Vpp. 200155-1 Pin Configuration 2-244

INTRODUCTION ARCHITECTURE DESCRIPTION The Intel 5CO32 is an 8-macrocell, 20-pin, general- The architecture of the 5C032 is based on the “Sum purpose PLD (Programmable Logic Device).This de- _of Products” PLA (Programmable Logic Array) struc- vice can be used to replace bipolar programmable —_ture with a programmable AND array feeding into a logic arrays and LS TTL and 74HC (CMOS) SS! and fixed OR array. This device can accommodate both MSI logic devices. The 5C032 can alsobe used asa combinational and sequential logic functions. A pro- direct, low-power replacement for almost all com- Prietary programmable 1/O architecture provides in- mon 20-pin fuse-based programmable logic devices. dividual selection of either combinational or regis- With its flexible programmable I/O architecture, this tered output and feedback signals, all with select- device is a superset of common 20-pin PLDs. able polarity. The 5C032 PLD uses CMOS EPROM {floating gate) The 5C032 contains 10 dedicated inputs as well as 8 cells as logic control elements instead of fuses. The input/output pins. These |/O pins can be individually CMOS EPROM technology reduces power con- _configured to be inputs, outputs or bi-directional I/O ‘sumption of PLDs to less than 20% of a comparable pins. Each of these I/O pins is connected to a mac- bipolar device without sacrificing speed perform- _rocell. The 5C032 contains 8 identical macrocells or- ance. In addition, the use of Intel's advanced CMOS ganized as shown in Figure 1. 2 \\-E EPROM process technology enables greater logic densities to be achieved with superior speed Each macrocell (see Figure 2) consists of a PLA and low-power performance over other comparable (programmabie logic array) block and an I/O archi- devices. Intel's 5C032 has the benefit of “zero” tecture block, which contains a “D” type register. stand-by power not available on other programma- The PLA block consists of eight 36-input AND gates ble logic devices. EPROM technology allows these (TRUE & COMPLEMENT of 10 dedicated inputs devices to be 100% factory tested by programming plus the 8 feedback inputs from the eight macro- and erasing all the EPROM logic control elements. _ceils), feeding into an OR gate. The output of this PLA block is fed into the I/O architecture block. The The 5C032 with its superior speed and power per- different I/O and feedback options that are available formance and its plastic package is an ideal produc- in the 5C032 1/O block are shown in Figure 3. tion vehicle for high-volume manufacturing. Most commonly used 20-pin bipolar PLDs can be easily replaced with this device allowing for tremendous power consumption savings without sacrificing speed of operation. | 2-245

7 CONTROL 4, [I]

3 CONTROL , [J

4 PLA BLOCK | yo R

Figure 1. 5C032 Architecture

Figure 2. Logic Array Macrocell

Figure 3. 5C032 I/O Architecture Control

20 PIN CMOS COMPATIBILITY

20 pin PLD configurations by utilizing the individual logic and output controls of each macrocell. List of PAL devices logically compatible with the 5C032. *PAL is a registered trademark of Advanced Micro Devices.

intel ° 5C032 Erased-State Configuration This method greatly decreases the overall program- ming time while programming reliability is ensured as Prior to programming or after erasing, the I/O struc- the incremental program margin of each bit is con- ture is configured for combinatorial active low output _tinually monitored to determine when the bit has with input (pin) feedback. been successfully programmed. ERASURE CHARACTERISTICS FUNCTIONAL TESTING Erasure characteristics of the 5C032 are such that Since the logical operation of the 5C032 is con- erasure begins to occur upon exposure to light with _trolled by EPROM elements, the device is complete- wavelengths shorter than approximately 4000A. It __ly testable. Each programmable EPROM bit control- should be noted that sunlight and certain types of ing the internal logic is tested using application-in- flourescent lamps have wavelengths in the 3000- dependent test program patterns. After testing, the 4000A. Data shows that constant exposure to room devices are erased before shipment to customers. level flourescent lighting could erase the typical —_No post-programming tests of the EPROM array are 5C032 in approximately three years, while it would required. take approximately one week to cause erasure when exposed to direct sunlight. If the 5C032 is to be ex- The testability and reliability of EPROM.based pro- [WP4 Posed to these types of lighting conditions for ex- _grammable logic devices is an important feature tended periods of time, conductive opaque iabels over similar devices based on fuse technology. should be placed over the device window to prevent Fuse-based programmable logic devices require a unintentional erasure. user to perform post-programming tests to insure Proper programming. These tests must be done at The recommended erasure procedure for the 5CO32__—the device level because of the cummulative error is exposure to shortwave ultraviolet light with a effect. For example, a board containing ten devices wavelength of 2537A. The integrated dose (.e., UV _ each possessing a 2% device fallout translates into intensity x exposure time) for erasure should be a _an 18% fallout at the board level (it should be noted minimum of fifteen (15) Wsec/cm?. The erasure that programming fallout of fuse-based programma- time with this dosage is approximately 15 to 20 min- _ble logic devices is typically 2% or higher). utes using an ultraviolet lamp with a 12,000 W/cm? Power rating. The 5C032 should be placed within ‘one inch of the lamp tubes during erasure. The maxi- DESIGN RECOMMENDATIONS mum integrated dose the 5C032 can be exposed to without damage is 7258 Wsec/cm?2 (1 week at For proper operation, it is recommended that all in- 12,000 4W/cm2). Exposure to high intensity UV light put and output pins be constrained to the voltage for longer periods may cause permanent damage to range GND < (Vin or Vout) < Voc. Unused inputs the device. should be tied to an appropriate logic level (0.9. ei- ther Voc or GND) to minimize device power con- ‘sumption. Reserved pins (as indicated in the iPLDS PROGRAMMING CHARACTERISTICS REPORT file) should be lett floating (no connect) so m that the pin can attain the appropriate logic level. A Initially, and after erasure, all the EPROM contro! power supply decoupling capacitor of at least 0.2 pF bits of the 5C032 are connected (in the “1” state). must be connected directly between Voc and GND Each of the connected control bits are selectively ping of the device. disconnected by programming the EPROM cells into their “0” state. Programming voltage and waveform —_ As with all CMOS devices, ESD handling procedures specifications are available by request from Intel to. should be used with the 5C032 to prevent damage support programming of the device. to the device during programming, assembly, and test. Intelligent Programming Algorithm The 5C032 supports the Intelligent Programming Al. DESIGN SECURITY gorithm which rapidly programs Intel H-ELPDs (and 4 single EPROM bit provides a programmable de- EPROMs) using an efficient and reliable method. sian security feature that controls the access to the The Intelligent Programming Algorithm is particularly gata programmed into the device. If this bit is set, a suited to the production programming environment. Fropretary design within the device cannot be cop- ied. This EPROM security bit enables a higher de- gree of design security than fused-based devices since programmed data within EPROM cells is invisi- | 2-249

The 5C032 is also supported by third-party compil- ers such as ABEL*, CUPL", PLOesigner", Log/ic, ORDERING INFORMATION etc. Programming support is provided by third-party Order Operating Programmer companies such as Data 1/0, Logical Code Range Devices, STAG, etc. Please refer to the “Third-Party [5c032-30 | 5, Support” lists in the Programmable Logic handbook 7 D5C032-30 |CERDIP | Commercial for complete information and vendor contacts. P5C032-30 | PDIP D5C032-35 | CERDIP [pscnse2s | poi CeROIP POIP [3s [20] 40 [rescos2as[eor [industria | *ABEL is a trademark of Data I/O, Corp. CUPL is a trademark of Logical Devices, Inc. PLDesigner is a trademark of MINC, Inc. Log/IC is a trademark of ISDATA, Incorporated. | 2-251

scone intel. ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- [symbor[ Parameter [win [wax [une] Serene Se ie orange we no *WARNING: Stressing the device beyond the “Absolute [voc [Supp voraget” __|-20| 70 | v | Maximum Ratings” may cause permanent damage. , These are stress ratings only. Operation beyond the Supply Voltage tended exposure beyond the “Operating Conditions” DC npurvoragett¥@ |-0.5|Voc+os| v | may afect device retbity [tte [Storage Tomporanxe | -e5 | +150 | °c | [tone [ambient Tomperatwets] ro] +05 | °c | NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is —0.5V. During transitions, the in- puts may undershoot to —2.0V or overshoot to +7.0V for Periods less than 20 ns under no load conditions. 3. Under bias, Extended temperature versions are also available. 4, Extended temperature versions also available. RECOMMENDED OPERATING CONDITIONS Supply Vottage | 47 [sas Input Voltage poo foo [| Yo | Outputvotage | Too P| Operating Temperature | oS] to || Input Rise Time ee ee 2-252 |

D.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5V +5% [_symboi_['_Parameter/Test Gonaitions | min [ Typ | Max |. Unit | High Level Input Voltage | 20 | | vocroa | v | Low Level input Voltage | -o3 [| oe Tv Vou®) High Level Output Voltage v Ip = —4.0MADC., Voc = min. Vou Low Level Output Voltage v lo = 4.0 mA DC., Voc = min. Input Leakage Current +10 BA Voc = max., GND < Vin < Voc Output Leakage Current +10 BA Voc = max., GND < Vout < Voc Igcl7) Output Short Circuit Current 2 Voc = max., Vout = 0.5V Standby Current 100 BA Voc = max., Vin = Voc or GND, Standby Mode loc) Power Supply Current mA Voc = max., Vin = Voc or GND, No Load, Input Freq. = 10 MHz Active Mode (Turbo = Ott), Device Prog. as 8-bit Ctr. NOTES: 5. Absolute values with respect to device GNO; all over- and undershoots due to system or tester noise are included. 6. Ip at CMOS levels (3.84V) = —2 mA. 7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. 8. With Turbo Bit = Off, device automatically enters standby mode approximately 100 ns after last input transition. 8. Maximum Active Current at operational frequency is less than 40 mA. A.C. TESTING LOAD CIRCUIT A.C, TESTING INPUT, OUTPUT WAVEFORM Sv 30 28 on 8550 0. DEVICE TO TEST 3410, Cy (INCLUDES JIG 290155-7 CAPACITANCE) AC. Testing: Inputs are Driven at 3.0V for a Logic “1” and OV for 8 Logic “0”. Timing Measurements are made at 2.0V for a Logic = “1” and 0.8V for a Logic “0” on inputs. Outputs are measured at 200185-6 4 1.5V point. Device input risa and fail imes < 6 ns. C, = 60 pF | 2-253

5C032 intel ° CAPACITANCE |__| tmputCapacitance | Vin=ov.t=10mHz | | | to | oF _| | Cour | OutputCapacitance | Vour=ov.i=1omHz | | | to | pF _| | Cox | Glock PinCapacitance | viw=ov.t=tomHz | | | 10 | oF | L_Cvee | Veerin | intt.t=tomnz [| | 20 | or A.C. CHARACTERISTICS T, = 0°C to +70°C, Voc = 5V +5%, Turbo Bit On(10) ole ee Symbol Turbo | min | Typ | Max | min | Typ | Max | min | Typ | Max] Mode [0 __[torvo] comb. ouput | | | so | | fas ||| ao | +15 [ns | lias [orv0[Ouputenavio| | [oo] | fas} | | «o] +15 | re [texet"9 [rorvo]outpurnisabie| | | sof | [ss] [| ao | +18 | as | NOTES: 10. Typ. values are at Ta = 25°C, Voc = 5V, Active Mode. o rage tpxz are measured at +0.5V from steady state voltage as driven by spec. output load. tpxz is measured with A.C. CHARACTERISTICS T, = 0°C to 70°C, Voc = 5V +5%, Turbo Bit On (10) SYNCHRONOUS CLOCK MODE ~_ — ee | win] Typ] Max] min] Typ] Max| min |Typ| Max] Mode few [iraretorosmese™ | |) | [ey | fey ee 1/tgy — No Feedback for [insenvmmmntroemec! | (| | |) | [P| [ee 1/tent — with Internal Feedback lisu__[ImputSetupTimetocix fas} | fas} | [sof [| +15 | ns | lta [lorvoHoidattercixvin | o | | fol {| fof { [| ns| ltco_[cuxHightoouputvaid ||| a7] | feof | fest ns | eee TT CT Register Input — Internal Path lion [ouxwigntime ts fret Ts ns | [tax [ouxtowtime ETT fet Ts] PT ns J 2-254 |

COMBINATORIAL OUTPUT | | tone COMBINATORIAL OR r HIGH IMPEDANCE REGISTERED OUTPUT ‘3= STATE 2 Le tenx HIGH IMPEDANCE a 220165-8 SYNCHRONOUS CLOCK MODE ton ta ‘CLKI tsu ty a Co —— Lp (FROM REGISTER Rou Reis VaLIo OUTPUT (290155-9° | 2-255,

sense intel. Current in Relation to Frequency Current in Relation to Temperature oL Ly “Ll || He ° aa =~ aa AT a | => = § l(t | § B x B x» ST mers 0 o © 5 10 15 20 25 30 35 40 o 20 40 60 80 85 fowr(MHz) Temp(©) 200185-11 20018s-12 Conditions: T, = 0°C, Voc = 5.28V Conditions: Voc = 5.25V Output Drive Current in Relation to Voltage C—O SS ft 8 Si z= [Z| Ne

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a = ed a a a | Ltt Tt ° 1 2 3 4 s Vo Output Vettoge ”) 200155-13 Conditions: Ty = +25°C, Voc = 5V tpp Derating vs Capacitive Loading 12n8 Low=to-High 10ns High=to-Low @ Bans 2 6ns a EB Ans 2ne ons Conditions: Ae sec SOPF 90 pF 130 pF 170 pF Veo = 5.0 nce e ¥ Copactia (290155-15 2-256 |