82288

M82288 INTEL | Alldatasheet

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@ Offers Wide Flexibility in System to. Figure 1. M82288 Block Diagram Figure 2. M82288 Pin Diagram MULTIBUS® | is a registered trademark of Intel Corporation.

Table. 1. Pin Description The following pin function descriptions are for the M82288 bus controller. CLK ‘SYSTEM CLOCK provides the basic timing control for the M82288 in an M80286 microsystem. Its frequency is twice the internal processor clock frequency. The falling edge of this input signal establishes when inputs are sampled and command and control outputs change. 50, 51 BUS CYCLE STATUS starts a bus cycle, and along with M/IO, defines the type of bus ele. ‘These inputs are active LOW. A bus cycle is started when either S1 or SO is sampled LOW at the falling edge of CLK. These inputs have pullups sufficient to hold them HIGH when nothing drives them. Setup and hold times must be met for proper operation.

80286 Bus Cycle Status Definition

Mio [ si | 5 | Type of Bus Cycle 0 0 0 Interrupt Acknowledge 0 0 1 W/O Read 0 1 ° 1/0 Write 0 1 1 None; Idle 1 0 0 Halt or Shutdown 1 0 1 Memory Read 1 1 0 Memory Write 1 1 1 None; Idle M/iO MEMORY or I/O SELECT determines whether the current bus cycle is in the memory space or I/O space. When LOW, the current bus cycle is in the I/O space. Setup and hold times must be met for proper operation. MULTIBUS | MODE SELECT determines timing of the command and control ‘outputs. When HIGH, the bus controller operates in MULTIBUS | mode. When LOW, the bus controller optimizes the command and control output timing for short bus cycles. The function of the CEN/AEN input pin is selected by this signal. This input is intended to be a strapping option and not dynamically changed. This input may be connected to Vcc or GND. CENL COMMAND ENABLE LATCHED is a bus controller select signal which enables the bus controller to respond to the current bus cycle being initiated. CENL is an active HIGH input latched internally at the start of each bus cycle. CENL is used to select the appropriate bus controller for each bus cycle ina system where the CPU has more than one bus it can use. This input may be connected to Vc to select this M82288 for all transfers. No control inputs affect CENL. Setup and hold times must be met for proper operation. CMDLY COMMAND DELAY allows delaying the start of a command. CMDLY is an active HIGH input. If sampled HIGH, the command output is not activated and CMDLY is again sampled at the next CLK cycle. When sampled LOW the selected command is enabled. If READY is detected LOW before the command output is activated, the M82268 will terminate the bus cycle, even if ‘no command was issued. Setup and hold times must be satisfied for proper operation. This input may be connected to GND if no delays are required before starting a command. This input has no effect on M82288 control outputs. READY READY indicates the end of the current bus cycle. READY is an active LOW input. MULTIBUS I mode requires at least one wait state to allow the command outputs to become active. READY must be LOW during reset, to force the M8288 into the idle state. Setup and hold times must be met for proper operation. The M82C284 drives LOW during RESET. 20-181

Table 1. Pin Description (Continued) outputs of the bus controller. CEN/AEN inputs may be asynchronous to CLK. synchronous inputs. This input inay, be connected to Voc or GND. inactive but does not tristate them. address on the falling edge of ALE. for write cycles in the MULTIBUS | mode. active. DT/R is not affected by any of the control inputs. when this output becomes active. READY controls when it becomes inactive. when this output becomes active. READY controls when it becomes inactive. [Vcc | ——_—*| SYSTEM POWER: +5V power supply. [GND «|__| SYSTEM GROUND: 0 volts.

address/data setup and hold time requirements. clock phase when it asserts the status signals. via a CMDLY input to determine the start of acom- —_ local bus master's internal clock. the pipelined timing on the M80286 local bus. sor clock phases. such as the M82289. in the T; state. DEN timing allows sufficient time for tristate bus driv. The S1 and SO inputs signal the start of a bus cycle. Figure 3. CLK Relationship to the Processor Clock and Bus T-States

state is repeated. This is called inserting a wait state. Figure 5. Bus Cycle Definition Table 2. Command and Control Outputs for Each Type of Bus Cycle

0 Wit [0 [+ [| tows [wich [ves [no _|

‘on address to command active and write data to mand output is activated. ing interrupt acknowledge cycles. Figure 7. Idle-Write-Idle Bus Cycles with MB = 0

Figure 10. Idle-Write-Idle Bus Cycles with MB = 1 fore any write command output becomes active. data drivers reach 3-state OFF. Three signal transitions are delayed by MB = 1 as MCE. 2) The HIGH to LOW transition of the write com- not affected by any control input.

98 Tne la dolaved ore CLR cyclo, TN TMS CY” cycle longer than ALE to hold the cascade address

DEN always becomes inactive between bus cycles °C!e. MCE is not affected by any control input.

: intel ms2288 than one bus which may be used to perform a bus during any T-state. AEN LOW immediately allows cycle. Normally, a CPU will only have one bus con- _DEN to go to the appropriate state. Three CLK edg- troller active for each bus cycle. Some buses may be es later, the command outputs will go active (see shared by more than one CPU (i.e. MULTIBUS |) timing waveforms). The MULTIBUS | requires this requiring only one of them use of the bus at a time. delay for the address and data to be valid on the bus before the commands become active. Systems with multiple and shared buses use two __ control put sionals of the M82288 bus controller, When MB = 0, CEN/AEN becomes CEN. CEN is an CENL and AEN (see Figure 12). CENL enables the asynchronous input which immediately affects the bus controller to control the current bus cycle. The command and DEN outputs. When CEN makes a AEN input prevents _a bus controller from driving its HIGH to LOW transition, the commands and DEN command outputs. AEN HIGH means that another are immediately forced inactive. When CEN makes a bus controller may be driving the shared bus. LOW to HIGH transition, the commands and DEN outputs immediately go to the appropriate state (see In Figure 12, two buses are shown: a local bus and a timing waveforms). READY must still become active MULTIBUS |. Only one bus is used for each CPU to terminate a bus cycle if CEN remains LOW for a bus cycle. The CENL inputs of the bus controllers selected bus controller (CENL was latched HIGH). select which bus controller is to perform the bus cy? cle. An address decoder determines which bus to Some memory or 1/O systems may require more ad- use for each bus cycle. The M82288 connected to dress or write data setup time to command active the shared MULTIBUS | must be selected by CENL. than provided by the basic command output timing. and be given access to the MULTIBUS | by AEN. To provide flexible command timing, the CMDLY in- before it will begin a MULTIBUS | operation. put can delay the activation of command outputs. The CMDLY input must be sampled LOW to activate CENL must be sampled HIGH at the end of the Ts the command outputs. CMDLY does not affect the bus state (see waveforms) to enable the bus control- control outputs ALE, MCE, DEN and DT/R. ler to activate its command and control outputs. If sampled LOW the commands and DEN will not go CMDLY is first sampled on the falling edge of the active and DT/R will remain HIGH. The bus control- CLK ending Ts. If sampled HIGH, the command out- ler will ignore the CMDLY, CEN and READY inputs _put is not activated, and CMDLY is again sampled until another bus cycle is started via S1 and SO. ‘on the next falling edge of CLK. Once sampled Since an address decoder is commonly used to LOW, the proper command output becomes active identify which bus is required for each bus cycle, immediately if MB = 0. If MB = 1, the proper com- CENL is latched to avoid the need for latching its mand goes active no earlier than shown in Figures 9 input. and 10. The CENL input can affect the DEN control output. READY can terminate a bus cycle before CMDLY When MB = 0, DEN normally becomes active dur- allows a command to be issued. In this case no ing Phase 2 of Ts in write bus cycles. This transition commands are issued and the bus controller will de- occurs before CENL is sampled. If CENL is sampled activate DEN and DT/R in the same manner as if a LOW, the DEN output will be forced LOW during Tc. command had been issued. as shown in the timing waveforms. When MB = 1, CEN/AEN becomes AEN. AEN con. | Waveforms Discussion trols when the bus controller command outputs en- ter and exit 3-state OFF. AEN is intended to be driv- The waveforms show the timing relationships of in- ‘en by a bus arbiter, like the MB2289, which assures _ puts and outputs and do not show all possible tran- ‘only one bus controller is driving the shared bus at sitions of all signals in all modes. Instead, all signal any time. When AEN makes a LOW to HIGH tran- timing relationships are shown via the general cas- sition, the command outputs immediately enter es. Special cases are shown when needed. The 3-state OFF and DEN is forced inactive. An inactive | waveforms provide some functional descriptions of DEN should force the local data transceivers con- the M82288; however, most functional descriptions nected to the shared data bus into 3-state OFF (see —_are provided in Figures 5 through 11. Figure 12). The LOW to HIGH transition of AEN should only occur during T; or Ts bus states. To find the timing specification for a signal transition in a particular mode, first look for a special case in The HIGH to LOW transition of AEN signals that the the waveforms. If no special case applies, then use bus controller may now drive the shared bus com- a timing specification for the same or related func- mand signals. Since a bus cycle may be active or be tion in another mode. in the process of starting, AEN can become active 20-188

Figure 12. System Use of AEN and CENL

Jute Maximum Ratings” may cause permanent dam- Case Temperature Under Bias...—55°C to +125°C age to the device. This is a stress rating only and Voltage on Any Pin with other conditions above those indicated in the opera: ° posure to absolute maximum rating conditions for Operating Conditions [_Symbot [ Description | Min Max [Units Case Temperature (instanton) | = 58 | #125 | Digital Supply Voltage [475 | sas TY D.C. CHARACTERISTICS (Over Specified Operating Conditions) [| Vu | input LowVottage | -05 | os PvP | Vin___| input HIGH Voltage | 20 | Voctos | vf CLK input LOW Voltage [ -o5 | o6 [ v foo | CLK input HIGH Voltage [38 | vocros [ vo fo Vou ‘Output LOW Voltage ‘Command Outputs 0.45 v lo, = 32 mA (Note 1) Control Outputs: 0.45 v lou. = 16 mA (Note 2) Vou Output HIGH Voltage Command Outputs v lou = —5 mA (Note 1) Control Outputs Vv lou = —1 mA (Note 2) [ie | input Current 6G andStinputsy | [08 | ma | i= 045 | tit Input Leakage Current #10 BA OV < Vin < Veo {all other inputs) [ to | Output Leakage Curent [| #10 Twa | 0.45V < ViouT < Vou [tcc | PowerSupply Curent [tao ma PO CLK Input Capacitance re ee ec | input Capacitance a ee Input/Output Capacitance ee NOTES: 4. Command Outputs are INTA, ORC, TOWC, MDC, MWRC. 2. Control Outputs are DT/R, DEN, ALE and MCE. A.C. CHARACTERISTICS (Over Specified Operating Conditions) ‘AC timings are referenced to 0.8V and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. [1 | cikPerod [ea [250 | 62 | 260 | so | 260 | ns | | [2 | cikHicHTime [25 [230 | 20 | 205 | 16 | 298 | ns | atsev | [3 | crxtowTime [20 [ 26 | 15 [ 290 | 12 [ 204 | ns | atiov | 20-190

A.C. CHARACTERISTICS (Over Specified Operating Conditions) (Continued) me] oe a a aaa om [4 [cikRisotime | S| to] | to | Te | ns | t.0vt0sev | [5 [ctkraitme | S| to] | to | Te | ns | 36vt01.0v| [6 | M/OandStatusSewpTime | 28 | | 22 | | we || ns | [7 [mAGandstausHoidtime | 1 | ft | tt TT ns TO [e_[centseuptime | go || co] Ps ff ms [| [9 [CENLHodTime | at | Tt] UT th [Uf ns [| [10 | READYSetuptimo | SO] | co | | oe || ns [| [11 | READYHoidTime | 85 | fs | os || ns | [12 [cmotysetuptime | 25 | | ao] fs | ns | [13 | omptyHoidtime Tt Tt Tt TT ns TO [14 | AENSetupTime | 5 | To | as || ns | (Notes) | [1s | AENHoTime | | To To | ns [inotes) | [16 [ ALE, MCE ActiveDelaytromcik | 3 | 25 [ 3 | 20 | 3 | 16 | ns | (Notes) | [17 | ALE, MCE Inactive Delayfromcuk || 3s | | 25 || 19 | ns | (Notes) | [18 | DEN (Write) Inactive fromcenc || 35 | | 35 | | 23 | ns | (Notes) | [19 [or/ALowtemcik || ao || as | a3 | ns | (Notes) [20 | DEN (Read) ActivetromoT/A_ | 5 | 50 | 5 | 35 | 5 | 21 | ns | (Notes) | [21 | DEN (Read) Inactive Dlyfromouk | 5 | 40 | 5 | 35 [5 | 21 | ns | (Notes | [22 | DI/RHIGHfromDEN Inactive | 3 | 45 [ 3 | 35 [ 3 [ 20 | ns | (Notes | [23 [ DEN (Write) Active Delaytromeuk [| 35 [| 30 | | 23 | ns | Notes) | [24 [ DEN (Write) inactive Diy tromouk [3 | as [3 [ 30 | 3 | to | ns | (Notes) | [25 | DENInactvefromcen | | ao || 30 || 25 | ns | (Notes) | [26 | DENActvefromceN | | 5 | | co | | ae | ns | (Notoa) | Pee et re (when CEN = LOW) [28 | DENActivetromAEN | =| 5 | | 30 | | 26 | ns | (Noted) | [20 | CMDActiveDelaytromcuk | 3 | 40 [ 3 | 26 | 3 | 21 | ns | (Notes) | [30 CMDinactiveDelaytromcuk | 5 | 30 | 5 | 25 | 5 | 20 | ns [ (Notes) | [31 | CMDinactivetromcen || a5 | | a5 || 25 | ns | (Notes) | [32 | CMDActivetromceN | | a5 | | 25 | | 25 | ns | (Notes) | [33 | CMDinactiveEnabletromAEN | [| 40 | | 40 | | 40 | ns | (Notes) | [34 | CNDFloatDelaytromAEN | | 40 | | ao | | 40 | ns | (Notes) | [a5 | MBSeuptime | 25 | | ao] | ao | ns | [36 [MBHoldTime | Tf | CT oT ls TO

37 Command Inactive Enable

[" [remusgemremr Tf et fet felts [ees | [38 [Command FioatTimetrommad | | 40 | | 40 [| 40 | ns | Wotes) | [se | DENinactvetrommat | | 40 || a0 || 26 | ns | (Notes) | [40 [DEN ActivetrommBd || a5 | | a0 | [30 | ns [Wot | SER is ‘an asynchronous input. This specification is for testing purposes only, to assure recognition at a specific CLK Beret output load: Cl = 150 pF. 5. Command output load: Cl = 300 pF. 6. Float condition occurs when output current is less than Io in magnitude. 20-191

NOTE 8: AC Drive and Measurement Points—CLK Input av 36v 36v ux input tov 10 cusy \\ ‘setup: toto. aN TRY EOP WPT PRR eaentan cos LR ARS wasy LK TREK ARS toe pee SSR RE 0 DEVICE <o xe ‘J oureur eee SES SS ow APOE T ROY TPN zri0si-14 NOTE 9: AC Setup, Hold and Delay Time Measurement—General DEVICE OUTPUT | L : a 271031-15 NOTE 10: AC Test Loading on Outputs 20-192

© © © TA FeAl STATUS, ALE, MCE, CHARACTERISTICS ) Kk ne FY o o CENL, CMDLY, DEN CHARACTERISTICS WITH MB = 0 AND CEN = 1 DURING WRITE CYCLE , a8 Ole) one LLL ANY 271031-18 20-193

WAVEFORMS (Continued) READ CYCLE CHARACTERISTICS WITH MB = 0 AND CEN = 1 Feats K:) @) er | WRITE CYCLE CHARACTERISTICS WITH MB = 0 AND CEN = 1 tO AAS 1@)s 20-194

WAVEFORMS (Continued) CEN CHARACTERISTICS WITH MB = 0 _ +, _ o) awe Ky - ‘OTR, o oo LOM IIT ; AEN CHARACTERISTICS WITH MB = 1 © | LO+40 wen ‘asynchronous input. AEN setup and hold time is specified to guarantee the response shown in the waveforms. 20-195