82284 INTEL | Alldatasheet
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Clock Driver and Ready Interface for iAPX 286 Processors PRELIMINARY
5 DISTINCTIVE CHARACTERISTICS
© Generates system clock for iAPX 286 processors © Generates system reset output from Schmitt Trigger © Uses crystal or TTL signal for frequency source: input © provides locel READY and MULTIBUS" HEADY © te-pin packayo synchronization © Single +5 V power supply GENERAL DESCRIPTION “The 62284 is a clock generator/driver which provides clock _from either asynchronous or synchronous sources. It also signals for (APX 286 processors and support components. generates a synchronous reset signal from an asynchro- The device contains logic to supply READY to the CPU —_—nous input with hysteresis. BLOCK DIAGRAM [p=] | FES si eset . ‘SYNCHRONZER: % | * Ea pi | ~ “ FE - oe ical | toe [| —_ dD L= READY 7 — | . i Q GENERATOR: ee 180007270 meee 3.260 teu Date: May 1987
= Re ek apy (J 1® 1815 Yoo. oie 2 ¥ SRDY [J 2 17 [—] ARDYEN ae SADYEN [[]3 16 [J SROVEN [| 4 e wl READY (C4 3% READY Cs 7h eri C]s 1415 ne Fé C6 13 [5 Poi FIT] 16[] NC x, 7 12 [5 reset re, 15[_] Pouk x, Je 117 FES x;Oe 14 [7] RESET 9 10 11 12 13 eno 9 10 [7 cuk a 0010750 x2 2368 0010760 Note: Pin 1 is marked for orientation. LOGIC SYMBOL E ARDY SRDY SRDYEN uk EFI - RESET FIC PCLK
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2h of 50,51 KROVEN L$003040 3.261
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8 ORDERING INFORMATION
AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by acombination of: a. Temperature Range b, Package Type cc. Device Number d. Speed Option @. Optional Processing L ©. OPTIONAL PROCESSING Slai= Standere processing ~eumn d. SPEED OPTION Blank 8 Mire fo = 10 Me ¢. DEVICE NUMBER/DESCRIPTION pease Clock Driver and Ready Intertace Yor IAP 256 Processors b. PACKAGE TYPE P= 18-Pin Plastic DIP (PD 018) ‘D= 18-Pin Ceramic DIP (CD 018) Na20eI Paste Leaded Chip Carer . TEMPERATURE RANGE Blank = Commercial (0 to + 70°C) Valid Combinations Valid Combinations [szesC Valid Combinations list configurations planned to be [ezzenio Cid ‘supported in volume for this device. Consult the local AMD. [eas sales office to confirm availability of specific valid [no EBB —] Sando eh rn nasa conaion [“Gnpackaged Oe | amaazeaxc a prods nna Gata on AMD's standard mitany 9-262
KRDY_ Kaynchronous Ready (Input; Active LOW) ‘explained later in tho READY generator section. READY is | > ARDY is an active-LOW input used to terminate the current ‘an open collector output requiring an external 910 ohm pull- bus cycle. The ARDY input is qualified by ARDYEN. inputs up resistor. to ARDY may be applied asynchronously to CLK. Setup and RES least Tn (Input; Active LOW) hold times are given to assure a guaranteed response to FIES is an active-LOW input which generates the system synchronous inputs. reset ‘signal RESET. Signals to FES may be. applied KRDYEN Asynchronous Ready Enable (Input; Active asynchronously to CLK. A Schmitt Trigger input is provided Low) on RES, so that an RC circuit can be used to provide a time FARDYEN is an active-LOW input which qualifies the ARDY delay. Setup and hold times are given to assure a input. ARDYEN selects ARDY as the source of READY for guaranteed response to synchronous inputs. the current bus cyclo. Inputs to ARDYEN may be appliod —peseT Reset (Output; Active HIGH) synchronously to CLK. Setup and hold times are given to RESET is an active-HIGH output which is derived from the assure @ guaranteed response to synchronous inputs. RES input. RESET is used to force the system into an initial CLK System Clock (Output) state. When RESET is active, READY will be active (LOW). CLK output is used by the processor and any support 50, 57 Status (Input) devices which must be synchronized with the processor. “Those inputs prepare the 82284 for a subsequent bus cycle. The frequency of the CLK output is twice the processor's ‘50 and 51 synchronize PCLK to the ioral processor clock internal clock frequency. CLK can drive both TTL and MOS and control READY. These inputs have pullup resistors to level inputs. keep them HIGH if nothing is driving them. Setup and hold EF External Frequency In Gree times must be satisfied for proper operation. ‘The EF! input drives CLK when F/C is strapped HIGH. The SABY Synchronous Ready (Input; Active L EF! inpaa frequency must be twice the processor's interne! ADV is an active LOW input ted 1 trminto the curent clock frequency. bus cycle, The SRDY input is qualified by the SRDYEN F/E _ Frequency/Crystal Select (Input) input. Setup and hold times must be satisfied for proper F/T is a strapping option used to select the source for the operation. ‘CLK output. When F/T is strapped LOW, the internal crystal SROVEN ‘Synchronous Ready Enable drives CLK, When F/T is strapped HIGH, the EFI input tow © (input: Active Orives the CLK output. ‘SADYEN is an active-LOW input which qualifies SFDY. GND System Ground: 0 V SRDYEN selects SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold times must be PCLK Peripheral Clock (Output) i PCLK is an output which provides a 50% duty cycle clock Satisfied for proper operation. with one half the frequency of CLK. PCLK will be in phase Vc +5-V Power Supply (Input) with the processor's internal clock following the fist bus 1 x» Crystal in (Input) cycle after the processor has been reset. ‘These are the pins to which a parallel resonant fundamental READY Ready (Output; Active LOW) mode crystal is attached for the internal oscillator. When READY is an active-LOW output which signals the cunt F/is strapped LOW, the oscillator will drive the CLK output bus cycle is to be completed. The SADY, |, ARDY, at the crystal frequency. The crystal frequency must be ARDYEN, S1, 50 and RES inputs control READY as twice the processor's internal clock frequency. 3.263
required for iAPX 286 processors and support components. both SO and ST are HIGH. clock generator, MULTIBUS-ready synchronization logic and Change except during the first bus cycle after reset. 286 system. CLK has output characteristics sufficient to drive Thode crystal. The output of the ecilator Internally buttered. strapping option. When F/T is LOW, the crystal oscillator foad capacitance of 32 PF. drives the CLK output. When F/T is HIGH, the EFI input drives . After reset, the PCLK signal may be out of phase with the capacitance) to less than 10 pF betwoen the X; and X2 pins. cycle are used to synchronize PCLK to the internal processor as possible. Figure 1. Recommended Crystal and READY Connections TABLE 1. 82284 CRYSTAL LOADING CAPACITANCE VALUES ‘Note: Capacitance values must include stray board capacitance.
single transition of RESET with an RC circuit on RES. The Figure 3 illustrates the operation of SRDY and SADYEN. level at which the circuit output switches from LOW to HIGH. active when both SRDY and SROYEN are sampled as LOW. ARDYEN) for selecting the type of ready source required to ‘or the ready inputs are sampled as inactive. Figure 2. Typical RC RES Timing Circuit
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES 8 Power Dissipation ....scciucssssssssssecsssseiisssneet W Operating ranges define those limits between which the Stresses above those listed under ABSOLUTE Maximum — “Unetlonallty of the device is guaranteed, RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device rebability. DC CHARACTERISTICS over operating range unless otherwise specified Parameter Parameter vaenaics [om [on om ie LOW Vase ee rT SS [oi pH aro POTS oO [vou | HERBY oof berber Derm we [vou [ok cupathowotage [orem ws Pv [Voie ct onpa a vouge toa a [oc Power Suny Goro | CAPACITANCE (Ta = +25°C, Voc = GND = 0 V, Vin= +5 V or GND) Parameter Parameter Tat comatose | ne | vt | Input Capacitance (Note 1) [ic=twie TT to | Notes: 1. This specification is provided for reference only. Seo Sacton 6 for Thermal Grarairiatcs Infomation 3-267
@ | SWITCHING CHARACTERISTICS over operating range unless otherwise specified parameter [_emn: | towne | ee ee eee SSE [a0 ine Ves eS A ESO A [os [ax tow tee ve ge a CA ENA sk [Tei Rie Tine vig Re [sax Far tine sg Rae ee eo [oats Setup Tene et SP [10 [an Ho fener Rc a [3 [ROY or ROVER Wy tthe [oes tayo | [RF or ROVER Bis Tmo eet GE A [7H racve Dowy vee sf 8 [ie REROY Awe Day id Ve me A a [carro cow time i os see e [2 ti tine TF oes Sune [uo os Notes: 1. CLK loading: C. = 150 pF. 1 Ei ete ee ua ving commended et! and capctive lag, of wih the EF input neatng specctons tp A ee a ee I a cera cea Ssng or LK wocosones ENG Nets we 35 Fee ee en ee ee ene a et aay atte, Be Te oe Oar anbex os wolane Se ce Ne oe ct scan Seen et tstng puposes only 0 ase rcogiton at specie CLK o4ge 4, READY loading: i, = 7 mA, C= 150 pF. In system application, use 910 ohm *5% pull-up resistor to meet 80286 timing requirements. For systems which operate faster than 10 MHz, care should be taken to minimize capacitive ioading on READY. The user must ensure Fe ES ee ee ees nat ate dene open 5. PCLK and RESET loading: CL = 75 pF. PCLK also has 750 ohm pull-up resistor. Se ee anne ak poe 7. When driving the 82284 with EFI, provide minimum EFI HIGH and LOW times as follows: [eax uipat Freaseney [toms ox aosmie GL] [iin Reaired EFTHIGH Tine [90s [25 ne | [Twin Reaured EFT LOW Time [25 m5 | ne | “A CLK temuaeien above 16 MHz, CLK ouput HIGH and LOW Fe ee at ek ott tt enone wees peetond cy whan ug na ora Seen aaee re ae, anh wren cng compost rom, crystal is used to drive the 62284, * €. ho usg a ey! (th recommended letrg eamctance pet Tat 1) eprops fr he apse off ACED8, CLK cup HGH and LOW times are guaranteed to meet 80286 requirements. (3-268
- 9100 DEVICE DEVICE UNDER UNDER TEST TEST T 75 pF T 150 pF ~ 710004260 - TC004270 A. PCLK Output B. READY Output DEVICE DEVICE UNDER UNDER TEST TEST T 150 pF T 75 pF _ ei C. CLK Outputs D. RESET Output 3-269
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8 SWITCHING TEST WAVEFORMS
o | 24V assy YF Kv WF024590 ‘A. EFI Drive and Measurement Points 3.0V 26V 0.45V / \\ o8v wro24s40 | B. RES Drive and Measurement Points i 36V 36V 1.0V 1.0V WF024550 C. CLK Output Measurement Points ook 36V eV OUTPUT 1.0V 1.0V | 'seTuP HOLD | 24v as DS | device “WVYVVV7 | 200 TKXXXKKKK eur YYW oe | osv LOX EFI8 RES) 0.45V 1 ‘DELAY —>| YYVYVVVYVWYY{VW@VWYVYVW{W¥VWVW®P¥_Vvyv- 200 XA AAA 0.8V WF024560 D. AC Setup, Hold and Delay Time Measurement - General 3.270
| SWITCHING WAVEFORMS 8 (3) a a am cu ', i) Note: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH CLK as a Function of EFI Dan © NOTE? =o (IMU Notes: 1. This is an asynchronous input. The setup and hold times shown are required to guarantee the 2. Te ono oh 5% pull-up resistor to the READY output. This LOW-to-HIGH transition depends on the state of ARDY, ARDYEN, SADY, and SADYEN. RESET and READY Timing as a Function of RES with 51 and SO HIGH [De pe Ee) ae co tO; © eee, el = coy olor Notes: 1. This is an asynchronous input. The setup and hold times shown are required to quarantee the 2. Testo ons % pull-up resistor to the READY output. READY and PCLK Timing with RES HIGH