U2500

T2700 INTEL | Alldatasheet

Document overview

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• PDF pages: 91

Technical content

Datasheet sections

• 1.1 Terminology
• 1.2 References
• 2 Low Power Features
• 2.1 Clock Control and Low Power States
• 2.1.1 Core Low-Power States
• 2.1.1.1 C0 State
• 2.1.1.2 C1/AutoHALT Powerdown State
• 2.1.1.3 C1/MWAIT Powerdown State
• 2.1.1.4 Core C2 State
• 2.1.1.5 Core C3 State
• 2.1.1.6 Core C4 State
• 2.1.2 Package Low Power States
• 2.1.2.1 Normal State
• 2.1.2.2 Stop-Grant State
• 2.1.2.3 Stop Grant Snoop State
• 2.1.2.4 Sleep State
• 2.1.2.5 Deep Sleep State
• 2.1.2.6 Deeper Sleep State
• 2.2 Enhanced Intel SpeedStep® Technology
• 2.3 Extended Low Power States
• 2.4 FSB Low Power Enhancements
• 2.5 Processor Power Status Indicator (PSI#) Signal
• 3 Electrical Specifications
• 3.1 Power and Ground Pins
• 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
• 3.3 Voltage Identification
• 3.4 Catastrophic Thermal Protection
• 3.5 Signal Terminations and Unused Pins
• 3.6 FSB Frequency Select Signals (BSEL[2:0])
• 3.7 FSB Signal Groups
• 3.8 CMOS Signals
• 3.9 Maximum Ratings
• 3.10 Processor DC Specifications
• 4 Package Mechanical Specific ations and Pin Information
• 4.1 Package Mechanical Specifications
• 4.1.1 Package Mechanical Drawings
• 4.1.2 Processor Component Keep-Out Zones
• 4.1.3 Package Loading Specifications
• 4.1.4 Processor Mass Specifications
• 4.2 Processor Pinout and Pin List
• 4.3 Alphabetical Signals Reference
• 5 Thermal Specifications and Design Considerations
• 5.1 Thermal Specifications
• 5.1.1 Thermal Diode
• 5.1.2 Thermal Diode Offset
• 5.1.3 Intel® Thermal Monitor
• 5.1.4 Digital Thermal Sensor (DTS)
• 5.1.5 Out of Specification Detection

Document Number: 309221-006 Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Datasheet January 2007

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Core™ Duo processor and the Intel® Core™ Solo processo r may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Core Duo, Intel Core Solo, Pentium, Intel SpeedStep, MMX and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 - 2007, Intel Corporation. All rights reserved.

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3 Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and

4 Deeper Sleep V CC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and

6 Deeper Sleep V

10 Voltage and Current Specifications for Intel Co re Solo Processor ULV (Ultra Low Voltage)...33

28 Thermal Diode n

Revision History

-001 Initial Release January 2006 -002

• Added references to ULV processor throughout the document
• Replaced references to the terminology Deep C4 voltage with Intel® Enhanced Deeper Sleep Voltage throughout the document.
• Replaced references to Enhanced Low Power states with CxE Low Power States
• Section 3.10 — Included Table 10 Voltage and Current Specifications for Intel Core Solo Processor ULV — Included Figure 5 Active VCC and ICC Load Line for Intel Core Solo Processor ULV — Included Figure 6 Deeper Sleep VCC and ICC Load Line for Intel Core Solo Processor ULV
• Chapter 5 — Included Table 24 Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) April 2006 -003 • Added Intel® Core™ Duo Processor T2300E and Intel® Core™ Solo Processor T1400 specifications. May 2006 -004
• Added references to Intel Core Duo Proce ssor, Ultra Low Voltage (ULV) throughout the document
• CxE low power states now also referred to as Extended Low Power States
• Section 3.10 —U p d a t e d Table 6 - Added Icc spec for T2700 — Included Table 9 Voltage and Current Specifications Intel Core Duo Processor, Ultra Low Voltage (ULV)
• Chapter 5 —U p d a t e d Table 20 - Added TDP for T2700 — Included Table 23 - Power Specification for Intel Core Duo Processor Ultra Low Voltage (ULV) June 2006 -005
• I n Chapter 3: — Added L2500 processor specifications to Table 8. — Added U2400 processor specifications to Table 9.
• I n Chapter 5: — Added L2500 processor power specifications to Table 22. — Added U2400 processor power specifications to Table 23. September 2006 -006
• I n Chapter 3: — Added U1500 processor specifications to Table 10.
• I n Chapter 5: — Added U1500 processor power specifications to Table 24. January 2007

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1 Introduction

The Intel® CoreTM Duo processor and the Intel® CoreTM Solo processor are built on Intel’s next generation 65 nanometer process technology with copper interconnect. The Intel Core Solo processor refers to a single core processor and the Intel Core Duo processor refers to a dual core processor. This document provides specifications for all Intel Core Duo processor and Intel Core Solo processor in standard voltage (SV), low voltage (LV) and ultra low voltage (ULV) products. Note: All instances of the “processor” in this document refer to the Intel Core Duo processor and Intel Core Solo processor with 2-MB L2 cache, unless specified otherwise. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor:

• First dual core processor for mobile
• Supports Intel® Architecture with Dynamic Execution
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache
• On-die, 2-MB second level cache with Advanced Transfer Cache Architecture
• Data Prefetch Logic
• Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)
• T h e I n t e l Core Duo processor and Intel Core Solo processor standard voltage and low voltage processors are offered at 667-MHz FSB
• The Intel Core Duo processor and Intel Core Solo processor ultra low voltage are offered at 533-MHz FSB
• Advanced power management features including Enhanced Intel SpeedStep® Technology
• Digital thermal sensor (DTS)
• T h e I n t e l Core Duo processor and Intel Core Solo processor standard voltage are offered in both the Micro-FCPGA and the Micro-FCBGA packages
• I n t e l Core Duo processor low voltage is offered only in the Micro-FCBGA package
• T h e I n t e l Core Duo processor and Intel Core Solo processor ultra low voltage are offered only in Micro-FCBGA package
• Execute Disable Bit support for enhanced security
• Intel® Virtualization Technology
• Intel® Enhanced Deeper Sleep and Dynamic Cache Sizing The processor maintains support for MMX™ te chnology, Streaming SIMD instructions, and full compatibility with IA-32 software. The processor features on-die, 32-KB, Level 1 instruction and data caches and a 2-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced to help with the write-back latency performance.

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In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions which extend the capabilities of Intel processor technology further. These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics and other entertainment applications, such as gaming, will have the opportunity to take advantage of these new instructions as platforms with the processor and SSE3 become available in the market place. The processor’s FSB utilizes a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. The 4X data bus can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X address bus provide a data bus bandwidth of up to 5.33 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor features Enhanced Intel SpeedStep Technology, which enables real-time dynamic switching between multiple voltage and frequency points. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep low power C-states. The processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. The processor supports the Execute Disable Bit capability. This feature, combined with a support operating system, allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. Intel Virtualization Technology is a set of hardware enhancements to Intel server and client systems that combined with the appropriate software, will enable enhanced virtualization robustness and performance for both enterprise and consumer uses. Intel Virtualization Technology forms the foundation of Intel technologies focused on improved virtualization, safer computing, and system stability. For client systems, Intel Virtualization Technology’s hardware-based isolation helps provide the foundation for highly available and more secure client virtualization partitions.

1.1 Terminology

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document. Chipset references in this document are to the Mobile Intel® 945 Express Chipset family unless specified otherwise. Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors. Document Document Number Intel® Core™ Duo Proces sor and Intel® Core™ So lo Processor on 65 nm Process Specification Update 309222 Mobile Intel® 945 Express Chipset Family Datasheet 309219 Mobile Intel® 945 Express Chipset Family Specification Update 309220 Intel® I/O Controller Hub 7 (ICH7) Family Datasheet 307013 Intel® I/O Controller Hub 7 (ICH7) Family Specification Update 307014 Intel® Architecture Software Developer's Manual Volume 1 Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 AP-485, Intel® Processor Identification and CPUID Instruction Application Note 241618

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2 Low Power Features

2.1 Clock Control and Low Power States

both at the individual core level and the package level for optimal power management. P_LVLx read can be configured in a software programmable MSR. the Intel Core Duo processor will enter the Deeper Sleep state. Table 1. Coordination of Core-Level Low Power States at the Package Level

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Figure 1. Package-Level Low Power States Figure 2. Core Low Power States † — Deeper Sleep includes the Deeper Sleep and the Intel Enhanced Deeper Sleep state. † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper sleepstate.

2.1.1 Core Low-Power States

2.1.1.1 C0 State

This is the normal operating state for the Intel Core Duo processor and Intel Core Solo processor.

2.1.1.2 C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when the processor core executes the HALT instruction. The processor core will transition to the C0 state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® Architecture Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate an STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Powerdown state, the dual core processor will process bus snoops and snoops from the other core, and the single core processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3 C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® Architecture Software Developer's Manual, Volumes 2A/2B: Instruction Set Reference, for more information.

2.1.1.4 Core C2 State

Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in C2 state, the dual core processor will process bus snoops and snoops from the other core, and the single core processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the C2 state.

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2.1.1.5 Core C3 State

Core C3 state is a very low power state the processor core can enter while maintaining context. Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual core processor accesses cacheable memory. The processor core will transition to the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.

2.1.1.6 Core C4 State

Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C4 state by initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, then the central power management logic will request that the entire dual core processor enter the Deeper Sleep package low power state (see Section 2.1.2.5). The single core processor would be put into the Deeper Sleep State in C4 state if the low power state coordination logic is enabled. To enable the package level Intel Enhanced Deeper Sleep Low Voltage, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR.

2.1.2 Package Low Power States

The package level low power states are applicable for the Intel Core Duo processor as well as the Intel Core Solo processor. The package level low power states are described

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor enters the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2 Stop-Grant State

When the STPCLK# pin is asserted, each core of the Intel Core Duo processor and Intel Core Solo processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low- power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 450 µs prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#. While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire dual core processor should return to the Normal state. A transition to the Stop Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal.

2.1.2.3 Stop Grant Snoop State

The processor will respond to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.

2.1.2.4 Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.

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2.1.2.5 Deep Sleep State

Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms with the CK410M clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip mu st drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re- started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

2.1.2.6 Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to one of two lower levels. One lower core voltage level is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor will drive the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point.

2.1.2.6.1 Intel Enhanced Deeper Sleep State

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero.
• The processor drives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins.

2.1.2.6.2 Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions:

• The second core is already in C4 and the Intel Enhanced Deeper Sleep state is
• The C0 timer, which tracks continuous residency in the Normal package state, has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions. Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded when the next INTR event would occur. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, then the processor does not enter the Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full size.

2.2 Enhanced Intel SpeedStep® Technology

Intel Core Duo processor and Intel Core Solo processor feature Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage/frequency operating points provide optimal performance at the lowest power.
• Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers). — If the target frequency is higher than the current frequency, V CC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than th e current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp ra tes internally to ensure glitch free transitions.
• Low transition latency and large number of transitions possible per second. — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition

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— The bus protocol (BNR# mechanism) is used to block snooping

• Improved Intel® Thermal Monitor mode. — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/ voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management.
• Enhanced thermal management features. — Digital thermal sensor and thermal interrupts — TM1 in addition to TM2 in case of non successful TM2 transition. — dual core thermal management synchronization. Each core in the Intel Core Duo processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage then the Intel Core Duo processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests then the Intel Core Duo processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage.

2.3 Extended Low Power States

The Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state. Instead of directly transitioning into the package low power states, the extended low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the package low power states. The processor implements two software interfaces for requesting extended low power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring a software programmable MSR bit to automatically promote package low power states to extended low power states. Note: C2E and C4E must be enabled via the BIOS for the processor to remain within specification. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states. C4E is an exception to this rule when the Hard C4E configuration is enabled in a software programmable MSR bit. This C4E low power state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state

entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.

2.4 FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low VCCP (I/O termination voltage) The Intel Core Duo processor and Intel Core Solo processor incorporate the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.

2.5 Processor Power Status Indicator (PSI#) Signal

The Intel Core Duo processor and Intel Core Solo processor incorporate the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and improved battery life. The algorithm that the Intel Core Duo processor and Intel Core Solo processor use for determining when to assert PSI# is different from the algorithm used in previous Intel® Pentium® M processors.

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3 Electrical Specifications

3.1 Power and Ground Pins

voltage determined by the VID (Voltage ID) pins.

3.2 FSB Clock (BCLK[1:0] ) and Processor Clocking

processor uses a differential clocking implementation.

3.3 Voltage Identification

Table 2. Voltage Identification Definition (Sheet 1 of 4)

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Table 2. Voltage Identification Definition (Sheet 2 of 4)

Table 2. Voltage Identification Definition (Sheet 3 of 4)

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3.4 Catastrophic Thermal Protection

to thermal runaway of the processor. Table 2. Voltage Identification Definition (Sheet 4 of 4)

3.5 Signal Terminations and Unused Pins

processor and the location of all RSVD pins. a 51 Ω ±5%, pull-down resistor to VSS.

3.6 FSB Frequency Select Signals (BSEL[2:0])

3.7 FSB Signal Groups

Table 3. BSEL[2:0] Encoding for BCLK Frequency

26 Datasheet

1. Refer to Table 17 for signal descriptions and termination requirements.
2. In processor systems where there is no debug port implemented on the system board, these signals are

board, these signals are no connects.

1. BPM[2:1]# and PRDY# are AG TL+ output only signals.
2. PROCHOT# signal type is open drain output and CMOS input.

Table 4. FSB Pin Groups

3.8 CMOS Signals

3.9 Maximum Ratings

operation limits, can functionality and long-term reliability be expected. exposure to conditions exceeding the functional operation condition limits.

1. This rating applies to any processor pin.
2. Contact Intel for storage requir ements in excess of one year.

Table 5. Processor DC Ab solute Maximum Ratings

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3.10 Processor DC Specifications

signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. CMOS group are listed in Table 13. Table 6. Voltage and Current Specifications for Intel Core Duo Processor SV (Standard

2.33 GHz and HFM V

2.16 GHz and HFM VCC

2.00 GHz and HFM VCC

1.83 GHz and HFM VCC

1.66 GHz and HFM VCC

1 GHz and LFM VCC

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

1. The voltage specifications are as sumed to be measured across VCCSENSE and VSSSENSE pins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the VID voltage.
2. The I CCDES(max) specification of 36 A comprehends only Intel Core Duo processor SV HFM frequencies.

Platforms should be designed to 44 A to be compatible with next generation processor.

1. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. Measured at the bulk capa citors on the motherboard.
2. V CC, boot tolerance is shown in Figure 3.
3. This is a steady-state I CCP current specification, which is applicable when both VCCP and VCC core are high.
4. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC core is low.
5. Specified at the nominal V CC.
6. If a given Operating Systems C-St ate model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

1. T2300E does not support Intel Virtualization Technology.

30 Datasheet

1. Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

1. The voltage specifications are a ssumed to be measured across VCCSENSE and VSSSENSE pins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the VID voltage.
2. The I CCDES(max) specification of 36 A comprehends only Intel Core Solo processor SV HFM frequencies.

Table 7. Voltage and Current Specifications fo r Intel Core Solo Processor SV (Standard

1.83 GHz and HFM V

15.5 A 3,11

1. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. Measured at the bulk capa citors on the motherboard.
2. V CC, boot tolerance is shown in Figure 3.
3. This is a steady-state Iccp current specification, which is applicable when both VCCP and Vcc core are high.
4. This is a power-up peak current spec ification, which is applicable when VCCP is high and Vcc core is low.
5. Specified at the nominal V CC.
6. If a given Operating System C-St ate model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID. Table 8. Voltage and Current Specifications for Intel Core Duo Processor LV (Low

1.50 GHz and HFM VCC

32 Datasheet

1. Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

1. The voltage specifications are a ssumed to be measured across VCCSENSE and VSSSENSE pins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the VID voltage.

CCDES(max) specification of 19 A comprehends only Intel Core Duo processor LV HFM frequencies.

1. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. Measured at the bulk capacitors on the motherboard.
2. V CC, boot tolerance is shown in Figure 3.
3. This is a steady-state Iccp current specification, which is applicable when both VCCP and VCC core are high.
4. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC core is low.
5. Specified at the nominal V CC.
6. If a given Operating System C-St ate model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID. Table 9. Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage

1.20 GHz and HFM V

1.06 GHz and HFM VCC

800 MHz and LFM VCC

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

(Thermal Monitor 2, Enhanced Intel SpeedStep technology, or C1E).

1. The voltage specifications are as sumed to be measured across VCCSENSE and VSSSENSE pins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the VID voltage.
2. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. Measured at the bulk capa citors on the motherboard.
2. V CC, boot tolerance is shown in Figure 3.
3. This is a steady-state Iccp current specif ication, which is applicable when both VCCP and VCC_CORE are high.
4. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
5. Specified at the nominal V CC.
6. If a given Operating System C-St ate model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID. Table 10. Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra

34 Datasheet

1. Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or C1E).

1. The voltage specifications are a ssumed to be measured across VCCSENSE and VSSSENSE pins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the VID voltage.
2. This specification comprehends Intel Core Duo processor ULV processor HFM frequencies.
3. Based on simulations and averaged over the durati on of any change in current. Specified by design/
4. Measured at the bulk capacitors on the motherboard.
5. Vcc, boot tolera nce is shown in Figure 5.
6. This is a steady-state I CCP current specification, which is applicable when both VCCP and VCC_CORE are high.
7. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
8. Specified at the nominal V CC.
9. If a given Operating System C-St ate model is not based on the use of MWAIT or I/O Redirection, the

processor Deeper Sleep VID will be same as LFM VID.

1.33 GHz and HFM V

1.20 GHz and HFM VCC

Figure 3. Active V CC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Differential Remote Sense required.

36 Datasheet

NOTE: For low voltage, if PSI# is not asserted, then the 13-mV ripple allowance becomes 10 mV. Figure 4. Deeper Sleep V CC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) Differential Remote Sense required.

Figure 5. Active V CC and ICC Loadline for Intel Core Solo Processor ULV Differential Remote Sense required.

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Figure 6. Deeper Sleep V CC and ICC Loadline for Intel Core Solo Processor ULV Differential Remote Sense required.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as abso lute voltage where rising edge of BCLK0 is equal to the falling edge of
3. Threshold Region is defined as a re gion entered about the crossing voltage in which the differential receiver

switches. It includes input threshold hysteresis.

1. For Vin between 0 V and V IH.
2. Cpad includes die capacitance only. No package parasitics are included.
3. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
4. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
5. V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
6. V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
7. V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the

signal quality specifications.

1. This is the pull-down driver resistance.
2. GTLREF should be generated from V

decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP.

1. R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver.
2. Specified with on die R TT and RON are turned off.
3. Cpad includes die capacitance only. No package parasitics are included.

Table 11. FSB Differential BCLK Specifications Table 12. AGTL+ Signal Group DC Specifications

40 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V CCP referred to in these specifications refers to instantaneous VCCP.
3. For Vin between 0 V and V CCP. Measured when the driver is tristated.
4. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#,PWRGOOD. No package parasitics are included.
5. Cpad2 includes die capaci tance for all other CMOS input signals. No package parasitics are included.
6. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
7. V OH is determined by value of the external pullup resistor to VCCP. Please contact your Intel representative
8. For Vin between 0 V and V OH.
9. Cpad includes die capacitance only. No package parasitics are included.

Table 13. CMOS Signal Group DC Specifications Table 14. Open Drain Signal Group DC Specifications

Package Mechanical Specifications and Pin Information

4 Package Mechanical

4.1 Package Mechanical Specifications

The Intel Core Duo processor and Intel Core Solo processor are available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7 through Figure 10. Table 15 (two sheets) shows a top-view of package pin-out with their functionalities. Warning: The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive, care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors, and possibly damage the device or render it inactive.

4.1.1 Package Mechanical Drawings

Different views showing all pertinent dimensions of the Micro-FCPGA package are shown in Figure 7 and continued in Figure 8. Views and pertinent dimensions for Micro- FCBGA package are shown in Figure 9 and continued in Figure 10.

42 Datasheet

Figure 7. Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

Figure 8. Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

44 Datasheet

Figure 9. Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)

Figure 10. Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)

Package Mechanical Specifications and Pin Information

46 Datasheet

4.1.2 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted in the keep- out areas. The location and quantity of the capacitors may change, but will remain within the component keep-in. See Figure 7 and Figure 9 for keep-out zones.

4.1.3 Package Loading Specifications

Maximum mechanical package loading specifications are given in Figure 7 and Figure 9. These specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading. These limitations are more platform specific, and should be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution.

4.1.4 Processor Mass Specifications

The typical mass of the processor is given in Figure 7 and Figure 9. This mass includes all the components that are included in the package.

4.2 Processor Pinout and Pin List

different formats is shown in the following pages. Table 15. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package

48 Datasheet

Table 16. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package

4.3 Alphabetical Signals Reference

Table 17. Signal Description (Sheet 1 of 9) sampled before RESET# is deasserted. Output Write bus transaction. reply ID match operations associated with the new transaction. outputs and latch their inputs. stall, the current bus owner cannot issue any new transactions.

50 Datasheet

performance monitoring tools. the FSB. It must connect the appropriate pins of both FSB agents. the bus by deasserting BPRI#. Intel® 945 Express Chipset family (High Priority Agent). (166-MHz or 133-MHz BCLK[1:0] frequency, respectively). representative for more implementation details. Table 17. Signal Descript ion (Sheet 2 of 9)

indicate a valid data transfer. group is inverted and therefore sampled active high. connect in the system. DBR# is not a processor signal. connect the appropriate pins on both FSB agents. Table 17. Signal Description (Sheet 3 of 9)

52 Datasheet

within the covered group, would change level in the next cycle. deasserted. DPRSTP# is driven by the Intel® ICH7M chipset. driven by the ICH7M chipset.

945 Express

clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. Table 17. Signal Descript ion (Sheet 4 of 9)

when the processor detects an unmasked floating-point error. event, it will remain asserted until STPCLK# is deasserted. CPUID Instruction Application Note. GTLREF determines the signal reference level for AGTL+ input pins. can be continued by reasserting HIT# and HITM# together. no effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. Table 17. Signal Description (Sheet 5 of 9)

54 Datasheet

connect the appropriate pins of both FSB agents. RESET#, then the processor executes its Built-in Self-Test (BIST). Pentium processor. Both signals are asynchronous. Table 17. Signal Descript ion (Sheet 6 of 9)

processor has reached its maximum safe operating temperature. active until the system deasserts PROCHOT#. PROCHOT# must be enabled via the BIOS. This signal may require voltage translation on the motherboard. Please contact your Intel representative for more details. state (Deep Sleep and Deeper Sleep). then transition monotonically to a high state. should be driven high throughout boundary scan operation. source synchronous to ADSTB[0]#. (nominal) on die pull-up resistor on this signal. must connect the appropriate pins of both FSB agents. contact your Intel representative for more details. Table 17. Signal Description (Sheet 7 of 9)

56 Datasheet

processor begins program execution from the SMM handler. signals to all processor core units except the FSB and APIC units. clock; STPCLK# is an asynchronous input. (also known as the Test Access Port). requirements and implementation details. provides the serial input needed for JTAG specification support. requirements and implementation details. TDO (Test Data Out) transfers serial test data out of the processor. requirements and implementation details. contact your Intel representative for more details. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. Table 17. Signal Descript ion (Sheet 8 of 9)

system by the THERMTRIP# (Thermal Trip) pin. requirements and implementation details. must connect the appropriate pins of both FSB agents. requirements and implementation details. must be driven low during power on Reset. requirements and implementation details. CC Input Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. VCCP Input Processor I/O Power Supply. should be used to sense voltage near the silicon with little noise. regarding termination and routing recommendations. needed to support the processor voltage specification variations. voltage that is requested by the pins, or disable itself. Intel® MVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense ground near the silicon with little noise. regarding termination and routing recommendations. Table 17. Signal Description (Sheet 9 of 9)

Package Mechanical Specifications and Pin Information

58 Datasheet

Table 18. Pin Listing by Pin Name

60 Datasheet

62 Datasheet

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66 Datasheet

68 Datasheet

Table 19. Pin Listing by Pin Number

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Thermal Specifications and Design Considerations

5 Thermal Specifications and

The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 20 to Table 22. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 20 to Table 22. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.

80 Datasheet

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
2. T2300E does not support Intel Virtualization Technology.

Table 20. Power Specifications for the Inte l Core Duo Processor SV (Standard Voltage)

2.33 GHz & HFM V

2.16 GHz & HFM VCC

2.00 GHz & HFM VCC

1.83 GHz & HFM VCC

1.66 GHz & HFM VCC

1.00 GHz & LFM VCC

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate

Table 21. Power Specifications for the Intel Core Solo Processor SV (Standard Voltage)

1.83 GHz & HFM V

82 Datasheet

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate

Table 22. Power Specifications for the In tel Core Duo Processor LV (Low Voltage)

1.50 GHz & HFM VCC

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate

Table 23. Power Specifications for the In tel Core Duo Processor, Ultra Low Voltage

1.20 GHz & HFM V

1.06 GHz & HFM VCC

800 MHz & LFM VCC

84 Datasheet

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate

Table 24. Power Specifications for the In tel Core Solo Processor ULV (Ultra Low

1.20 GHz and HFM

5.1 Thermal Specifications

specified processor junction temperature has been reached.

5.1.1 Thermal Diode

diode usage recommendation when the PROCHOT# signal is not asserted. location on the die, and time based variations in the die temperature measurement. processor Model Specific Register (MSR). Table 27. The Diode Model parameters (Table 26) apply to traditional thermal sensors thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor. Table 25. Thermal Diode Interface

86 Datasheet

1. Intel does not support or re commend operation of the thermal diode under reverse bias.

power supplies are not within their specified tolerance range.

1. Characterized across a temperature range of 50 - 100°C.
2. Not 100% tested. Specified by design characterization.
3. The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by

Boltzmann Constant, and T = absolute temperature (Kelvin).

1. The series resistance, R T, is provided to allow for a more accurate measurement of the

Constant, q = electronic charge.

1. Intel does not support or re commend operation of the thermal diode under reverse bias.
2. Same as I FW in Table 25.
3. Characterized across a temperature range of 50 - 100°C.
4. Not 100% tested. Specified by design characterization.
5. The ideality factor, nQ, represents the deviat ion from ideal transistor model behavior as
6. The series resistance, R T, provided in the Diode Model Table (Table 26) can be used for

more accurate readings as needed. Table 26. Thermal Diode Parameters using Diode Mode Table 27. Thermal Diode Parame ters using Transistor Mode

5.1.2 Thermal Diode Offset

Model Specific Register (MSR) which will contain thermal diode characterization data. ntrim as defined in the temperature sensor manufacturers' datasheet.

5.1.3 Intel® Thermal Monitor

the TCC is active continuously. Table 28. Thermal Diode n

Thermal Specifications and Design Considerations

88 Datasheet

The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence. Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the Model Specific Registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if TM2 is not sufficient to cool the processor below the maximum operating temperature then TM1 will also activate to help cool down the processor. Intel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the Intel Core Duo processor and Intel Core Solo processor. If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results: 1. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is higher than the Intel Thermal Monitor 2 transition-based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the Intel Thermal Monitor 2 transition-based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non- critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be On-demand mode may be used at the same time automatic mode is enabled, however,

Thermal Specifications and Design Considerations if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.

5.1.4 Digital Thermal Sensor (DTS)

The processor also contains an on-die DTS that can be read via a MSR (no I/O interface). In a dual core implementation of the Intel Core Duo processor, each core will have a unique DTS whose temperature is accessible via processor MSR. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the DTS will output a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the digital thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The DTS relative temperature readout corresponds to the Intel Thermal Monitor (TM1/ TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical

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and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC.

5.1.5 Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt.

5.1.6 PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. In a dual core implementation, only a single PROCHOT# pin exists at a package level. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state. Note: It is important to note that Intel recommends both TM1 and TM2 be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor core will enter the lowest programmed TM2 performance state. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very

Thermal Specifications and Design Considerations short periods of time when running the most power intensive applications. An under- designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.