87C51FA INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. September 1993COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 270961-003 87C51FA/87C51FB/87C51FC/87C51FC-20 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive Y FX Core Architecture Device Y Extended Automotive Temperature Range ( b40§Ct o a125§C Ambient) Y Available in 12 MHz, 16 MHz and
20 MHz Versions
Y High Performance CHMOS EPROM Y Three 16-Bit Timer/Counters Ð Timer 2 (Up/Down Counter) Y Programmable Counter Array with: Ð High Speed Output, Ð Compare/Capture, Ð Pulse Width Modulator, Ð Watchdog Timer Capabilities Y One-to-Three Level Program Lock System on EPROM Y 8K On-Chip User Programmable EPROM in 87C51FA Y 16K On-Chip User Programmable EPROM in 87C51FB Y 32K On-Chip User Programmable EPROM in 87C51FC Y 256 Bytes of On-Chip Data RAM Y Quick Pulse Programming Algorithm Y Boolean Processor Y 32 Programmable I/O Lines Y 7 Interrupt Sources Y Four Level Interrupt Priority Y Programmable Serial Channel with: Ð Framing Error Detection Ð Automatic Address Recognition Y TTL and CMOS Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y MCSÉ-51 Fully Compatible Instruction Set Y Power Saving Idle and Power Down Modes Y ONCE (On-Circuit Emulation) Mode Y RFI Reduction Mode Y Available in PLCC and PDIP Packages MEMORY ORGANIZATION PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the 87C51FA On-Chip EPROM. Up to 16 Kbytes of the program memory can reside in the 87C51FB on-chip EPROM. Up to 32 Kbytes of the program memory can reside in the 87C51FC on-chip EPROM. In addition the device can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 25 6 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of external data memory. The Intel 87C51FA/87C51FB/87C51FC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS EPROM technology. Being a member of the MCS-51 family, the 87C51FB/87C51FC uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of products. The 87C51FA is an enhanced version of the 87C51. The 87C51FB is an enhanced version of the 87C51FA. The 87C51FC is an enhanced version of the 87C51FB. With 8 Kbytes of program memory in the 87C51FA and 16 Kbytes of program memory in the 87C51FB and 32 Kbytes of program memory in the 87C51FC, it is an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as brake and traction control. For the remainder of this document, the 87F51FA, 87C51FB and 87C51FC will be referred to as the 87C51FA/FB/FC.
Figure 1. 87C51FB/FC Block Diagram
with 16 Kbyte/32 Kbyte EPROM program memory. Figure 2. Package Options Table 1. Temperature Options
quired during program verification. EPROM programming and verifying. **Do not connect reserved pins. Figure 3. Pin Connections (Top View)
of the P2 Special Function Register. IL, on the data sheet) because of the pullups. cess to external Data Memory. internally latched on reset. age (V PP) during EPROM programming. XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifier. Figure 4. Either a quartz crystal or ceramic resonator Design for Microcontrollers’’.
writes to a port pin or to external memory.
- Pull ALE low while the device is in reset and
- Hold ALE low as RST is deactivated.
emulator or test CPU can be used to drive the circuit. disables the ALE pin during instruction code fetches. ware or until a hardware reset occurs. Table 2. Status of the External Pins during Idle and Power Down
AUTOMOTIVE 87C51FA/FB/FC/FC-20 ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias b40§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA/V PP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (Based on package heat transfer limitations, not device power consumption) Typical Junction Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ a135§C (Based on ambient temperature at a125§C) Typical Thermal Resistance Junction-to-Ambient (iJA): PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45 §C/W PLCC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46 §C/W NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION DC CHARACTERISTICS: (TA eb 40§Ct o a125§C; V CC e 5V g 20%; V SS e 0V) Symbol Parameter Min Typ Max Unit Test Conditions(Note 4) VIL Input Low Voltage b0.5 0.2 V CC b 0.1 V VIL1 Input Low Voltage EA 0 0.2 V CC b 0.3 V VIH Input High Voltage 0.2 V CC a 0.9 V CC a 0.5 V (Except XTAL1, RST, EA ) VIH1 Input High Voltage (XTAL1, RST) 0.7 V CC VCC a 0.5 V VOL Output Low Voltage (Note 5) 0.3 V I OL e 100 mA (Note 1) (Ports 1, 2 and 3) 0.45 V I OL e 1.6 mA (Note 1) 1.0 V I OL e 3.5 mA (Note 1) VOL1 Output Low Voltage (Note 5) 0.3 V I OL e 200 mA (Note 1) (Port 0, ALE, PSEN ) 0.45 V I OL e 3.2 mA (Note 1) 1.0 V I OL e 7.0 mA (Note 1) VOH Output High Voltage V CC b 0.3 V I OH eb 10 mA (Ports 1, 2 and 3) VCC b 0.7 V I OH eb 30 mA VCC b 1.5 V I OH eb 60 mA VOH1 Output High Voltage V CC b 0.3 V I OH eb 200 mA (Port 0 in External Bus Mode, VCC b 0.7 V I OH eb 3.2 mAALE, PSEN ) VCC b 1.5 V I OH eb 7.0 mA IIL Logical 0 Input Current b75 mAV IN e 0.45V (Ports 1, 2 and 3) ILI1 Input Leakage Current (Port 0 ) g10 mA 0.45V k VIN k VCC ITL Logical 1 to 0 Transition Current b750 mAV IN e 2V (Ports 1, 2 and 3) RRST RST Pulldown Resistor 40 225 K X CIO Pin Capacitance 10 pF @1 MHz, 25 §C ICC Power Supply Current: (Note 3) Running at 16/20 MHz (Figure 6) 26/28 35/40 mA Idle Mode at 16/20 MHz (Figure 6) 5 12/14 mA Power Down Mode 15 100 mA
AUTOMOTIVE 87C51FA/FB/FC/FC-20 EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, T AVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low AC CHARACTERISTICS (TA eb 40§Ct o a125§C, V CC e 5V g 20%, V SS e 0V, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol Parameter
12 MHz Variable Oscillator
1/TCLCL Oscillator Frequency 3.5 16/20 MHz TLHLL ALE Pulse Width 127 2T CLCL b 40 ns TAVLL Address Valid to ALE Low 43 T CLCL b 40 ns TLLAX Address Hold After ALE Low 53 T CLCL b 30 ns TLLIV ALE Low to Valid 234 4T CLCL b 100/ ns Instruction In 4T CLCL b 75* TLLPL ALE Low to PSEN Low 53 T CLCL b 30 ns TPLPH PSEN Pulse Width 205 3T CLCL b 45 ns TPLIV PSEN Low to Valid 145 3T CLCL b 105/ ns Instruction In 3T CLCL b 90* TPXIX Input Inst. Hold After 0 0 ns PSEN Trans TPXIZ Input Inst. Float After 59 T CLCL b 25/ ns PSEN Trans T CLCL b 20* TAVIV Address Valid to Valid 312 5T CLCL b 105 ns Instruction In TPLAZ PSEN Low to Address 10 10 ns Float TRLRH RD Pulse Width 400 6T CLCL b 100 ns TWLWH WR Pulse Width 400 6T CLCL b 100 ns
AUTOMOTIVE 87C51FA/FB/FC/FC-20 AC CHARACTERISTICS (TA eb 40§Ct o a125§C, V CC e 5V g 20%, V SS e 0V, Load Capaci- tance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF) (Continued) ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued) Symbol Parameter TRLDV RD Low to Valid Data In 252 5T CLCL b 165/ ns 5TCLCL b 95* TRHDX Data Hold After RD High 0 0 ns TRHDZ Data Float After RD High 107 2T CLCL b 60 ns TLLDV ALE Low to Valid Data In 517 8T CLCL b 150/ ns 8TCLCL b 90* TAVDV Address Valid to Valid Data In 585 9T CLCL b 165/ ns 9TCLCL b 90* TLLWL ALE Low to RD or WR Low 200 300 3T CLCL b 50 3T CLCL a 50 ns TAVWL Address Valid to WR Low 203 4T CLCL b 130/ ns 4TCLCL b90* TQVWX Data Valid before WR Low 33 T CLCL b 50/ ns TCLCL b 35* TWHQX Data Hold after WR High 33 T CLCL b 50/ ns TCLCL b 40* TQVWH Data Valid to WR High 433 7T CLCL b 150/ ns 7TCLCL b 70* TRLAZ RD Low to Address Float 0 0 ns TWHLH RD or WR High to ALE High 43 123 T CLCL b 40 T CLCL a 40 ns NOTE: *Timings specified for the 87C51FC-20 are valid at 20 MHz only. For timing information below 20 MHz, use the 87C51FA/ FB/FC timings.
AUTOMOTIVE 87C51FA/FB/FC/FC-20 EXTERNAL PROGRAM MEMORY READ CYCLE 270961–12 EXTERNAL DATA MEMORY READ CYCLE 270961–13 EXTERNAL DATA MEMORY WRITE CYCLE 270961–14
AUTOMOTIVE 87C51FA/FB/FC/FC-20 SERIAL PORT TIMINGÐSHIFT REGISTER MODE Test Conditions: TA eb 40§Ct o a125§C; V CC e 5V g 20%; V SS e 0V; Load Capacitance e 80 pF Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max TXLXL Serial Port Clock Cycle Time 1 12T CLCL ms TQVXH Output Data Setup to Clock 700 10T CLCLb133 ns Rising Edge TXHQX Output Data Hold after 50 2T CLCLb117 ns Clock Rising Edge TXHDX Input Data Hold After Clock 0 0 ns Rising Edge TXHDV Clock Rising Edge to Input 700 10T CLCLb133 ns Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 270961–15 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 16/20 MHz 87C51FA/FB/FC TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORMS 270961–16
min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. Table 3. EPROM Programming Modes P3.5 respectively for A0–A13. DATA LINES: P0.0–P0.7 for D0–D7. turned to a high (also refer to timing diagrams).
Figure 11. Programming the EPROM
- Input the valid address on the address lines.
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control sig-
/VPP from V CC to 12.75V g0.25V.
- Pulse ALE/PROG 5 times for the EPROM array,
programming of the 87C51FA/FB/FC. Lock section in this data sheet.
5 Pulses
Figure 12. Programming Signal’s Waveforms
Table 4. Program Lock Bits and the Features
2 P U U MOVC instructions executed from external program memory are disabled
Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. Any other combination of the lock bits is not defined.
AUTOMOTIVE 87C51FA/FB/FC/FC-20 EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (TA e 21§Ct o2 7 §C; V CC e 5V g20%; V SS e 0V) ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13.0 V IPP Programming Supply Current 75 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48T CLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48T CLCL TGHDX Data Hold after PROG 48TCLCL TEHSH (Enable) High to V PP 48TCLCL TSHGL VPP Setup to PROG Low 10 ms TGHSL VPP Hold after PROG 10 ms TGLGH PROG Width 90 110 ms TAVQV Address to Data Valid 48T CLCL TELQV ENABLE Low to Data Valid 48T CLCL TEHQZ Data Float after ENABLE 0 48T CLCL TGHGL PROG High to PROG Low 10 ms EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 270961–21
AUTOMOTIVE 87C51FA/FB/FC/FC-20 DATA SHEET REVISION HISTORY The following are key differences between this data sheet and the -002 revision of the data sheet: 1. The data sheet has been revised from the 87C51FB/87C51FC to the 87C51FA/87C51FB/87C51FC/ 87C51FC-20 and includes the 20 MHz 87C51FC. 2. RST pin in Figure 3 has been changed to RESET pin. 3. Reference to Application Note AP-486 was added on page 5. 4. The I CC specification has been corrected in the D.C. Characteristics section. 5. The 20 MHz I CC max values have been added. 6. 20 MHz 87C51FC timings information were added to the External Program Memory Characteristics table. DATA SHEET REVISION HISTORY The following are key differences between this data sheet and the -001 version of the data sheet: 1. ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3. 2. Capacitor value for ceramic resonators deleted in Figure 4. 4. Replaced D0–D7 with P0 (EPROM programming and verification waveforms). 5. Combined the 87C51FB and 87C51FC data sheets. The following are the key differences between the previous 87C51FB data sheet versions and this new data sheet (rev-001): 1. The data sheet has been revised from a 83C51FB/87C51FB to an 87C51FB data sheet only. 2. The data sheet has been revised to specify AC and DC parameters to V CC e 5V g20% instead of V CC e 5V g10%. 3. The 87C51FB is now offered in a 3.5 MHz–20 MHz version. 4. The RST description has been modified to clarify the reset operation when the oscillator is not running. 5. Figure 4 (Oscillator Connections) has been changed for Ceramic Resonators. 6. A description of RFI Reduction Mode has been added. 7. V OH1,I IL,I TL and I CC DC Characteristics have been revised. 8. Note 1 of the DC Characteristics has been clarified. 9. The External Clock Drive diagram has been modified to include 16 MHz and 20 MHz device types. 10. The Float Waveforms diagram has been revised for greater clarity. 11. Table 4, EPROM Programming Modes, has been modified, included logic levels for P3.3 and three pro- gram lock bits. 12. The Encryption Array section now states that six address lines are used to select a byte from the Encryp- tion Array instead of five. 13. The I PP specification in the EPROM Programming and Verification Characteristics has been increased to 75 mA.