Microcontroller

TN8XC196JQ

Intel Corporation

COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER

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COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KR/KQ/JR/JQ—16 Kbytes of On-Chip OTPROM 80C196KR/KQ/JR/JQ—ROMiess @ High Performance CHMOS 16-Bit CPU @ High-Speed Peripheral Transaction m 16 MHz Operating Frequency tes Prog een Ti Up to 488 of r) s rammable 1 mer! s was Bytes of On-Chip Register C with P Je, C ‘i Standard and Quadrature Counting @ 256 Bytes of Additional RAM Inputs (Code or Data RAM) @ 10 High-Speed Capture/Compare (EPA) @ Register-Register Architecture Dedicated = Two High Speed Compare @ 8& Channel/10-Bit A/D with Sample/Hold Registers @ 37 Prioritized Interrupt Sources @ Two Flexible 16-Bit Timer/Counters @ Up to Seven 8-Bit (56) I/O Ports @ Quadrature Counting Inputs © Ful Duplex Sorted VO Port (ato) and @ Flexible 8-/16-Bit External Bus Port (S810) van Dedicated Baud Rate @ Programmable Bus (HOLD/HLDA) Generators @ 1.75 »s 16 x 16 Multiply @ Interprocessor Communication Siave @ 3 ps 32/16 Divide Port m Extended Temperature Available m Watchdog Timer @ 68-Pin and 52-Pin PLCC Packages |_Device | Pine/Package | OTPROM | Reg RAM | intemal Ram | 1/0 | EPA | sio | ssio | 4/0 | |ercroexn |esppicc | ek | siz | ase [se] to | v | y | 8 | jsrcreeia | szppicc | ia | see | 128 | 41 | 6 | vy | ¥ | 6 | [eocieexr [esppicc | o | siz | ae [se] |v] y |e | jsocrsexa|espricc | o | see | 128 | s6| to | v| ¥ | 8 | jeocisen | seppicc | o | si | 26 |[ai| 6 [vy] y¥ | 6 | jsocrsesa|szppicc | o | se | es [a] 6 | v{ v | ¢ | The 87C196KR/KQ/JR/JQ devices represent the 4th generation of MCS® 96 products implemented on Intel's advanced 1 micron process technology. These products are members of the 80C196 family of devices and the instruction set is the same as that of the 80C196KC. The 87C196JR is a 62-ead version of the 87C196KR device, while the 87C196KQ/JQ are memory scalars of the 87C196KR/JR. The MCS 96 microcontrolter family members are all high-performance microcontrollers with a 16-bit CPU. The 87C196KR is composed of the high-speed (16 MHz) core as well as the following peripherals: up to 16 Kbytes of on-chip EPROM, up to 512 bytes of Register RAM, 256 bytes of Code RAM, an eight-channel 10-bit analog 10 digital converter, an (8096 compatible) asynchronous/synchronous serial 1/O port, an additional synchro- nous serial [/O port, 10 modularized multiplexed capture and compare channels (called the Event Processor Array), @ sophisticated prioritized interrupt structure with the programmabie Peripheral Transaction Server

Additional register space is allocated for the EPA and can be windowed into the lower Register RAM area. Cations are the same for both options. See the prefix identification for extended temperature designators. Figure 1. Block Diagram

Reserved memory focations must contain OFFH unless noted.
Reserved SFR bit locations must contain OH unless noted.
WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may

8XC196KR/8XC196KG/8XC 196JR/8XC 196JQ intel. ity information is available in Intel's Components Quality and Reliability Handbook, Order Number 210997. Table 1. Prefix identification *T = Extended Temperature, no burn-in. Table 2. Thermal Characteristics 240800) for a description of intet’s thermal impedance test methodology.

Figure 2. Package Diagrams

Figure 2. Package Diagrams (Continued)

intel ° 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ PIN DESCRIPTIONS Main supply voltage (+ 5¥). Vss Digital circuit ground (OV). There are three Vss pins, all of which MUST be connected. Vrer Reference for the A/D converter (+ 5V). Vacr is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. Reference ground for the A/D converter. Must be held at nominally the same potential as Vgs. Vpp Programming voltage for the OTPROM parts. It should be + 12.5V for programming. Itis also the timing pin for the return from powerdown circuit. If this, function is not used, Vpp must be tied to Voc. ACHO-ACH7/PORTO | Analog inputs to the on-chip A/D converter. [AINC _———_| input to automatically increment the address when in Programming mode. ALE/ADV/P5.0 ‘Address Latch Enable or Address Valid output, as selected by CCR. Both pin options allow a latch to demultiplex the address/data bus. When the pin is ADV, it goes inactive (high) at the end of the bus cle When the pin is ALE, the address can be latched on the falling edge. ALE/ADV is active only during external memory accesses. Can be used as standard I/O when not used as ALE. BHE/WRH/P5.5 Byte High Enable or Write High output, as selected by the CCR. BHE = 0 selects the bank of memory that is connected to the high byte of the data bus. if the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is only valid during 16-bit external memory cycles. Can be used as standard I/O when not used as BHE/WRH. BREG/P2.3 Bus Request output activated when the bus controller has a pending external memary cycle, Gan be used as standard 1/0 when not used as BRE. BUSWIDTH/P5.7 Input for bus width selection. If CCR bit 1= 1 and CCR1 bit 2= 1, this pin dynamically controls the Bus width of the bus cycle in progress. if BUSWIDTH is low, an 8-bit cycle occurs. If BUSWIDTH is high, a 16-bit cycle occurs. Can be used as standard I/O when not used as BUSWIDTH. CLKOUT/P2.7 Output of the internal clock generator. The frequency is 12 the oscillator frequency. Ithas a 50% duty cycle. Can be used as standard |/O when not used as CLKOUT. CPVER Cumulative Program Verify output. Indicates when all EPROM locations program correctly. Input for memory select (External Access). EA = 1 causes memory accesses from locations 2000H to SFFFH to be directed to on-chip EPROM/ROM. EA~=0 causes all memory accesses to be directed to off-chip memory. EA= + 12.5V causes ‘execution to begin in the Programming Mode. EA is latched at reset. EPAO-7/PORT1 Event Processor Array pin for High Speed capture and compare. EPAO and EPA2 EPA8-9/P6.0-6.1 also function as T2CLK and T2DIR. Can be used as standard I/O when not used as. EPA or T2 clock functions. EXTINT/P2.2 ‘A positive transition on this pin causes a maskable interrupt vector through memory location 203CH. May be used as standard (/0 if not used as EXTINT. FLDA/P2.6 Bus Hold Acknowledge output indicating release of the bus. Can be used as standard I/O when not used as HLDA. FOLD /P2.5 Bus Hold input requesting control of the bus. Can be used as standard |/O when not used as . ADVANCE INFORMATION 4.215 M™§ 4826175 0144633 TOS

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° PIN DESCRIPTIONS (Continued) INST/P5.1 Output high during an external memory instruction fetch. INST is valid throughout the bus cycle. INST is low otherwise. Can be used as standard I/O when not used as INST. INTOUT/P2.4 interrupt output indicating that a pending interrupt requires use of the external bus. Can be used as standard 1/0 if net used as INTOUT, A positive transition causes a non-maskable interrupt vector through memory location 203EH. If not used, this pin should be tied to Vg. May be used by Intel Evaluation boards. Output that indicates when the device is currently programming itself. Not active during slave programming. [PALE __—_—_| Input tolatch the address during programming modes. PMODE.0-PMODE.3 | Programming mode select inputs. PORTO 8-bit high impedance input-only port. Also used as A/D converter inputs. Port 0 pins should not be left floating. These pins are also used as inputs by EPROM paris to select the Programming Mode. | @-bit bidirectional standard I/O por. All ofits pins are shared with the EPA. | PORT2 bit bidirectional standard I/O port. All of its pins are shared with other functions (TxD, FD, EXTINT, BREG, INTOUT. HOLD, HILDA, GLKOUN). PORT3 8-bit bidirectional standard I/O with open drain outputs. These pins are shared with | PORT4 the multiplexed address/data bus which uses strong internal pullups. | PORTS S-bitbidrectional standard /0 por. Alot its pins are shared with other functions | (ALE/ADV, INST, WR/WAL, RD, SLPINT, /WRH, READY, BUSWIDTH). PORTS bit bidirectional standard I/O port. All of its pins are shared with other functions (EPA8, EPAQ, TICLK, T1DIR, SCO, SD0, SC1, SD1). [PROG _—_| Programming mode enable input. Program Verify output. Goes high after a byte/word is programmed to indicate a successful operation. RD/P5.3 Read signal output to external memory. RD is low only during external memory reads. Can be used as standard I/O when not used as RD. READY/P5.6 Ready input to lengthen external memory cycles. If READY = 1, CPU operation continues in a normal manner. if READY = O with the appropriate timings, the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY = 1. Can be used as standard I/O when not used as READY. | Reset input to and output from the chip. Held low for at least 16 state times to reset the chip. The subsequent low to high transition resynchronizes CLKOUT and ‘commences a 10-state time sequence. Input high for normal operation. RESET has an internal pullup. RXD/P2.1 Receive data input pin for the Serial I/O port. Can be used as standard I/O if not used as RXD. Slave port chip select input pin. Can be used as standard I/O if not used as SLPCS. SLPINT/P5.4 Slave Port Interrupt Output pin. Can be used as standard 1/O when not used as SLPINT. ‘SSIO/P6.4-6.7 ‘Synchronous Serial I/O pins. SCO/SC1 serve as clock pins and SDO/SD1 are data (SCO, SD0, SC1, SD1) | pins. Can be used as standard 1/0 if not used for serial I/O. 4-216 ADVANCE INFORMATION MH 4826175 0144834 94, me

intel ° 8XC196KR/8XC196KQ/8XC 196JR/8XC196JQ PIN DESCRIPTIONS (Continued) TICLK/P6.2 | TIMERI Clock input. The timer increments or decrements on both positive and negative edges. Can be used as standard I/O when not used as TICLK. T1DIR/P6.3 | TIMER} Direction input. The timer increments when this pin is high and decrements when this pin is low. Can be used as standard I/O when not used as T1DIR. T2CLK/P1.0 | TIMER2 Clock input. The timer increments or decrements on both positive and negative ‘edges. Can be used as standard I/O when not used as T2CLK. T2DIR/P1.2 | TIMER2 Direction input. The timer increments when this pin is high and decrements when this pin is low. Can be used as standard I/O when not used as T2DIR. Transmit data output pins for the Serial I/O port. Can be used as standard I/O if not used as TXD. WR/WRL/P5.2 | Write and Write Low output to external memory. WR will go low for every external write. : ‘WAL will go low only for external writes where an even byte is being written. WA/WAL is active only during external memory writes. Can be used as standard |/O when not used as WAAWAL XTALI Input of the oscillator inverter and the internal clock generator. This pin should be used when using an external clock source. Output of the oscillator inverter. . ADVANCE INFORMATION 4217 MH 4826175 0144835 668

8XC196KR/8XC196KQ/8XC196JR/8XC196J0 intel . ELECTRICAL CHARACTERISTICS NOTICE: This data sheet contains information on ABSOLUTE MAXIMUM RATINGS** Products in the sampling and initial production phases of development. It is valid for the devices indicated in Ambient Temperature change without notice. Voltage from Vpp or EA to Maximum Ratings" may cause permanent damage “Operating Conditions” is not recommended and ex- Voltage from Any Other Pin tended exposure beyond the “Operating Conditions” This includes Vpp on ROM and CPU devices. (based on PACKAGE heat transfer limitations, not device power consumption) . OPERATING CONDITIONS | [ symect [Bescon wh we [te] [ta | Anion TorgorreunderSiesCommercalTenp [0 [+ | -c] [a | antion Tonperatire under Sie Extended erp. | —a | ves [-o] [vec | Die spoy vote dt amo | eso |v | | _Vaer | AnetogSuppiyvottage | 450 | 80 |v | [osc | OetaorFromeney a 8 NOTE: ANGND and Vgg should be nominally at the same potential. DC CHARACTERISTICS (Over Specified Operating Conditions)(9) [Symbot[ Parameter [win [typ'®)| max [Units Test Conditions Vi. Input Low Voltage -0.5V 03Vcc | Vv (All Pins) [van [nnthighVolags | o?ves | [ves sos] v |__| Vor Output Low Voltage 03 V_ | lop = 200 pats. 5) (Outputs Configured 0.45 V | lop = 32m as Push/Pull) 15 V_| lo. = 7.0mA Vou | Output High Voltage | Voc — 0.3 V_ | lon = —200 pa’s. 5,8) (Outputs Configured | Voc - 0.7 V_ | ton = -3.2mA as Push/Pull) Voc — 15 V_| lon = -7.0mA Vouz2 | OutputHigh Voltage | Voc — 1V V_ [lon = —15patt.7) in RESET Input Leakage Current 210 | pA | Ves < Vin < Voc — 0.3V@) (Std. inputs) Input Leakage Current Fa] +3 pA | Vg < Vin < Veer (Port O—A/D Inputs) Ih Input High Current +175 | pA | Vss < Vin < Voc — 0.30010) (NM) 4-218 ADVANCE INFORMATION MB 4426175 O14483b 714

intel ° 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ DC CHARACTERISTICS (Over Specified Operating Conditions)(®) (Continued) [ symbot | ___ Parameter | in | Typ'®) | Max | Unite | Test Conditions lec Voc Supply Current 75 | mA | XTAL1 = 16 MHz, Voc = Vpp = Vrer = 5.5V (While Device in Reset) A/D Reference Supply Current ‘pte —_| Idle Mode Current XTAL1 = 16 MHz, Voc = Vep = Vacr = 5.5V Powerdown Mode Voc = Vpp = Vaer = 5.5V fre | Se |_| = [reo] Reset Pulp Resistor jex | fexfo fo Cy Pin Capacitance pF | Fregr = 1.0 MHz (Any Pin to Vgs) LRweu [Weak Pulup Resistance Approx) | | 150K | | a [i NOTES: 4. All BD (Bidirectional) pins except INST and CLKOUT. 8D pins include Portt, Port2, Port3, Porté, Port5 (as @ port), and Porté. 2. Standard Input pins include XTAL1, EA, RESET, and Port 1/2/3/4/5/6 when setup as inputs. 3. All Bidirectional 1/O pins when configured as Outputs (Push/Pull). 4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum io. /lox currents per pin will be characterized and published at a lator dato. 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and vi = Veo = 5.0V. 7, Violating these specifications in reset may cause the device to enter test modes (P54 and P2.6). 8. This specification applies to P3/4 only when used as an address bus supplying the address. 9. All voltages are referenced relative to Vgs. When used, Vig refers to the device pin. 10. Worst case is at upper limit of test conditions. ‘cc vs Frequency 80 wax i ee ee a bes sop PT pice om of i 30 + ale MAX a en ee a, oe _ Ee | . aur tomnz 1eune ar0012-4 NOTES: . loc Max = 3.88 x FREQ + 13.43 ; lige Max = 1.65 X FREQ + 22 ADVANCE INFORMATION we 4826175 0144837 650 Mm 4219

REESE'S :’ST'’S “=i intel ® 8XC196KR/8XC196KQ/8XC196UR/8XC196JQ AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 87C196KR/KQ/JR/JQ will meet these specifications. Oseilator Peri 17 Fea [ees | 250 [| XTALtFightoCLKOUTHghortow |, 20 | 10) rat _| CLKOUT Peed CLKOUT Falling Edge to ALE Rising [| -10 [8 | ns | Tuca ALE/ADV Falling Edge 15 to CLKOUT Rising ALE/ADY Oya Tino | atesc | ALE/ADY High Peto [Toso=10 | Tosoti0 [ne | TaviL Address Setup to ALE/ADV Tosc—15 Falling Edge Tua ‘Address Hold after ALE/ADV Toso—40 Falling Edge Tue ‘ALE/ADV Falling Edge to Toso~30 RD Falling Edge AD low ioCuKouTFaiingeage | a | a | wm | 7D Low Perod ee TRHLH RD Rising Edge to Tosc Tosct 25 ALE/ADV Rising Edge I Low to Adcress Float ee ee TuLWe ALE/ADV Falling Edge Tosc~10 to WR Falling Edge Touwe CLKOUT Low to WR Falling Edge Date Stable to WA ising Ego | Toso-@ | SiC | CLKOUTHigh WR Risingage | -0 | 18 | ns | [Tw | WAtowPoios «| Toso | Sit Data Hol ator WARIng EGG | _Toso=25_ | _——~id| rs | TWHLH WR Rising Edge to ALE/ADV Tosc-10 Tosc+ 15 Rising Edge ADE-1SHold ator WA Rising ago | Toso-2oe |_| ns | BHE, INST Hold ater FD Rising E2go_| Toso-10 | +e _| ADS-15HoWaterFOAsing Ege | Tosca | __——*dY—os | BHE Vado ALE Fang E290 | Toso-15 | | ra NOTES: 1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 Togc < n, where n = number of wait states. 6. Does not apply to JR/JQ. | ADVANCE INFORMATION 4-221 EB 4826175 0144839 423

8XC196KR/8XC196KQ/8XC196UR/8XC196JQ intel ° System Bus Timing Tose xvaut Teter: Tawen Tenet eukour Teun -effe-Tuce Tua ALE TULL Taye bus >)»: Tine Tue Twow TwHLH we TwHox pus a ADORESS OUT Feo BRE, mst a, = : Xe od TwHax OF TrHax ADB-15 270912-6 Buswidth Timings Tose XTALI | Tove TxHoH Tone. cuKour Tut Tue | ALE ‘ | : LL aus EE D>)» READY | Tua Tavry: Teusx sv) suswioTH 270912-6 1 4.222 ADVANCE INFORMATION | WH 4826475 OL44840 145

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° EXTERNAL CLOCK DRIVE OscilatorFrequency | 4a | tee Oscillator Period (Toso) | 625 | a0 | ns High Time 0.35 Tose ee | tan | Risotime Pts Fall Time ee EXTERNAL CLOCK DRIVE WAVEFORMS Tacx Truxt Twat O.7Vec#0.5¥ AO WVece0BV Tax O.7VeqrOBV Tru. 270012-8 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS ¢ Voc xtAL ane Vss 1 = 8XC196KR/KQ/JR/JO cuock input —f >O writ \\ waz Seok driver 8XC198KR/KO/ 8/10 ° 10 connect =f XTAL2 Quartz Crystat 270912-16 27081217 *Required i TTL devor used NOTE: Not needed if CMOS dvr is used. Koop oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and Vgs. When using quartz crystals, typically C1 ~ 22 pF and C2 = 22 pF. When using ceramic resonators, consult manu- facturer for recommended circuitry.

4.224 ADVANCE INFORMATION

intel . 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS seve ourpurs Veoapte.t5¥ Vour0.18¥ 5. TMING REFERENCE, oo Aono 90. easy 270012-9 270912-10 NOTE: NOTE: ‘AC Testing Inputs are driven at 3.5V for a logic "1" and For Timing Purposes a Port Pin is no longer floating 0.45V for a logic “0". Timing measurements are made when a 150 mV change from Load Voltage Occurs and at 2.0V for a logic 1" and 0.8V for logic “O". Begins to Float when a 150 mV change from the Load- ing Vou/Vox Level occurs loy/lon < 15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by “T” for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: Signals: H— High A— Address L— ALE/ADV L—Low 8— BHE Q— Data Out V— Valid BR— BREO R—RD X— No Longer Valid —CLKOUT w— WR/WRH/WAT Z— Floating D— DATA X— XTAL1 G— Buswidth Y— READY H— HOLD HA— ALDA AC CHARACTERISTICS—SERIAL PORT—SHIFT REGISTER MODE (MODE 0) SERIAL PORT TIMING—SHIFT REGISTER MODE (Over Specified Operating Conditions) Test Conditions: Load Capacitance = 100 pF Serial Port Clock Period | etosc | | ns | Serial Port Clock Faling Edge to Rising Edge [/4Tosc-50 | 4Toso+s0| ns | Output Data Setup to Clock Rising Edge | stoso | | ns | Output Data Hold ater Clock Rising Edge | 2Toso~50 | | ns | Next Output Data Valid attr Clock Rising Edge | | 2 Toso+ 50] ns_| Input Data Hold after Clock Rising Edge po fs | Last Clock Rising to Output Float ee ADVANCE INFORMATION 4-225 WB 4826175 0144843 954 mw

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE (MODE 0) SERIAL PORT WAVEFORM—SHIFT REGISTER MODE Foun aes es le ees ee ee ee ee Torn] [+ Tew Tay fl fe Tovar Toor fe co) XFS FX XX EXT Town | Tox Le CD GD TT DCD ND DDC) ND TD NTT, 270812-14 ATOD A/D CONVERTER SPECIFICATION The speed of the A/D converter in the 10-bit or 8-bit After a conversion is started, the device is placed in modes can be adjusted by setting the AD_TIME the IDLE mode until the conversion is complete. special function register to the appropriate value. —_Testing is performed at Vagr = 5.12V. The AD_TIME register only programs the speed at which the conversions are performed, not the speed There is an AD_TEST register that allows for con- it can convert correctly. version on ANGND and Vper as well as zero offset adjustment. The Absolute Error listed is WITHOUT The converter is ratiometric, so absolute accuracy is doing any adjustments. dependent on the accuracy and stability of Vaer. 4-226 ADVANGE INFORMATION Mi 4826175 o144844 890 Me

intel ° 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ 10-BIT A/D OPERATING CONDITIONS() [-Symbor [Description Tin [max | Unite | Ambiont Temperature CommercialTemp. | 0 | +70 |e Ambient Temperature Extended Temp. | 40 | +85 | °C Digital Supply Voltage [sso [sso |v | |_Vaer |" Analog Supply vonage | aso | sso |v | [tow | Sanpietine SSCs to |_Toonv | Conversiontime | tes [tas | nse) | L_Fosc | OscitatorFrequency | # | te NOTES: 1. ANGND and Vsg should nominally be at the same potential. 2. VaeF must not exceed Voc by more than +0.5V. 3. The value of AD__TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) [Parameter [Typical [| wn | Max Unity | Resolution 1024 Level

10 Bits

| AbsouteEnor TT Tt tes | | FulScaleEror | oasz0s | TT tse | | ZeroOfisetEnor | oaszos | TT tse | |_Non-tineanty | tote0 [Te tsas | |_DitferentialNon-Linearty [| > 05 [+05 | tses | | Grannetto-ChannetMatching [ =01 [oT et tsa | Repeatability es Temperature Coefficients: Offset 0.009 LsB/c Fullscale 0.009 LsB/C Differential Non-Linearity 0,009 LsB/C [onisoaion | CC [_Feeatvrougn S| CSdC Voc Power SupyRejecion [eo | sd SSSSCSC~d:C | |" iputSeres Resistance [+t od] SK Ca Vollage on Analog nputin || _ANGNO=08 | Verto5 |v | [samping Capacior | eT CCidC BC input Leekage eS ES NOTES: *An “LSB”, as used here, has a value of approximately 5 mV. (See Embedded Microcontroliers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25°C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make Guaranteed. 4, Resistance from device pin, through internal multiplexer, to sample capacitor. ADVANCE INFORMATION 4227 MH 4826175 Ol4484s 727 Mm

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° 8-BIT A/D OPERATING CONDITIONS(1) | Sympor [Description Twin | Max | Unite | Ambient Temperature Commercial Temp. | 0 | +70 |e Ambiont Temperature Extended Temp. | 40 | +05 |e _| Digital Supply Volage | aso [550 | ov | Analog Supply Voltage [| aso | ssom@ |v | Sample Time p20 JT we | |_Toow | Cowersiontine | t65 | 95 | pst | |_Fosc | Oseitator Frequency [4 | te Tee | NOTES: 1. ANGND and Vss should nominally be at the same potential. 2. Vater must not exceed Vcc by more than +0.5V. 3. The value of AD__TIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) The 8-bit mode trades off resolution for a faster conversion time. The AD__TIME register must be used when performing an 8-bit conversion. | [Parameter | typi) [Minimum [Maximum [uniter [Notes | Resolution 256 Levels

8 Bits ;

| Absouteenor | CT Tee ses [| Full Scale Error [tos [tse | Zeroorsetenor | eos [OT tses | Noninearty TT te ses [| Differential Non-LineartyEror | | >t [ta sas || Channelto-Channel Matching | [Tet tas || | Repose Ts Temperature Coefficients: Offset 0.003 LsB/°c Full Scale 0.003 LsB/°c Differential Non-Linearity 0.003 usB/°c Feedthrough [| =o [Owe VecPowerSupplyRejection | -60 | | | ao || , Input Series Resistance Po Tso ek | Voltage on Analog nputin | | ANGNO-05 | Var+os |v |_| Sampling Capacitor es DC input Leakage [fs ed NOTES: *An “LSB”, as used here, has a value of approximately 20 mV. 1. Typical values are expacted for most devices at 25°C. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make Guaranteed, 4. Resistance from device pin, through interna! multiplexer, to sample capacitor. 4-228 = ADVANCE INFORMATION MM 4826175 O14484b bb3

intel ° 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ OTPROM PROGRAMMING OPERATING CONDITIONS DURING PROGRAMMING(3) [symbot | __—Deserpton | im [Max [Unie | [ta | AnbionTonperue ring Poganning [2 [9 | 0 _| [ves | Si Votape ung Pogamnirg | as [ss | wi [vner | Reference Sup Votage avng Progamming | as [ss | wiv | [ve | Progamming atage | teas | vers | ve i = sremesa= Te [To fo | Slave Mode Programming = [amie Le Do To Run-Time Programming NOTES: 1. Voc and Vaer should nominally be at the same voltage during programming. 2. Vp and Vea must never exceed the maximum specification, or the device may be damaged. 3. Vgs and ANGND should nominally be at the same potential (OV). AC OTPROM PROGRAMMING CHARACTERISTICS [Symbot | ___Dewsnpon | ina unte| [tue | aaoesenptine oP tose | [otc | ates ron Tine [a0 Toe | [tom | oatnseuptine i 0 | i Toso | [tape | oad tine anf Toso [ran PATE Pusewaan Po || Toee | a [ue | PRE Hgh PROG Low [ew [tose | [Tout PROG Hghionet PATE Lew [20 [| Toso | [Tro [ Wo ounp Honing || | tose | [To | PROG Hohe Nen RGB Low [| | Tow | [Toe | PRE HahioPROG Low [em | Tose | [tru | PROG Low toworscunpvaid [| 50 | Tose _| [tear | RESET ign Fre PACELow [|| Tose | [tru | FROG HehioACLow fo | Toe] [tum | aCe wim few [Tose | [tae | PveR Heder sNELow [>| | Toso | [tan | AIC Lowio PROG [ro |—* Toso | [tron | PROG eno pvERvaRe [| a0 Toso | NOTE: 1. This specification is for the word dump mode. For programming pulses use 100 ps. ADVANCE INFORMATION 4-229 M@ 4826175 O144aur STT

8XC196KR/8XC 196KQ/8XC196JR/8XC 196JQ intel ° OC OTPROM PROGRAMMING CHARACTERISTICS [__symbot [Parameter |= Min. =| Max | Unite | Lt | VepProgramming Supply Curent [| =| ~—'100~=S«|=SsmA CO NOTE: Do not apply Vpp until Voc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. OTPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE atag Tavee Tove R- nn «[ ooness/comuano_)> Tome | Tax Tnx PALE PROG P22 er \\Lvao_/ | Tun 270912-11 | SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT | Tyo Troy Tewox Tetpy Tpwox PACE PROG . 72.2 | Ture, Tow Tiwe 4-230 ADVANGE INFORMATION MH 4826175 O14464s 3b

intel ° 8XC196KR/8XC196KQ/8XC 196JR/8XC196JQ SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT wef a P21 Thun Tun = " n Tava Tum rd rae Towa 270912-13 ; 87C196KR/87C196JR ERRATA 3, P2.7 (CLKOUT) " 1. lone Port 2.7 (CLKOUT) does not operate in open Current devices do not méet the test condition Grain mode. . for Von2 of —15 4A. Instead the devices are 4. Current versions of the 8XC196KQ/JQ are fabri 4 guaranteed to source a minimum of —6 pA. cated with 16K of internal OTPROM, 512 bytes of register RAM, and 256 bytes of internal RAM. The memory map of the 8XC196KQ/JQ is identi- 87C196KR/87C196JR DESIGN cal to re ears ore wot tested yoo! tied one memory ns are NK should ni CONSIDERATIONS be used. Intel may disable this extra memory on 1. EPA Timers future versions of the 8XC196KQ/JQ. Any soft- A snc/ writ ies on reading or writing these loca- Special care must be taken when resetting/writ- ware that rel rn : ing the EPA timers. This is more of a software tions may not function correctly on future devic- technique than a device errata. For example: 6. The EPA timers do not generate a ‘time valid” ‘Two steps the user should always incorporate to signal when the counter is either reset or writ- insure future compatibility are: ten. This means that if a compare event is pro- A) The program must contain a jump to a loca- grammed in the EPA/Compare channel for a tion greater than 16K before the 12K bounda- value of “OOOOH” (when reset) or equal to a 1y is reached. This is necessary only if greater written value, the compared event will NOT hap- than 12K of program memory is required and pen. However, if the timers are allowed to incre- portions of the program executes from inter- ment/decrement to that value, that compare nal OTPROM. event WILL occur. 8) Use program memory from 12K to 16K only if . The user is not allowed to modify the P6_REG. from 180H to 1FFH or from 480H to 4FFH. register when these pins are configured as Spe- | : cial Function P6_MODE.x = 1). During sott- | ware manipulation of these registers, it is a good practice to first change the P6__MODE register, then modify the P6_REG register when switch- : ing from SF to LSIO. | ADVANCE INFORMATION 4-231 MH 4826175 01448495 372

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° S2-LEAD DEVICES © the NM vector ‘at locaton 209¢h vector fo a e NMI vector at location vector to a Intel offers a 52-lead version of the 87C196KR de- Return instruction. This is for glitch safety pro- vice: the 87C196JR and 87C196JQ devices. tection only. Itis important to point out some functionality difer. %) Autertrogramming Made. The S@iead tovce ‘ences because of future devices or to remain soft- during auto-programming. ware consistent with the 68-lead device. Because of ° the absence of pins on the 52-lead device some _(5) EPA4 through EPA7. Since the JR and JQ de- functions are not supported. vices use the KR silicon, these functions are in the device, just not bonded out. A programmer s2 sted Functions: ‘can use these as compare only channels or for prenmynescaciy phonies other functions like software timer, start and INST Pin Functionality A/D, or reset timers. SLPINT Pin Support (6) Slave Port Support. The Slave port can still be HLD/HLDA Functionality used on the 52-lead devices. The only function External Clocking/Direction of Timert removed is the SLPINT output function. The following is a list of recommended practices PANE vpdated and toad: She womens when using the 52-lead device: should not use the corresponding bits associat- (1) External Memory. Use an 8-bit bus mode only. ed with the removed port pins to conditionally There is neither a WAH or BUSWIDTH pin. The branch in software. Treat these bits as RE- bus cannot dynamically switch from 8- to 16-bit SERVED. or vice Niele ii Son nes to an 8-bit only Aion, these port pins should be setup in- mode, inction only. ternally by software as : (2) Walt State Control. Use the CCB bytes to con- ritten to Px “4” of "0" figure the maximum number of wait states. If the 1, Written to PxREG 98 “1" or "0", READY pin is selected to be a system function, 2. Configured as Push/Pull, Px_DIR as "0". the device wil lockup waiting for READY. Ifthe 3. Configured as LSIO. READY pin is configured as LSIO (default after is confi i etfecth i RESET), the internal logic will receive a logic ane we ar on OO Ae ones Oe “0” level and insert the CCB defined number of Open Diz ouput °?”, or as an trout pin wait states in the bus cycle. DON'T USE IRC = This device is CMOS. | 4-232 = ADVANGE INFORMATION mm 4826175 o144aso O84

intel ° 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ REVISION HISTORY 16. Changed External Clock min/max, high/low times from percentage to ratio of Togc This data sheet (270912-003) supercedes 270912- 17. Removed NMI from standard inputs (Note 2 un- 002 and is valid for devices with a "C" at the end of der DC Characteristics) changed as now dots Inoriton becomes ave, 18 Removed Vo. spec able. Verify that you have the latest version before 19. Removed Tciav finalizing a design or ordering devices. 20. Added JQ/KQ design consideration {Removed the folowing errata: sheet 270912-002 supercedes 270912-001 Slave Programming Mode ad's vald for devices with an"A" at the end of the EPA_MASK1/EPA_PEND1 topside tracking number. BMOVI 1. Removed: PTS and Other Interrupts CPU features descriptions Serial Port Framing Error Peripheral features descriptions Remap Mode on EPAS ‘SFR Operation (placed in Quick Reference) A/D Abort ‘SFR Maps (placed in Quick Reference) PTS/NMI Conflict SFR Bit Maps (placed in Quick Reference) Data Output Register Cleared hi. in DC Characteristics Divide Error during HOLD/READY TouHaL Max and Tota Max SIO Mode 0 Incorrect Sample and Convert time table from EPAIPV Multiplied by Two B-bit A/D (These were fixed on the C-step) 2. Added: 2. Moved the following from Errata to Design Con- Express options siderations: Bullets on front page EPA Timers Memory Map Port 6.4, 6.5, 6.6, 6.7 (and reworded) Process Information 2.7 (CLKOUT) Prefix Identification Oscillator Noise Sensitivity Thermal Characteristics 3. Added New Errata: Programming functions to pin-out and pin de- loa (also existed on A-step) scriptions 4, Added SLPCS to Package Diagrams and Pin De- Ambient Temperature under Bias to Absolute seriptions Maximum Ratings 5. Added Tayi Note relating to Power Dissipation in Absolute 6. Added Iiy for NMI Maximum Rating 7. Added notes to AC Characteristics identifying Notes 8 and 9 to DC Characteristics specifications that do not apply to JR/JQ Tovey to AC Characteristics 8. Changed Touiy from —5 ns to —10 ns under Title to Buswidth timing diagram HOLD/HLDA Timings TyLyH to Buswidth timing diagram 9, Changed THycH from 55 ns to 65 ns Hold latency spec 10. Changed TazHa from 10 ns to 25 ns External Crystal Connection diagram 11. Changed TazuaL from 10 ns to 25 ns External Clock Connection diagram 12. Changed loc (max) from 70 mA to 75 mA 10-bit A/D Operating Conditions Table 13. wasex ‘cc Joey (3.88 x Freq + 8.43) Title to 10-bit and 8-bit mode A/D Characteristics i req “) Voltage on Analog input Pin specification 14. onenaee Voue test point from —50 pA to Sampling Capacitor typical value 15. Changed Note 1 in DC parameters Note 4 to 10-bit and 8-bit A/D Specifications 8-bit A/D Operating Conditions Table 4 4-233 ADVANGE INFORMATION MH 4426175 014485) T20

8XC196KR/8XC196KQ/8XC196JR/8XC196JQ intel ° Ot tsolation, Feedthrough, Voc Power Supply Format of symbols in AC Characteristics Rejection, Input Series Resistance, Voltage on in Analog Input Pin, Sampling Capacitor and DC in- Texch t© Teun in System Bus Timing diagram put Leakage to 6-bit A/D specications Txt Max from 286 ns to 250 ns Notes 1, 2 and 3 to EPROM Programming Condi- Txtxx from Tosco — 44 ns to 35% /65% tions Txuxx from Tosc — 44 ns to 35%/65% New Errata (Items 10 to 16) Tx.xH from Togo — 50 ns to 10 ns 3. Changed: Txtxi ftom Togc — 50 ns to 10 ns Title of data sheet from “8XC196KR/KQ/JR/JQ AC Testing Input, Output Waveform 16-BIT HIGH PERFORMANCE CHMOS MICRO- A ‘istic CONTROLLER” to “8XC196KR/KQ/JR/JQ eee cation naracterstics and COMMERCIAL/EXPRESS CHMOS MICROCON- TROLLER™ OC Input Leakage from 1 pA to +3 nA in A/D Several bullets on cover sheet Specifications. Register RAM numbers in table on front to Dissipation from 0.5W to 1.0W. mech device page Wording in Float Waveform from 100 mV to Operating conditions to tabular format 180 mV. Note 1 in OG Characteristics to include Ports 9 eee erie reractraica to Operat- 0 to Vgg for iy; and i), in DC Characteristics Data sheet (270912-001) is valid for devices with an “A” at the end of the topside tracking number. This is the first version of the data sheet. 4-234 ADVANGE INFORMATION MH 4826175 0144852 Ib? |

Product Information

TN8XC196JQ specifications and overview.

Summary

COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER

Description

COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER

Source title TN8XC196JQ Datasheet(PDF) - Intel Corporation

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