80C251SB16 INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 36
Technical content
COPYRIGHT © INTEL CORPORATION, 1996 May 1996 Order Number: 272783-003 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations. ■ Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS® 51 ■ Pin Compatible with 44-pin PLCC and 40- pin PDIP MCS 51 Sockets ■ Register-based MCS® 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, or Double Words ■ Enriched MCS 51 Instruction Set — 16-bit and 32-bit Arithmetic and Logic Instructions — Compare and Conditional Jump Instructions — Expanded Set of Move Instructions ■ Linear Addressing ■ 256-Kbyte Expanded External Code/Data Memory Space ■ ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
■ 16-bit Internal Code Fetch ■ 64-Kbyte Extended Stack Space ■ On-chip Data RAM Options: 1-Kbyte (SA/SB) or 512-Byte (SP/SQ) ■ 8-bit, 2-clock External Code Fetch in Page Mode ■ Fast MCS 251 Instruction Pipeline ■ User-selectable Configurations: — External Wait States (0-3 wait states) — Address Range & Memory Mapping — Page Mode ■ 32 Programmable I/O Lines ■ Seven Maskable Interrupt Sources with Four Programmable Priority Levels ■ Three Flexible 16-bit Timer/counters ■ Hardware Watchdog Timer ■ Programmable Counter Array — High-speed Output — Compare/Capture Operation — Pulse Width Modulator — Watchdog Timer ■ Programmable Serial I/O Port — Framing Error Detection — Automatic Address Recognition ■ High-performance CHMOS T echnology ■ Static Standby to 16-MHz Operation ■ Complete System Development Support — Compatible with Existing Tools — New MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE ■ Package Options (PDIP , PLCC, and Ceramic DIP)
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P .O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
512 Bytes
1024 Bytes
8 Kbytes
16 Kbytes
4 PRELIMINARY
1.0 NOMENCLATURE
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature Table 1. Description of Product Nomenclature
7 User programmable OTPROM/EPROM
Table 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ family nomenclature. Table 3 lists the 8XC251SA/SB/SP/SQ packages. Table 3. Package Information Table 2. Proliferation Options
6 PRELIMINARY
2.0 PINOUT
Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package
Figure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages
8 PRELIMINARY
Table 4. 8XC251SA/SB/SP/SQ Pin Assignment
1 VSS 1 23 VSS 2
Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category
10 PRELIMINARY
3.0 SIGNALS
Table 6. Signal Descriptions Microcontroller User’s Manual). See also RD# and PSEN#. compare mode and PCA PWM mode. ROM/OTPROM/EPROM, EA# must be strapped to ground. set by a low level on INT1:0#. programming the on-chip OTPROM.
Embedded Microcontroller User’s Manual). ing a capacitor between this pin and VCC . returns the chip to normal operation. 0 and receives data in serial I/O modes 1, 2, and 3. counter, a falling edge on the T1:0 pin increments the count. and transmits serial data in serial I/O modes 1, 2, and 3. Table 6. Signal Descriptions (Continued)
12 PRELIMINARY
applied to this pin for programming the on-chip OTPROM/EPROM. (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. a period of one-half the oscillator frequency. is the clock source for internal timing. an external oscillator is used, leave XTAL2 unconnected.
Table 7. Memory Signal Selections (RD1:0)
14 PRELIMINARY
4.0 ADDRESS MAP
Table 8. 8XC251SA/SB/SP/SQ Address Map
- 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
- The special function registers (SFRs) and the register file have separate internal address spaces.
- Data in this area is accessible by indirect addressing only.
- Devices reset into internal or external starting locations depending on the state of EA# and configura-
Embedded Microcontroller User’s Manual.
- The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map
- This reserved area returns indeterminate values.
- Data is accessible by direct and indirect addressing.
- Data is accessible by direct, indirect, and bit addressing.
- Data is accessible by direct, indirect, and register addressing.
- Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.0 ELECTRICAL CHARACTERISTICS
OPERATING CONDITIONS † TA (Ambient T emperature Under Bias): NOTE Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. NOTICE: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. † WARNING : Stressing the device beyond the “Absolute Maximum Ratings” may cause perma- nent damage. These are stress ratings only. Oper- ation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
16 PRELIMINARY
Parameter values apply to all devices unless otherwise indicated. Table 9. DC Characteristics at VCC = 4.5 – 5.5 V
- Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
to sink current greater than the listed test conditions.
- Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
- Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
- Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)
- Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
to sink current greater than the listed test conditions.
- Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
- Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
- Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
18 PRELIMINARY
Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V Figure 6. ICC vs. Frequency (Mhz) All other 8XC251SA/SB/SP/SQ pins are unconnected.
5.2 Definition of AC Symbols
Test Conditions: Capacitive load on all pins = 50 pF. Table 10. AC Timing Symbol Definitions affected by a PSEN#/RD#/WR# wait state. Table 11. AC Characteristics
- Specifications for PSEN# are identical to those for RD#.
- In the formula, M=Number of wait states (0 or 1) for ALE.
- In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
- “Typical” specifications are untested and not guaranteed.
20 PRELIMINARY
37.5 T OSC – 25
Table 11. AC Characteristics (Continued)
- Specifications for PSEN# are identical to those for RD#.
- In the formula, M=Number of wait states (0 or 1) for ALE.
- In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
- “Typical” specifications are untested and not guaranteed.
- Specifications for PSEN# are identical to those for RD#.
- In the formula, M=Number of wait states (0 or 1) for ALE.
- In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.
- “Typical” specifications are untested and not guaranteed.
22 PRELIMINARY
5.3.1 EXTERNAL BUS CYCLES, NONPAGE MODE
Figure 7. External Bus Cycle: Code Fetch (Nonpage Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 8. External Bus Cycle: Data Read (Nonpage Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
24 PRELIMINARY
Figure 9. External Bus Cycle: Data Write (Nonpage Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
5.3.2 EXTERNAL BUS CYCLES, PAGE MODE
Figure 10. External Bus Cycle: Code Fetch (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics. state (2TOSC ); a page miss requires two states (4TOSC ). ††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
26 PRELIMINARY
Figure 11. External Bus Cycle: Data Read (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 12. External Bus Cycle: Data Write (Page Mode) † The value of this parameter depends on wait states. See the table of AC characteristics.
28 PRELIMINARY
5.3.3 DEFINITION OF REAL-TIME WAIT SYMBOLS
5.3.4 EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES
Figure 13. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode) Table 12. Real-time Wait Timing Symbol Definitions
30 PRELIMINARY
Figure 16. External Bus Cycle: Data Write (Page Mode) Table 13. Real-time Wait AC Timing
5.4 AC Characteristics — Serial Port, Shift Register Mode
Figure 17. Serial Port Waveform — Shift Register Mode
5.5 External Clock Drive
Table 14. Serial Port Timing — Shift Register Mode Table 15. External Clock Drive †TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
32 PRELIMINARY
Figure 18. External Clock Drive Waveforms Figure 19. AC Testing Input, Output Waveforms Figure 20. Float Waveforms
0.7 VCC
a min of VIH for a logic 1 and VOL for a logic 0.
33 PRELIMINARY
6.0 THERMAL CHARACTERISTICS
thermal impedance test methodology. Table 16. Thermal Characteristics
7.0 NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION
7.1 Definition of Nonvolatile Memory Symbols
Table 17. Nonvolatile Memory Timing Symbol Definitions
34 PRELIMINARY
7.2 Programming and Verification Timing for Nonvolatile Memory
Figure 21. Timing for Programming and Verification of Nonvolatile Memory Table 18. Nonvolatile Memory Programming and Verification Characteristics at
8.0 ERRATA
There are no known errata for this product.
9.0 REVISION HISTORY
- Real-time wait state operation is described in
- Memory map reserved locations are newly
- AC Characteristics have been updated. The
- DC Characteristics have been updated. The
typical, IDL max, ICC typical, and ICC max.
- An I CC vs. Frequency graph is included.
- Process information is no longer contained in
- The section “Programming and Verifying Non-
memory have been retained in this datasheet.
- Signature Byte information has been deleted.
Microcontroller User’s Manual.
- Sections in the datasheet are numbered.
- New sections have been created to provide
- Proliferation Options and Package Options are
in the Nomenclature section.
- T emperature range is contained in the Electri-
- Bus timing diagrams have been organized into
- A corrected PDIP diagram appears on page 7.
- A corrected formula to calculate T
- The RD#/PSEN# waveform is changed in Fig-