80C196KT INTEL | Alldatasheet
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e 8XC196KT COMMERCIAL CHMOS MICROCONTROLLER @ High Performance CHMOS 16-Bit CPU ® Oscillator Fail Detection Circuitry m@ Up to 32 Kbytes of On-Chip EPROM @ High Speed Peripheral Transaction m Up to 1 Kbyte of On-Chip Register RAM Server (PTS) m Up to 512 Bytes of Additional RAM m1 Two Dedicated 16-Bit High-Speed (Internal RAM) Compare Registers @ Register-Register Architecture @ 10 High Speed Capture/Compare (EPA) m@ 8 Channel/10-Bit A/D with Sample/Hold © Port (3500) Synchronous Serial 1/0 7 y eee anno oneee m Two Flexible 16-Bit Timer/Counters
7 Ful + seval + a @ Quadrature Counting Inputs
m Full Duplex ° & Flexible 8-/16-Bit External Bus mw Dedicated Baud Rate Generator (Programmable) @ Interprocessor Communication Slave @ Programmable Bus (HOLD/HLDA) Port a 1.75 ys 16 x 16 Multiply @ Selectable Bus Timing Modes for 3 of Flexible Interfacing m 3 1s 32/16 Divide @ 68-Pin PLCC Package |_Device | Pina/Package | EPROM | Reg RAM | Code RAM | Address Space | 1/0 | EPA | A/D | [excise |earinpoc | sax | ik | siz | anos | s6| 10 | 2 | X = 7 EPROM Device X = 0 ROMiess Device The 8XC196KT 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller farnily. The 8XC196KT Is an enhanced BXC196KR device with 1000 byte register RAM, 512 bytes internal RAM, 16 MHz operation and an optional 32 Kbytes of ROM/EPROM. Intel's CHMOS II-E process provides a high Performance processor along with low power consumption. The 8XC196KT has a maximum guaranteed frequency of 16 MHz. Ten high-speed capture/compare modules are provided. As capture modules event times with 250 ns resolu- tion can be recorded and generate interrupts. As compare modules events such as toggling of a port pin, starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be based on the timer or up/down counter.
intel. 8XC196KT PROCESS INFORMATION 8XC196KT Memory Map This device is manufactured on PX29.5, a CHMOS Fa | ¢ Koes Enteral Marr IIHE process. Additional process and reliability infor- mation is available in Intel's Components Quality . hamster [Ly oe| , Table 1, Thermal Characteristics Reserved Memory (internal EPROM Package 2000H | or External Memory)(*, 5) Type Ept | Memory Manod Spec Furcton [roc | sesrcrw [veer | EEO Reet en All thermal impedance data is approximate for static | 1FOOH | Registers (SFA’s)(* air conditions at 1W of power dissipation. Values will 1EFFH change depending on operation conditions and ap- 0600H plication. See the Intel Packaging Handbook (Order Number 240800) for a description of intel’s thermal OSFFH | Internal Code or Data RAM (Address impedance test methodology. 0400H | with Indirect or Indexed Modes) OSFFH Upper Register File (Address with Indirect or Register RAM / i dexed Modes or through 0100H Windows)(1) OOFFH |p Lower Register File TRAM (Address with Direct, 0017H , Indirect, or indexed 0000H CPU SFR's Modes)(. 3) NOTES: 1, Code executed in locations 0000H to O3FFH will be forced external. 2. Reserved memory locations must contain OFFH unless noted. 3. Reserved SFR bit locations must be written with 0. 4, Refer to BXC196KT for SFR descriptions. 5. WARNING: The contents or functions of reserved mem- ory locations may change with future revisions of the de- vice. Therefore, a program that relies on one or more of these locations may not function properly.
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s intel. 8XC196KT PIN DESCRIPTIONS | Symbot [| Name and Function Main supply vottage (+ 6¥). Vss, Vssu Vssi Digital circuit ground (0V}. There are multiple Vsg pins, all of which MUST be connected. Vrer Reference for the A/D converter (+ 5V). Vper is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. Vpp Programming voltage for the EPROM parts. It should be + 12.5V for programming. It is also the timing pin for the return from powerdown circuit. Reference ground for the A/D converter. Must be held at nominally the same potential as Vss. Input of the oscillator inverter and the internal clock generator. [raiz | Ouputof he cota nvertr P.27/CLKOUT Output of the internal clock generator. The frequency is 1 the oscillator frequency. It has a 50% duty cycle. Also LSIO pin. Reset input to and open-drain output from the chip. P6.7/BUSWIDTH | Input for bus width selection. If CCR bit 1 is a one and CCRt bit 2 is a one, this pin dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an &8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is “0” and CCA bit 2 is “1", all bus cycles are 8-bit, if CCR bit 1 is "1" and CCA1 bit 2 is “0”, all bus cycles are 16-bit. CCR bit 1 = “0” and CCR bit 2 = “0” is illegal. Also an LSIO pin when not used as BUSWIDTH. pm | A positive transition causes a non maskable interrupt vector through memory location 203EH. PS.1/INST Output high during an external memory read indicates the read is an instruction fetch. INST Is valid throughout the bus cycle, INST is active only during external memory fetches, during internat EPROM fetches INST is held low. Also LSIO when not INST. Input for memory select (External Access). EA equal to a high causes memory accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM/ROM. EA equal to a low causes accesses to these locations to be directed to off-chip memory. EA = +12.5V causes execution to begin in the Programming Mode. EA is latched at reset. Bus Hold input requesting control of the bus. |ACDA —_|_Bushold acknowledge output indicating release of the bus. Bus request output activated when the bus controller has a pending external memory cycle. P5.0/ALE/ADV | Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demuttipiex the address from the address/data bus. Wunen the pin is , it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip select for external memory. ALE/ADV is active only during external memory accesses. Also LSIO when not used as ALE. P5.3/AD Read signal output to external memory. FID is active only during external memory reads or LSIO when not used as FD. P5.2/WR/WRL Write and Write Low output to external memory, as selected by the CCR, WA will go low for every external write, while WH will go low only for external writes where an even byte is being written. WA/WAL is active during external memory writes. Also an LSIO pin when not used as WA/WRL.
PIN DESCRIPTIONS (Continued) [__sympor | NameandFunction P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHE =0 selects the bank of memory that is connected to the high byte of the data bus. AO=0 selects that bank of memory that is connected to the low wee ‘Thus accesses to a 16-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only (A0=1, BHE =0) or both bytes (A0=0, BHE = 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is only valid during 16-bit external memory write cycles. Also an LSIO pin when not BHE/WRH. P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/ CCR1. Also an LSIO pin when READY is not selected. P5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The system function is a Slave Port Interrupt Output Pin. P6.2/TICLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on both positive and negative edges of this pin. P6.3/T1DIR Dual function {/O pin. Primary function is that of a bidirectional 1/O pin, however, it may also be used as a TIMER1 Direction input. The TIMER1 will increment when this pin is high and decrements when this pin is low. PORT1/EPA0-7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System P6.0-6.1/EPA8-9 | function is that of High Speed capture and compare. EPAO and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer/counter. PORT 0/ACHO-7 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to EPROM parts to select the Programming Mode. P6.3-6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial 1/O. Two pins are clocks and two pins are data, providing full duplex capability. PORT 2 8-bit multi-functional port. All of its pins are shared with other functions. PORT 3 and 4 8-bit bidirectional |/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. 4-240 ELIMIN, ME 4826175 0144853 385 me PRELIAIRARY |
intel : @XC196KT ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- Voltage from Vpp or EA to your local Intel Sales office that you have the latest Voltage from Any Other Pin “WARNING: Stressing the device beyond the “Absolute This includes Vpp on ROM and CPU devices. Thess . Operation beyond Ws includes Vpp on ROM and CPU devices “Operating Conaitons® 1s not one the may affect device reliability. OPERATING CONDITIONS : [symooi [Parameter =| Win [Max [Units | Oseilator Frequency [4 [16 [tie wiote NOTE: ANGND and Vgg should be nominally at the same potential. DC CHARACTERISTICS (Under Listed Operating Conditions) 4 [Symboi] _Parameter__—[|_min__[typ]_Max [Unite] Test oneitions Voc Supply Current XTAL1 = 16 MHz, Voc = Vpp = Vrer = 5.5V [nar [Wo retoonce Sippy Goren | [| 8 | ma [Whedon Fesay Idle Mode Current mA |XTAL1 = 16 MHz, Voc = Vpp = Vac = 5.5V [no [Poweiownwaae Goro | | | 76 | oh [oo = Vr = Vaer 58087) [ver |noatignvotage | 07 vee | [veo-+as| v [rorponroco | Input High Voltage XTAL1 [07Vec | [Voc +.0.5| V_|XTALt Input Pin Oniy(®) Input High Voltage on RESET | 0.7Vcc | [Voc +0.5| V_|RESET input pin only Vo. | Output Low Voltage 0.3 V Jlot = 200 pass) (Outputs Configured as 045 | V Jip =32mA Complementary) 15 Vo ilo. = 7.0 mA, Vou _ | Output High Voltage Voc - 0.3 Vion = —200nA28) (Outputs Configured as Voc - 0.7 V Jig = -32mA Complementary) Voc — 1.5 V_ {lon = —7.0mA ln [oesionucuren [| | =70 [na [v= onsen —*| | PRELIMINARY 4241 Mm 4426175 O144855 21)
8XC196KT intel ° DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued) [-svmboi | Parameter [in| typ | max | units | test Consttions Vous ‘SLPINT (P5.4) and HLDA (P2.6) 7 lon = 0.8 mA) Output High Voltage in RESET Ouiputigh VotageinREseT | Voo-tv | | |v | tow = ~6 natn PinCepactanceranyrintoves) | | | to | oF | f= OMe [Rweu | Weak Putup Resistance || sox | | a [| owe | NOTES: 1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly pulled high in reset. BD pins include Portt, Port2, Ports, Porta, Ports and Port6 except SPLINT (P5.4) and HLDA (P2.6). 2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 when setup as inputs. 3. All bidirectional 1/O pins when configured as Outputs (Push/Pull. 4, Device is static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum lo. /lox currents per pin will be characterized and published at a later date, 6. Typicals are based on tiited number of samples and are not guaranteed. The values listed are at room temperature and ‘ner = Voc = 5.0V. 7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). 8, When PO is used as analog inputs, refer to A/D specifications for this characteristic. 9. For temperatures <100°C typical is 10 pA. 8XC196KT ADDITIONAL BUS TIMING MODES The 8XC196KT devices have 3 additional bus timing modes for external memory interfacing. MODE 3: Mode 3 is the standard timing mode. MODE 0: Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles. MODE 1: Mode 1 is the long R/W mode. This mode advances AD and WR signals by 1 Toc creating a 2 Togc RD/WA low time. ALE is also advanced by 0.5 Togc but ALE high time remains 1 Togc. MODE 2: Mode 2 is the long R/W mode with Early Address. Mode 2 is similar to Mode 1 with respect to RD, WR, and ALE signals. Additionally, the address is output on the bus 0.5 Tosc earlier in the bus cycle.
4.242 PRELIMINARY |
WM! 4826175 0144860 133
I ntel ° @XC196KT ‘ose xTAL wooe (3) L | MODE (1,2) --=—d wove (3) snneeee act Se eeies eee ap seeenenns, cgokey cer sec ame woo () saneeeen\\_\\_ Eee ees Pe CD Gio is ae men | | MODE (1,2) Detailed MODE 1, 2, 3, Comparison AR’ 4-243 | PRELIGN MB 4826175 0144861 97T
8XC196KT intel . EXPLANATION OF AC SYMBOLS Conditions: Signals: H-High A—Address ~HA—HLDA Each symbol is two pairs of letters prefixed by “T” Low B-BHE L_ALE/ADV for time. The characters in a pair indicate a signal INali and its condition, respectively. Symbols represent V—Valid BR—-BREQ Q—Data Out the time between the two signal/condition points. X—No Longer C—CLKOUT RO—AD Valid D—DATA — W—WR/WRH/WAT 2—Floating G—Buswidth X—XTAL1 H-HOLD Y—READY BUS MODE 0 AND 3 AC CHARACTERISTICS (Over Specied Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The system must mest these specifications to work with the 8XC196KT. AELowioREADY Soup [| owe 0 | | Non READY Time No Upper Limit [ ns__| READY Hol ar GiKOUTiow [0 [Tose 20 | | Address Valid to BUSWIDTHSetup | | 2 Toso - 75 Paes ValétwoutOaVekd | | Tee =| | O.KOUTiow outa vald || Tose = | | NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Tosc x n, where n = number of wait states, 3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the ‘specification. 4-244 ARY M™§ 4626175 O1448b2 806 PRELIMIN: |
intel ® 8XC196KT BUS MODE 0 AND 3 AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 8XC196KT will meet these specifications Frequency on XTAL [40 | 60 | et XTALI Period (1/F rau) ee XTALIHightoCLKOUTHighortow | +20 [10 |e GLKOUT Period [Po atosc | ns CLKOUT High Period [Toso 10 | Tosc+ 30 | ns | CLKOUTLowtoALE/ADVHigh [10 | +5 ns | ALE/ADVLowtoCLKOUTHih | 25 | +15 ns ALE/ADV Cycle Time ee ALE/ADV High Time | Toso= 10 | Tosc+10 | ns | Address Valid to ALE Low [toso-15 [|e Address Hold After ALE/ADV Low Toso=40 [| ns ALE/ADV Low to RD Low [Toso 40 [|e AD Low to CLKOUT Low ec ey 4 RD Low Period [Too-s || st] RD High to ALE/ADV High Tose + 25 AD Low to Address Float re ee ee ALE/ADV Low to WR Low | Toso-to | | ns OLKOUT Low to WR Low ee Data Valid betore WR High [Toso-2a [| ns CLKOUT High to WR High [=i [ts ns WR Low Period [Tosc-30 [nats Data Hold after WR High | Tosc=90 | Ts WR High to ALE/ADV High Toso- 10 | Tosc+ 15 | net | BHE, INST Hold after WR High Toso- 10 | Ts ADB~15 Hold after WR High [ Toso=90 | | nat) BHE, INST Hold after RD High [Toso- to [Ts | NOTES: 1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If walt states are used, add 2 Tosc x n, where n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2 Tosc to specification. 6. Top is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. KT customer QROM codes need to equate location 2016H to the value OCDEH if the oscillator fail detect (OFD) function is desired. intel manutacturing uses location 2016H as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit enables oscillator fail detection. PRELIMINARY 4-245 MH 4826175 0144863 742 Me
8XC196KT intel . BUS MODE 0 AND 3 8XC196KT SYSTEM BUS TIMING Tose XTALI Toten Tenn CLOCKOUT Tou TLLcH Tuna * ALE/ADV \\ Tone . Tur TRurw Tent — Teuov RD TrHoz fe Tove TrHox Tavov Tow Twowi” WR fe Tovws Tox —o BUS WRITE Twuex & Truex BHE, INST TwHax OF Trax (272266-5 * If mode 0 operation is selected, add 2 Tosc¢ to this time. 4-246 PRELIMINARY MH 4826175 144864 689 a |
MODE 0 AND 3 8XC196KT READY TIMINGS (ONE WAIT STATE) Tose XTALT Tawon CLKOUT Toc Teun = Tach Toure Gun) READY VTL] Ta Trurn * 2 Tose cr) Twuwn * 2 Tose WR ee 4 us write XX poowess oor Q(t) (272266-6 “If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 Tosc to these specifica- tions. 8XC196KT BUSWIDTH TIMINGS Tose CLKOUT ALE Tusv* = Teusx 272266-7 *If mode 0 selected, add 2 Togc to these specifications. PRELIMINARY 4-247 BB 4826175 O1448b5 515
8XC196KT intel ° BUS MODE 1—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The system must meet these specifications to work with the 8XC196KT. [_symbor [Parameter [win [Max [Units] | tan [ada Vaioio Ready Setup |__| Tose 78 | vw | | tuw | AtetowtoReADysewe | [48 Toso-70 | ne | | Turi | NonReADyTime [No Uppertimit ns | |_Tourx__[ READY HoldattercLxouTiow | 0 [Toso 30 | nat) |_Tavev | AddressvaidtosuswiotHseup [| 2 Toso 758 [nd | | tucv | AtetowtosuswiotHsewp [| Tsosc— 60 | ns | | Tox | suswiotHHodatercuxouttow [0 [| ns [Tar [Ades Vato mount veka | | Toa eo | oat] [Tov | ROAcweoinputDatavald__—| | Toso 44 | ra _| |_ Toy [7 ctkouTLowioinputdatavaid [| Tosc— 60 | ns | |_Taoz | EndotADtoinputOataFoat || Toso | ns [_Tanox | DataHoWdaternDHign | oT ns NOTES: 1. if Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Tosc x n, where n = number of wait states. If mode 0 is selected, one wait state minimum is always added. I additional wait states are required, add 2 Tosc to the specification. 4-248 . PRELIMINARY M@ 4826175 O1448bb 4S] |
intel ° 8XC196KT BUS MODE 1—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 8XC196KT will meet these specifications [Farm | Freworcyonataus «| ao | 180 | [tose | XTALt Perea Wea) =| wes sow [Time | XTAL Hight GLKOUT Highertow [ro | |e _| Trae [axourrees | Toss Side [Tee | tkoutHigneoied (tase 10 | Toso te? | me | | Tou | CLKOUTHighoALE/ADVHigh [05 Toso-18 | O5Tosc +15 | ns _| [Tau | eixourtowinALEADView | 08Tose 25 | o8Tosc+15 | rs _| [Tue | ALEMADVGeeTe | Togo |_| [tua | Ae/ADVegn Tine | Toso=v0 [Tose | rs _| tae Adeoss VaidtoALELow | O5Toss- | | as [Tux | AdseossHold ater ALE/ADViow | 05Toso=20 [| ne [tum | NE/ADV towoRDLow | 05Toso 15 | id | Cine | rotwiocixouriow [Toso | Tox ta | mo | [Tas | ROLowPeroa Togo | |_| 4 [Taz | ROtowiwAdiossFoat | | |e [um | NE/ADVLowowntow | a8Tose=10 | ——*d| re | [team | etKOUT tow ioWRtow | Toso15 | Tous as | os | [Town | bate vatdotorewarigh | @Toso=29 [| re | [Town | xKoUTHgniowRHgh [0 |e |e [wun | watowPerod =| Togo ||| [wnax | OataHot aterwivigh | 05Toso=28 [| rs [wn | WRHghtDALE/ADV High | 05Toso= 10 | O8Tosn + 10 | ns [Timex | BHEWodaRerwmnGh [Toot [| re | a [Twix | A08-16Hokaterwniigh | esTose=20 | |_| [Tasex | BHEHoWaterROWgh | Toso 92 | ids | taux [NST HodeternO Heh | 05Toso-@ | Ss ee NOTES: 1, Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3, Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 Togc n, where n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2 Tosc to specification. | PRELIMINARY 462eb1L?5 OL4Y48b? 396 “ee
MODE 1—8XC196KT SYSTEM BUS TIMING Tose XTAL1 Town Tevet. TyHon cLockouT Tout Tun ALE/ADV \\ Tune RD ( feta Tenoz ous Reap ))) aD ee (GENIN), Thum, Twuw m - foe TovwH Twuax BUS WRITE TwHexe Trex BHE Twnaxe TRHAX ADB - ADIS. Twixe TRHIX T2286-8 4-250 PRELIMINARY BB 4826175 0144868 224
MODE 1—8XC196KT READY TIMINGS (ONE WAIT STATE) XTAL1 CLKOUT 4 E READY aa Taw Tarn * 2 Tose Tov * 2 Tage ——— Bus READ SY))))YYPYNX_svowess oot) xT)», Twun + 2 Tose we BUS WRITE (Tsooness oot XQ oe) 272266-9° MODE 1—8XC196KT BUSWIDTH TIMINGS Tose CLKOUT ALE Tuev — Teusx BUS WRITE Em ((( LD Me (((( 27220610 ELM 251 | PRELIMINARY 4826175 O1448b9 1bO me *
8XC196KT intel . BUS MODE 2—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The system must meet these specifications to work with the 8XC196KT, ‘Address Valid to Ready Setup [ | 25tosc-75 | ns | ALE Low to READY Setup | | +8Tosc=70 [ns | Non READY Time No Upper Limit [ns | READY Hold after CLKOUT Low [| o | Tosc-30 | ns | Address Valid to BUSWIDTH Setup | =| 28 Tosc—75 | ns__| BUSWIDTHHoldattercuKoUTLow [0 {| ns_ | ‘Address Valid to Input Data Valid ee RD Active to Input Data Valid [| | aTosc= 44 | ns | End of RD to input Data Foat | | os tosc | ns | NOTES: 1, If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Tosc x n, where n = number of wait states. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the specification. 4-252 PRELIMINARY | SB 4826175 0144870 942
BUS MODE 2—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 8XC196KT will meet these specifications [symoo | __ Parmeter [wm | a [tose [tat Peioatveea) | es | tse | [Tyan [*TALt igh ouKOUT Highertow [+20 | re8 | os _| [tac eumoutrema | Toss [res | cumourrgnroioa | Toss | Tota” | vw | [Town | GLKOUTHgneALETABWFGh | O5Toss —15 | O5Tose + 6 | ro | [Tea | cLKOUT Low wALE/ADV Low | 05 Togo@5 | 08 Toscrts | om | [Tue | Aeovopetie [tows] | SP [tae | Ades Valo ALEtow [Toso | |e | [Tum | Aros Hot afer ALE/AGViGw | O5Toxs 20 | | me | [tun | ALe/ADViowioROLw | 0sToan 18 | |_| [tax | ROLowwaixouTiow | Toso 10 | Tosors0 | ne | [trea [RO Hgnio ALETADVRigh | O5Toso-6 | OSToso 06 | nat | [tase | AO towioAdessFot || [ram [ ADV iow owntow | 08Towe vo | |e | [rem _[ xKoUTLowiowntow | Toso-2 | Toso +28 | ne_| [towns | ata Vataetorewnvigh | PTose2s | | me | [toms [ cuKouTHgn owavign [| |e | [um | wrtoweerod «Togo | | [wor | tao aterwnvign | 0sTose- 25 | it | [tyne | Wgh oALE/ADVHgh | 05Towe 10 | 08 Tose +10 | os®™_| [woe [BME Wodaterwnvign | Too | | w | [wm INSTHodaterwnrign [estos | | [tyme | AD0-6Howaterwarigh | O5Toxo=30 | | —ra_—| [Tuex | BHEHoWateraDHign [Tose -s2 | iT | [tae [NSTHoM aternoHgh | Ostoxs—@ | || NOTES: 1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4, 8-bit bus only. 5. If wait states are used, add 2 Togo X n, where n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2 Tosc to specification.
8XC196KT intel. MODE 2—8XC196KT SYSTEM BUS TIMING Tose XTAL1 Tenet Toret TxHeH CLOCKOUT Tou Tu ALE/ADV \\ Tou ry \\ y, Tenoz be tae BUS READ (IED, Tuuwe wow wR BUS WRITE TwHex: Trex BHE Ce t=” Twraxe TRHaX ADB ~ ADI5 Twuixe Trac Tae 4-254 PRELIMINARY MB 4826175 0144872 755 ]
e MODE 2—8XC196KT READY TIMINGS (ONE WAIT STATE) XTALt CLKOUT J. Taw a READY o UIT] i“ Tra * 2 Tose RD Tavov * 2 Toso. —— +} pus wean DYX___soonss our) CL), Twn * 2 Tose WR BUS WRITE (>) 27226612 MODE 2—8XC196KT BUSWIDTH TIMINGS Tose CLKOUT ALE ‘uv —{ Teusx ous wane Xamon XQ) 272286-13 PRELIMINARY 4-255 MH 4626175 0144873 691
8XC196KT intel . BUS MODE 0, 1, 2, and 3 HOLD/HOLDA TIMINGS (Over Specified Operation Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. [Tora | OUKOUT tow ACDRtow [ts |e |_| LKOUT Low io BREG Low [1s [41s [ne | [Tama [| ACDAtowwadessFost || ts |_| [Tez | HCOR Low oBRE,INST.FO,WAWestiyOnven [| 405 | nw | NOTE: 1, To guarantee recognition at next clock. 8XC196KT HOLD/HOLDA TIMINGS Tose CLKOUT Tween Tween HOLD leo caTeNey TouwaL TounaH HOLDA Tevom Tovse BREQ Twauaz Tanna BUS ) ee Twaver TwaHax, BHE, INST, <a ~ RO IR ms oa Tone ALE [\\. res 4-256 PRELIMINARY MH 4626175 0144874 528 mm
intel ° 8XC196KT AC CHARACTERISTICS—SLAVE PORT SLAVE PORT WAVEFORM—{SLPL = 0) | TsrHav ne/as CD ® LY : ae " Ld 27228616 SLAVE PORT TIMING—{SLPL = 0, 1, 2, 3) 4 FD High to Address Valid | o | | os | WR Low Period [toss | | ne NOTES: 1. Test Conditions: Fogc = 16 MHz, Togc = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. PRELIMINARY 4-257 ME 4826175 O144875 4b4 mm
8XC196KT intel. AC CHARACTERISTICS—SLAVE PORT (Continued) SLAVE PORT WAVEFORM—{SLPL = 1) Tseuu TsrveH 5 | | ® — nd 8 (—_ C) [sar] Tucan | Tswuwn (272286-16 SLAVE PORT TIMING—{SLPL = 1, 2, 3) [| symbor_ [Parameter [Min |= Max | Unita GS Low to ALE Low ee ee ee ADorWAHightoCSHigh | eo | | ALE Low to FD Low | toss [| s| FD Low Period [toss [Ts | WE Low Period | toss | Ts Address ValidtoaLeLow | 20 | |_| ALELowtoAddressinvaid [20 || FDLowtoOuputDatavaid | | goons ‘inputDataSeuptoWRHign | 20 | |r| WR High to Data Invalid ee ee RD High to Data Float ee NOTES: 1. Test Conditions: Fogc = 16 MHz, Tosco = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are ‘subject to change.
4.258 PRELIMINARY
intel ® 8XC196KT EXTERNAL CLOCK DRIVE OscilatorFrequency | # | St | Me OscilatorPerod Tos) | 625 | aso Tn
0.35 X Tose o65Tosc | ns |
[tuxy | Rete | Tt ns Fall Time ee EXTERNAL CLOCK DRIVE WAVEFORMS Tx TxLxH Tox 0.7Ve¢40-5V A. 7ec0.5¥ Tax 0:7 Voc t0.5¥ a (272266-17 AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS oO ww ourrurs Vigaott.t8¥ Voy 0:18¥ SV TIMING REFERENCE \\ a “Loao » POINTS < J Test FONTS Vioap70-15¥ Vou +0-15¥ 0.45V = (272266-19 272266-18 For timing purposes a Port Pin is no longer floating AC Testing inputs are driven at 3.5V for a logic "1" and when a 150 mV change from load voltage occurs and 0.45V for a logic “0”. Timing measurements are made. begins to float when a 150 mV change from the loading at 2.0V for a logic “1” and 0.8 for logic “0”. Vou/Vor level occurs lov/Iow < 15 mA. PRELIMINARY 4.259 MH 4826175 0144877 237?
8XC196KT intel ° WAVEFORM—SERIAL PORT—SHIFT REGISTER MODE SERIAL PORT WAVEFORM—SHIFT REGISTER MODE RESET Tw ADOR ADDR+2 P21 PROG P2.2 Ture, TING P24 272206-22 AC CHARACTERISTICS—SERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMING—SHIFTING REGISTER MODE Test Conditions: Ta = —40°C to + 125°C; Voc = 5.0V + 10%; Vss = 0.0V; Load Capacitance = pF [_svmbot | Parameter | min | Max | ‘Unite | | Tax | SeralPoriockreios [toss | |__| Serial Port Clock Faling EdgetoRisingEdge | 4Tosc— 80 | Tosc+ 50 | ns_| Output Data Setup to Glock Rising Edge | STosc | |r| Output DataHoldatter Clock isingEdge | 2Tosc-80 [| ns_| Next Output Data Valid after Clock Rising Edge || 2 Toso + 50 | ns_| Input Data Setup to Clock Rising Edge | 2tosc +200 | | ns | | Taox" | inputDataHoidatteriockRisingewe || |_| [Toraz\\ | LastciocrFising to OupurFioat [|S Tose |__| NOTE: 1. Parameters not tested. 4-260 PRELIMINARY mm 4826175 0144878 173 Me
intel ° 8XC196KT ATO D CHARACTERISTICS The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of Vrer- 10-BIT MODE A/D OPERATING CONDITIONS a | Teter cameron | NOTES: 1. Ver must be within 0.5V of Voc. 2. The value of AD_TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)(®) . 1024 1024 Level cc UC nwauiserer 8] [erthesiy | ts20 | ae | Temperature Coefficients: Offset 0,009 LSB/C(1) Full Scale 0.009 LsB/c(1) Differential Non-Linearity 0.009 LsB/C(1) moat [one pst “An “LSB” as used here has a value of approximately 20 mV. NOTES: 1. These values are expected for most parts at 25°C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4, Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltages beyond these ‘specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode. PRELIMINARY 4-261 | @™ 4826175 0144879 ooT =
8XC196KT intel ® 8-BIT MODE A/D OPERATING CONDITIONS Symbol | __Deseription [min [Max «Unite —_— Ambient Temperate | oT x70 |e Digital Supply Voge | aso | sso fC Analog SupplyVotage | 450 | sso |_| Sample Time ee |_—Toow | Gonversontine [7 | ed OscilatorFrequency [40 | 60 | iz | NOTES: 1. Ver must be within 0.5V of Voc. 2. The value of AD__TIME is selected to meet these ‘specifications. 8-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)(6) [|-—__ Parameter tye) [win] Max | Unite ‘| 256 256 Level ee Full Scale Ertor a | Zeoonsetérr [sos [Cds [Nontinsrty +d a8 | DiterentalNoninearty [| os | ros | tsbe | Ghannelto-Channel Matching || oT eto «| tse | Temperature Coefficients: Offset 0.003 LSB/c(t) Full Scale 0.003 LSB/C(1) Differential Non-Linearity 0.003 LsB/o() Off isolation re ee ee a DC input Leakage [tio [of sa0 a | VotageonAnaloginputrin | | ANGND — 0.5 Sampling Capacitor | so [Oe *An “LSB” as used here has a value of approximately 20 mV. NOTES: 1. These values are expected for most parts at 25°C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4. Resistance from device pin, through internal MUX, to ‘sample capacitor. 5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 8. All conversions performed with processor in IDLE mode. 4-262 PRELIMINARY WH 4826175 0144880 62] |
intel ° 8XC196KT EPROM SPECIFICATIONS OPERATING CONDITIONS [symbol | Deseipion | win] wax [Unie Taian Tonperature ding Progamming | 20] #0 | -o _] Supply Volage ung Progening [nas [ss Feternce Sup} Volage dung Progranning [4s | 85 | wo] Programming Votage [eas | a8 EAP Votage iaas [1276 Oscillator Frequency during Auto and Slave Mode Programming Fose ‘Oscillator Frequency during Run-Time Programming NOTES: 1. Voc and Vaer should nominally be at the same voltage during programming. 2. Vpp and Veq must never exceed the maximum specification, or the device may be damaged. 3. Vgg and ANGND should nominally be at the same potential (OV). 4, Load capacitance during Auto and Slave Mode programming = 150 pF. AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) sates Soup Tine ee es 4 ‘Adress Hod Tire a a Daia Seip Tie [—° [| ese | Daia Hold Tine [a0 [ros | PACE Plo Wii a PROG Pls wit [so [} tose FALE tight PROG tow | 200 | | Toso | PRG High tonen PACE Low | 220 | | Tose | Word ump Hold Time ee PROG High to net PROGLow | 220 | | Toso | FALE Highto ROGLw | 200 | | Toso | PROG Low to Word Dunpvaid [| 60 | Tose | RESET High ort PALE Low [300] | Toso | PROG High wANCLow | 0 | | Toso _| TING Puise With ee PVER Hola ARGLow | 50 | | Tose | PROG High wPVER Vans |__| 290 | Tose] NOTES: Vpp = 12.5V +0.25V. For run-time programming over a full operating range, contact factory. 2. Programming specifications are not tested, but guaranteed by design. 3. This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm. PRELIMINARY 4-263 | ME 4826175 0144881 768 mm
8XC196KT intel ° DC EPROM PROGRAMMING CHARACTERISTICS Symbol [Parameter Min [Max | Units | [___lep_ | Vep Programming Supply Curent [| 200 Sma Ci NOTE: Don not apply Vpp until Voc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE ‘RESET Tavtt Tove, “ye C{ rooress/eouuan P—K ara Teas an Oe Toe Pa ex PROG ed Tu (272266-21 NOTE: P3.0 must be HIGH ("1") SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT ‘RESET ( Tow ADOR ADDR + 2 ay) Creras/wo oun )>-—€ ver 5/wo ouv Tov Tonox PALE eM PROG ra Ture TpHPL NC ree 272088-22 NOTE: 3.0 must be LOW ("0") 4-264 PRELIMINARY Mi 4426175 0144882 ETH Me
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT TEST i a a P21 Tevet Tur hood rt e2 ° tw a (iam hae / Tue ane Pa Tei 27226623 8XC196KT ERRATA The following is a list of all known functional devia- tions for 8XC196KT devices. C-step devices can be identified by a special mark following the eight digit FPO number on the top of the package. For C-step devices, this mark is a “C” 1. The following reserved op-codes do not generate the unimplemented op-code interrupt: 1Ch, 1Dh, 1Eh, 1Fh, E3h, E4h, E6h, E8h, Eh, EAh, EBh and Fth. PRELIMINARY 4-265 MB 4426175 0144883 530