TN87C196CB

87C196CA INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. April 1996COPYRIGHT © INTEL CORPORATION, 1996 Order Number: 272405-004 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive Y High Performance CHMOS 16-Bit CPU (up to 20 MHz Operation) Y Register-Register Architecture Y Up to 56 Kbytes of On-Chip EPROM Y Up to 1.5 Kbyte of On-Chip Register RAM Y Up to 512 Bytes of Additional RAM (Code RAM) Y Up to 16 Mbyte Linear Address Space Y Supports CAN (Controller Area Network) Specification 2.0 Y 15 Message Objects of 8 Bytes Data Length Y 10-Bit A/D with Sample/Hold Y 38 Prioritized Interrupts Y Up to Seven 8-Bit (60) I/O Ports Y Full Duplex Serial Port (SIO) with Dedicated Baudrate Generator Y Full Duplex Synchronous Serial I/O Port (SSIO) Y Interprocessor Communication Slave Port Y Selectable Bus Timing Modes for Flexible Interfacing Y Oscillator Fail Detection Circuitry Y High Speed Peripheral Transaction Server (PTS) Y Two Dedicated 16-Bit High-Speed Compare Registers Y High Speed Capture/Compare (EPA) Y Two Flexible 16-Bit Timer Counters Y Flexible 8-/16-Bit External Bus (Programmable) Y Programmable Bus (HLD/HLDA) Y 1.4 ms 16 x 16 Multiply Y 2.4 ms 32/16 Divide b40§Ct o a125§C Ambient Device Pins/Package EPROM Reg RAM Code RAM I/O EPA SIO SSIO CAN A/D Address Space 87C196CB 84-Pin PLCC 56K 1.5K 512b 56 10 Y Y Y 8 1 Mbyte 87C196CB 100-Pin QFP 56K 1.5K 512b 60 10 Y Y Y 8 16 Mbyte 87C196CA 68-Pin PLCC 32K 1.0K 256b 38 6 Y Y Y 6 64 Kbyte The 87C196CA/CB are new members of the MCS É 96 microcontroller family. These devices are based upon the MCS 96 Kx/Jx microcontroller product families with enhancements ideal for automotive and industrial applications. The CA/CB are the first devices in the Kx family to support networking through the integration of the CAN 2.0 (Controller Area Network) peripheral on-chip. The 87C196CB offers the highests memory density of the MCS 96 microcontroller family, with 56K of on-chip EPROM, 1.5K of on-chip register RAM, and 512 bytes of additional RAM (Code RAM). In addition, the 87C196CB provides up to 16 Mbyte of Linear Address Space. The 87C196CA is a sub-set of the CB, offering 32K of on-chip EPROM, up to 1.0K of on-chip register RAM, and 256 bytes of additional RAM (Code RAM).

to verify you have the latest information. Figure 1. 8XC196CB Block Diagram

mal impedance test methodology. Figure 2. The 87C196CA/CB Familiy Nomenclature

1. iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft.

away from case in air flow environment. iJC e Thermal resistance between junction and package face (case).

1. All values of iJA and iJC may fluctuate depending on the environment (with or without airflow, and how much airflow)

and device power dissipation at temperature of operation. Typical variations are g2§C/W.

1. Values listed are at a maximum power dissipation of 1.0W.

Figure 3. 84-Pin PLCC AN87C196CB Diagram

Figure 4. 100-Pin QFP AS87C196CB Diagram

Figure 5. 68-Pin PLCC 87C196CA Diagram

VCC Main Supply Voltage ( a5V). VSS,VSS1 Digital circuit ground (0V). There are 7 V SS pins CB (4 on CA), all of which MUST be connected to a single ground plane. VREF Reference for the A/D converter ( a5V). V REF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as V SS. VPP Programming voltage for EPROM parts. It should be a12.5V for programming. It is also the timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to V SS and a 1Mohm resistor to V CC. If this function is not used, V PP may be tied to V CC. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the Oscillator Inverter. RESETÝ Reset input to the chip. Input low for at least 16 state times will reset the chip. The subsequent low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared, bytes are read from 2018H, 201Ah and 201CH (if enabled) loading the CCB’s, and a jump to location 2080H is executed. Input high for normal operation. RESET Ý has an internal pullup. NMI A positive transition causes a non-maskable interrupt vector through memory location 203EH. If not used, this pin should be tied to V SS. May be used by Intel Evaluation boards. EAÝ Input for memory select (External Access). EA Ý equal to a high causes memory accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip EPROM/ROM. EA Ý equal to a low causes accesses to these locations to be directed to off-chip memory. EA Ý ea 12.5V causes execution to begin in the Programming Mode. EA Ý is latched at reset. PLLEN Selects between PLL mode or PLL bypass mode. This pin must be either tied high or low. PLLEN pin e 0, bypass PLL mode. PLLEN pin e 1, places a 4x PLL at the input(196CB only) of the crystal oscillator. Allows for a low frequency crystal to drive the device (i.e., 5 MHz e 20 MHz operation). P6.4–6.7/SSIO Dual function I/O ports have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data providing for full duplex capability. Also LSIO when not used as SSIO. P6.3/T1DIR Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Direction input. The TIMER1 will increment when this(CB only) pin is high and decrements when this pin is low. P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however may also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on(CB only) both positive and negative edges of this pin. P6.0–6.1/EPA8–9 Dual function I/O port pins. Primary function is that of bidirectional I/O. System function is that of High Speed capture and compare.

P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low,(CB only) an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’, all bus cycles are 16-bit. CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal. Also an LSIO pin when not used as BUSWIDTH. P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next opositive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if READY is not selected. P5.5/BHEÝ/WRHÝ Byte High Enable or Write High output, as selected by the CCR. BHE Ý e 0 selects the bank of memory that is connected to the high byte of the data bus. A0 e 0 selects the bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0, BHE Ý e 1), to the high byte only (A0 e 1, BHE Ý e0) or both bytes (A0 e 0, BHE Ý e 0). If the WRH Ý function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE Ý/WRHÝ is only valid during 16-bit external. Also an LSIO pin when not BHE/WRH Ý. P5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The system function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only). P5.3/RDÝ Read signal output to external memory. RD Ý is active only during external memory reads or LSIO when not used as RD Ý. P5.2/WRÝ/WRLÝ Write and Write Low output to external memory, as selected by the CCR, WR Ý will go low for every external write, while WRL Ý will go low only for external writes where an even byte is being written. WR Ý/WRLÝ is active during external memory writes. Also an LSIO pin when not used as WR Ý/WRLÝ. P5.1/INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is active only during external(CB only) memory fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST. P5.0/ALE/ADVÝ Address Latch Enable or Address Valid Output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV Ý, it goes inactive (high) at the end of the bus cycle. ADV Ý can be used as a chip select for external memory. ALE/ADV Ý is active only during external memory accesses. Also LSIO when not used as ALE.

PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. P2.7/CLKOUT Output of the internal clock generator. The frequency is the oscillator frequency. CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT. P2.6/HLDAÝ Bus Hold Acknowledge. Active-low output indicates that the bus controller has relinquished control of the bus. Occurs in response to an external device asserting the HLD Ý signal. Also LSIO when not used as HLDA Ý. P2.5/HLDÝ Bus Hold. Active-low signal indictes that an external device is requesting control of the bus. Also LSIO when not used as HLD Ý.(CB only) P2.4/INTOUTÝ Interrupt Output. This active-low output indicates that a pending interrupt requires use of the external bus. Also LSIO when not used as INTOUT Ý P2.3/BREQÝ Bus Request. This active-low output signal is asserted during a HOLD cycle when the bus controller has a pending external memory cycle. Also LSIO when not used as(CB only) BREQ Ý P2.2/EXTINT A positive transition on this pin causes a maskable interrupt vector through memory location 203CH. Also LSIO when not used as EXTINT. P2.1/RXD Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD. P2.0/TXD Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD. PORT 1/EPA0–7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System function is that of High Speed capture and compare. EPA0 and EPA2 have another function of T2CLK and T2DIR of the TIMER2 timer/counter. PORT 0/ACH0–7 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to EPROM parts to select the Programming Mode. EPORT 8-bit bidirectional standard and I/O Port. These bits are shared with the extended address bus, A16–A19 for CB PLCC, A16–A23 for CB QFP. Pin function is selected on(CB only) a per pin basis. TXCAN Push-pull output to the CAN bus line. RXCAN High impedance input-only from the CAN bus line.

FFFFFFH Program Memory - Internal EPROM or External Memory FF2080H (Determined by EA Ý Pin) FF207FH Special Purpose Memory (Internal EPROM or External Memory) FF2000H (Determined by EA Ý Pin) FF1FFFH External Memory FF0600H FF05FFH Internal RAM (Identically Mapped into 00400H–005FFH) FF0400H FF03FFH External Memory FF0100H FF00FFH Reserved for ICE FF0000H FEFFFFH Overlayed Memory (External)ÐAccesses into Memory Ranges 0F0000H to FEFFFFH will Overlay Page 15 (0FH) for CB QFP packageÐExternal Memory. (5)0F0000H 0EFFFFH 900 Kbytes External Memory 010000H 00FFFFH External Memory or Remapped OTPROM (Program Memory) (1) 002080H 00207FH External Memory or Remapped OTPROM (Special Purpose Memory) (1, 3) 002000H 001FFFH Memory Mapped Special Function Registers (SFR’s) 001FE0H 001FDFH Internal Peripheral Special Function Registers (SFR’s) (5) 001F00H 001EFFH Internal CAN Peripheral Memory (5) 001E00H 001DFFH Internal Register RAM 001C00H 001BFFH External Memory 000600H 0005FFH Internal RAM (Code RAM) 000400H (Address with Indirect or Indexed Modes) 0003FFH Register RAM – Upper Register File (Address with Indirect or Indexed Modes or through Windows.)(2)000100H

87C196CB Memory Map (Continued) Address Description 0000FFH Register RAM – Lower Register File. (Address with Direct, Indirect, or Indexed Modes.) (2) 000018H 000017H CPU SFR’s (4) 000000H NOTES: 1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA Ý e 5V. Otherwise they are external memory. 2. Code executed in locations 0000H to 003FFH will be forced external. 3. Reserved memory locations must contain 0FFH unless noted. 4. Reserved SFR bit locations must be written with 0. 5. Refer to 8XC196CB User’s Guide for SFR, CAN and Paging Descriptions. 87C196CA Memory Map Address Description 00FFFFH External Memory 00A000H 009FFFH Internal EPROM (32 Kbytes) 002080H 00207FH (Determined by EA Ý Pin) Reserved Memory (Internal EPROM or External Memory) 002000H 001FFFH Memory Mapped Special Function Registers (SFR’s) 001FE0H 001FDFH Internal Special Function Registers (SFR’s) (1) 001F00H 001EFFH Internal CAN Peripheral Memory 001E00H 001DFFH External Memory 000500H 0004FFH (Address with Indirect or Indexed Modes) Internal RAM (Code RAM) 000400H 0003FFH Internal Register RAM – Upper Register File (Address with Indirect or Indexed Modes or through Windows) (2)000100H 0000FFH Internal Register RAM – Lower Register File (Address with Direct, Indirect, or Indexed Modes(2).000018H 000017H CPU Special Function Registers (SFR’s) (2, 4) 000000H NOTES: 1. Refer to 8XC196KX Family User’s Guide for SFR Description. 2. Code executed in locations 0000H to 03FFH will be forced external. 3. Reserved SFR bit locations must be written with 0. 11

CCB (2018h : Byte) 0P D e ‘‘1’’ Enables Powerdown

1 BW0 e See Table

2W R e ‘‘1’’ e WRÝ/BHEБ‘0’’ e WRLÝ/WRHÝ

3 ALE e ‘‘1’’ e ALEБ‘0’’ e ADVÝ

4 IRC0 e See Table

5 IRC1 e See Table

6 LOC0 e See Table

7 LOC1 e See Table

CCB1 (201Ah : Byte)

0 CCR2 e ‘‘1’’ fetch CCB2 (‘‘0’’ for CA)

1 IRC2 e See Table

2 BW1 e See Table

3 WDE e ‘‘0’’ e Always Enabled

41 e Reserved Must Be ‘‘1’’ 50 e Reserved Must Be ‘‘0’’

6 MEMSEL0 e See Table (‘‘1’’ for CA)

7 MEMSEL1 e See Table (‘‘1’’ for CA)

CCB2 (201Ch : Byte) (CB Only) 00 e Reserved Must be ‘‘0’’

1 MODE16 e Select 16-Bit or 24-Bit Mode

2 REMAP e ‘‘0’’ÐSelect EPROM/CODERAM in Segment 0FFH only

( ‘‘1’’ÐSelect Both Segment 0FFH and Segment 00H 31 e Reserved Must be ‘‘1’’ 41 e Reserved Must be ‘‘1’’ 51 e Reserved Must be ‘‘1’’ 61 e Reserved Must be ‘‘1’’ 71 e Reserved Must be ‘‘1’’ LOC1 LOC0 Function 0 0 Read and Write Protected 0 1 Write Protected Only 1 0 Read Protected Only 1 1 No Protection MSEL1 MSEL0 ‘‘CB’’ Bus Timing Mode 0 0 Mode 0 (1-Wait KR) 0 1 Reserved Must Not Be Used 1 0 Reserved Must Not Be Used 1 1 Mode 3 (KR) Mode 0 Designed to be similar to the 87C196KR bus (1-Wait KR): timing with 1 automatic wait state. See AC Timings section for actual timings data. Mode 3 (KR): Designed to be similar to the 87C196KR bus timing. See AC Timings section for actual timings data. IRC2 IRC1 IRC0 Max Wait States 0 0 0 Zero Wait States 1 0 0 1 Wait State 1 0 1 2 Wait States 1 1 0 3 Wait States 1 1 1 INFINITE BW1 BW0 Bus Width 0 0 ILLEGAL 0 1 16-Bit Only 1 0 8-Bit Only 1 1 BW Pin Controlled

ABSOLUTE MAXIMUM RATINGS * Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b60§Ct o a150§C Voltage from V PP or EA to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a13.0V Voltage from Any Other Pin to V SS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b0.5 to a7.0V This includes V PP on ROM and CPU devices . Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.0W NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet be- fore finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Parameter Min Max Units TA Ambient Temperature Under Bias b40 a125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 4 20 MHz (4) NOTE: ANGND and V SS should be nominally at the same potential. DC CHARACTERISTICS (Under Listed Operating Conditions) Symbol Parameter Test Conditions Min Typ Max Units ICC VCC Supply Current XTAL1 e 20 MHz, (b40§Ct o a125§C Ambient) V CC e VPP e VREF e 5.5V CA (While device in Reset) 90 mA CB 100 mA IREF A/D Reference Supply Current 5 mA IIDLE Idle Mode Current XTAL1 e 20 MHz, CA V CC e VPP e VREF e 5.5V 40 mA CB 35 mA IPD Powerdown Mode Current V CC e VPP e VREF e 5.5V(6, 9) 50 TBD mA VIL Input Low Voltage (all pins) For PORT0 (8) b0.5V 0.3 V CC V VIH Input High Voltage For PORT0 (8) 0.7 V CC VCC a 0.5 V VOL Output Low Voltage I OL e 200 mA(3,5) 0.3 V (Outputs Configured as I OL e 3.2 mA 0.45 V Complementary) I OL e 7.0 mA 1.5 V VOH Output High Voltage I OH eb 200mA(3,5) VCC b 0.3 V (Outputs Configured as I OH eb 3.2 mA V CC b 0.7 V Complementary) I OH eb 7.0 mA V CC b 1.5 V

87C196CB I CC vs Frequency 272405–31 87C196CA I CC vs Frequency 272405–32

DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued) Symbol Parameter Test Conditions Min Typ Max Units ILI Input Leakage Current (Std. Inputs) V SS k VIN k VCC g10 mA ILI1 Input Leakage Current (Port 0) V SS k VIN k VREF CA g1.5 mACB g1.0 VOH1 SLPINT (P5.4) and HLDA (P2.6) I OH e 0.8 mA (7) 2.0 V Output High Voltage in RESET VOH2 Output High Voltage in RESET I OH eb 15 mA(1) VCCb1V V CS Pin Capacitance (Any pin to V SS)f test e 1.0 MHz (6) 10 pF RWPU Weak Pullup Resistance (Note 6) 150K X RRST Reset Pullup Resistor For CB 65K 180K X RRST Reset Pullup Resistor CA For CA 6K 65K X NOTES: 1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6). 2. Standard input pins include XTAL1, EA , RESET, and Port 1/2/5/6 when setup as inputs. 3. All bidirectional I/O pins when configured as Outputs (Push/Pull). 4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum I OL/IOH currents per pin will be characterized and published at a later date. 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF e VCC e 5.0V. 7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). 8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic. 9. For temperatures k100§C typical is 10 mA. 8XC196CB ADDITIONAL BUS TIMING MODES The 8XC196CB device has 2 bus timing modes for external memory interfacing. MODE 3: Mode 3 is the standard timing mode. Use this mode for systems that emulate the 8XC196KR bus tim- ings. MODE 0: Mode 0 is the standard timing mode, but 1 (mini- mum) wait state is always inserted in external bus cycles.

AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The 87C196CA/CB will meet these specifications Symbol Parameter Min Max Units FXTAL Frequency on XTAL1 4.0 20 MHz (1) TOSC XTAL1 Period (1/F XTAL) 50.0 250 ns TXHCH XTAL1 High to CLKOUT High or Low a20 110 ns TOFD Clock Failure to Reset Pulled Low (6) 44 0 ms TCLCL CLKOUT Period 2 T OSC ns TCHCL CLKOUT High Period T OSC b 10 T OSC a 15 ns TCLLH CLKOUT Low to ALE/ADV High b15 a10 ns TLLCH ALE/ADV Low to CLKOUT High b20 a15 ns TLHLH ALE/ADV Cycle Time 4 T OSC ns(5) TLHLL ALE/ADV High Time T OSC b 10 T OSC a 10 ns TAVLL Address Valid to ALE Low T OSC b 15 ns TLLAX Address Hold After ALE/ADV Low T OSC b 40 ns TLLRL ALE/ADV Low to RD Low T OSC b 30 ns TRLCL RD Low to CLKOUT Low CA a4 a30 ns CB b8 a20 ns TRLRH RD Low Period T OSC b 10 ns (5) TRHLH RD High to ALE/ADV High T OSC TOSC a 25 ns (3) TRLAZ RD Low to Address Float 5 ns TLLWL ALE/ADV Low to WR Low T OSC b 10 ns TCLWL CLKOUT Low to WR Low b5 a25 ns TQVWH Data Valid before WR High T OSC b 23 ns TCHWH CLKOUT High to WR High b10 a15 ns TWLWH WR Low Period CB T OSC b 30 ns (5) CA T OSC b 20 TWHQX Data Hold after WR High T OSC b 25 ns TWHLH WR High to ALE/ADV High T OSC b 10 T OSC a 15 ns (3) TWHBX BHE, INST Hold after WR High T OSC b 10 ns TWHAX AD8–15 Hold after WR High T OSC b 30 ns (4) TRHBX BHE, INST Hold after RD High T OSC b 10 ns TRHAX AD8–15 Hold after RD High T OSC b 30 ns (4) NOTES: 1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 Tosc c n, where n e number of wait states. If mode 0 (1 automatic wait state added) operation is selected, add 2 T OSC to specification. 6. T OFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detec- tion.

AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise anf Fall Times e 10 ns. The system must meet these specifications to work with the 87C196CA/CB. Symbol Parameter Min Max Units TAVYV Address Valid to Ready Setup 2 T OSC b 75 ns (3) TLLYV ALE Low to READY Setup T OSC b 70 ns (3) TYLYH Non READY Time No Upper Limit ns TCLYX READY Hold after CLKOUT Low 0 T OSC b 30 ns (1) TAVGV Address Valid to BUSWIDTH Setup 2 T OSC b 75 ns (2, 3) TLLGV ALE Low to BUSWIDTH Setup T OSC b 60 ns (2, 3) TCLGX BUSWIDTH Hold after CLKOUT Low 0 ns TAVDV Address Valid to Input Data Valid 3 T OSC b 55 ns (2) TRLDV RD active to input Data Valid CA T OSC b 22 ns (2) CB T OSC b 30 ns (2) TCLDV CLKOUT Low to Input Data Valid T OSC b 50 ns TRHDZ End of RD to Input Data Float T OSC ns TRHDX Data Hold after RD High 0 ns NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Tosc c n, where n e number of wait states. 3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the specification.

87C196CA/CB SYSTEM BUS TIMING 272405–17 * If mode 0 operation is selected, add 2 Tosc to this time.

87C196CA/CB READY TIMINGS (ONE WAIT STATE) 272405–18 *If mode 0 selected (CB only), one wait state is always added. If additional wait states are required, add 2 Tosc to these specifications. 87C196CB BUSWIDTH TIMINGS 272405–19 *If mode 0 selected (CB only), add 2 Tosc to these specifications.

8XC196CB HOLD/HOLDA TIMINGS (Over Specified Operation Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. Symbol Parameter Min Max Units THVCH HOLD Setup Time a65 ns (1) TCLHAL CLKOUT Low to HLDA Low b15 a15 ns TCLBRL CLKOUT Low to BREQ Low b15 a15 ns TAZHAL HLDA Low to Address Float a20 ns TBZHAL HLDA Low to BHE , INST, RD ,W R Weakly Driven a25 ns TCLHAH CLKOUT Low to HLDA High b15 a15 ns TCLBRH CLKOUT Low to BREQ High b25 a25 ns THAHAX HLDA High to Address No Longer Float b15 ns THAHBV HLDA High to BHE , INST, RD ,W R Valid b10 a15 ns NOTE: 1. To guarantee recognition at next clock. 8XC196CB HOLD /HOLDA TIMINGS 272405–20

8XC196CB AC CHARACTERISTICSÐSLAVE PORT SLAVE PORT WAVEFORMÐ(SLPL e 0) 272405–21 SLAVE PORT TIMINGÐ(SLPL e 0, 1, 2, 3) Symbol Parameter Min Max Units TSAVWL Address Valid to WR Low 50 ns TSRHAV RD High to Address Valid 60 ns TSRLRH RD Low Period T OSC ns TSWLWH WR Low Period T OSC ns TSRLDV RD Low to Output Data Valid 60 ns TSDVWH Input Data Setup to WR High 20 ns TSWHQX WR High to Data Invalid 30 ns TSRHDZ RD High to Data Float 15 ns NOTES: 1. Test Conditions: F OSC e 20 MHz, T OSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change.

AC CHARACTERISTICSÐSLAVE PORT (Continued) SLAVE PORT WAVEFORMÐ(SLPL e 1) 272405–22 SLAVE PORT TIMINGÐ(SLPL e 1, 2, 3) Symbol Parameter Min Max Units TSELLL CS Low to ALE Low 20 ns TSRHEH RD or WR High to CS High 60 ns TSLLRL ALE Low to RD Low T OSC ns TSRLRH RD Low Period T OSC ns TSWLWH WR Low Period T OSC ns TSAVLL Address Valid to ALE Low 20 ns TSLLAX ALE Low to Address Invalid 20 ns TSRLDV RD Low to Output Data Valid 60 ns TSDVWH Input Data Setup to WR High 20 ns TSWHQX WR High to Data Invalid 30 ns TSRHDZ RD High to Data Float 15 ns NOTES: 1. Test Conditions: F OSC e 20 MHz, T OSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change.

*Timings are guaranteed by design. *Timings are guaranteed by design.

1. This specification refers to input clocks during slave operation. During master operation, the device will output a nominal

The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal. to the latching edge of SCx. Figure 6. Synchronous Serial Port

Symbol Parameter Min Max Units 1/TXLXL Oscillator Frequency 4 20 MHz TXLXL Oscillator Period (T OSC) 50.0 250 ns TXHXX High Time 0.35 c TOSC 0.65 T OSC ns TXLXX Low Time 0.35 c TOSC 0.65 T OSC ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CLOCK DRIVE WAVEFORMS 272405–23 AC TESTING INPUT, OUTPUT WAVEFORMS 272405–24 AC Testing inputs are driven at 3.5V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’. Timing measurements are made at 2.0V for a logic ‘‘1’’ and 0.8V for logic ‘‘0’’. FLOAT WAVEFORMS 272405–25 For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading V OH/VOL level occurs I OL/IOH s 15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: Signals: HÐHigh AÐAddress HAÐHLDA LÐLow BÐBHE LÐALE/ADV VÐValid BRÐBREQ QÐData Out XÐNo Longer CÐCLKOUT RDÐRD Valid DÐDATA WÐWR /WRH/WRI ZÐFloating GÐBuswidth XÐXTAL1 HÐHOLD YÐREADY

AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions: Load Capacitance e 150 pF; T C e 25§C g5§C, V CC,V REF e 5.0V g0.5V, V SS, ANGND e 0V. Symbol Parameter Min Max Units TAVLL Address Setup Time 0 T OSC TLLAX Address Hold Time 100 T OSC TDVPL Data Setup Time 0 T OSC TPLDX Data Hold Time 400 T OSC TLLLH PALE Pulse Width 50 T OSC TPLPH PROG Pulse Width (2) CA 50 T OSC CB 100 T OSC TLHPL PALE High to PROG Low 220 T OSC TPHLL PROG High to next PALE Low 220 T OSC TPHDX Word Dump Hold Time 50 T OSC TPHPL PROG High to next PROG Low 220 T OSC TLHPL PALE High to PROG Low 220 T OSC TPLDV PROG Low to Word Dump Valid CA 50 T OSC CB 100 T OSC TSHLL RESET High to First PALE Low 1100 T OSC TPHIL PROG High to AINC Low 0 T OSC TILIH AINC Pulse Width 240 T OSC TILVH PVER Hold after AINC Low 50 T OSC TILPL AINC Low to PROG Low 170 T OSC TPHVL PROG High to PVER Valid 220 T OSC NOTES: 1. Run-time programming is done with Fosc e 6.0 MHz to 10.0 MHz, V CC,V PD,V REF e 5V g0.5V, T C e 25§C g5§C and VPP e 12.5V g0.25V. For run-time programming over a full operating range, contact factory. 2. Programming specifications are not tested, but guaranteed by design. 3. This specification is for the word dump mode. For programming pulses use 300 Tosc a 100 ms. DC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max Units IPP VPP Programming Supply Current 200 mA NOTE: VPP must be within 1V of V CC while V CC k 4.5V. V PP must not have a low impedance path to ground or V SS while V CC l 4.5V.

EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272405–26 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT 272405–27

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 272405–28 AC CHARACTERISTICSÐSERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMINGÐSHIFT REGISTER MODE 0 Test Conditions: T A eb 40§Ct o a125§C; V CC e 5.0V g10%; V SS e 0.0V; Load Capacitance e pF Symbol Parameter Min Max Units TXLXL Serial Port Clock Period 8 T OSC ns TXLXH Serial Port Clock Falling Edge to Rising Edge 4 T OSC b 50 4 T OSC a 50 ns TQVXH Output Data Setup to Clock Rising Edge 3 T OSC ns TXHQX Output Data Hold after Clock Rising Edge 2 T OSC b 50 ns TXHQV Next Output Data Valid after Clock Rising Edge 2 T OSC a 50 ns TDVXH Input Data Setup to Clock Rising Edge 2 T OSC a 200 ns TXHDX(8) Input Data Hold after Clock Rising Edge 0 ns TXHQZ(8) Last Clock Rising to Output Float 5 T OSC ns NOTE: 8. Parameters not tested.

WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE 272405–29 A TO D CHARACTERISTICS The sample and conversion time of the A/D convert- er in the 8-bit or 10-bit modes is programmed by loading a byte into the AD ÐTIME Special Function Register. This allows optimizing the A/D operation for specific applications. The AD ÐTIME register is functional for all possible values, but the accuracy of the A/D converter is only guaranteed for the times specified in the operating conditions table. The value loaded into AD ÐTIME bits 5, 6, 7 deter- mines the sample time, SAMP. The value loaded into AD ÐTIME bits 0, 1, 2, 3 and 4 determines the bit conversion time, CONV. These bits, as well as the equation for calculating the total conversion time, T, are shown in the following table: ADÐTIME 1FAFH:Byte 76543210 Sample Time Bit Conversion Time (SAMP) (CONV) 4n a 1 state times n a1 state times n e 1t o7 n e 2t o3 1 Equation: T e (SAMP) a Bx (CONV) a 2.5 T e total conversion time (states) B e number of bits conversion (8 or 10) n e programmed register value The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V REF. VREF must be close to V CC since it supplies both the resistor ladder and the analog portion of the convert- er and input port pins. There is also an AD ÐTEST SFR that allows for conversion on ANGND and V REF as well as adjusting the zero offset. The abso- lute error listed is without doing any adjustments. A/D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet. Test- ing is performed with V REF e 5.12V and 20 MHz operating frequency. After a conversion is started, the device is placed in IDLE mode until the conver- sion is complete.

10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b40 a125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V (1) TSAM Sample Time 2.0 ms(2) TCONV Conversion Time 15 18 ms(2) FOSC Oscillator Frequency 4.0 20.0 MHz NOTES: 1. V REF must be within 0.5V of V CC. 2. The value of AD ÐTIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions) (6) Parameter Typ *(1) Min Max Units * Resolution 1024 1024 Level 10 10 Bits Absolute Error 0 g3.0 LSBs Full Scale Error 0.25 g0.5 LSBs Zero Offset Error 0.25 g0.5 LSBs Non-Linearity 1.0 g2.0 g3.0 LSBs Differential Non-Linearity b0.75 a0.75 LSBs Channel-to-Channel Matching g0.1 0 g1.0 LSBs Repeatability g0.25 0 LSBs (1) Temperature Coefficients: Offset 0.009 LSB/C (1) Full Scale 0.009 LSB/C (1) Differential Non-Linearity 0.009 LSB/C (1) Off Isolation b60 dB (1,2,3) Feedthrough b60 dB (1,2) VCC Power Supply Rejection b60 dB (1,2) Input Resistance 750 1.2K X(4) DC Input Leakage g1.0 0 g3.0 mA Voltage on Analog Input Pin ANGND b 0.5 V REF a 0.5 V (5) Sampling Capacitor 3.0 pF *An ‘‘LSB’’ as used here has a value of approximately 5 mV. NOTES: 1. These values are expected for most parts at 25 §C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode.

8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b40 a125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V (1) TSAM Sample Time 2.0 ms(2) TCONV Conversion Time 12 15 ms(2) FOSC Oscillator Frequency 4.0 20.0 MHz NOTES: 1. V REF must be within 0.5V of V CC. 2. The value of AD ÐTIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions) (6) Parameter Typ *(1) Min Max Units * Resolution 256 256 Level 8 8 Bits Absolute Error 0 g1.0 LSBs Full Scale Error g0.5 LSBs Zero Offset Error g0.5 LSBs Non-Linearity 0 g1.0 LSBs Differential Non-Linearity b0.5 a0.5 LSBs Channel-to-Channel Matching 0 g1.0 LSBs Repeatability g0.25 0 LSBs (1) Temperature Coefficients: Offset 0.003 LSB/C (1) Full Scale 0.003 LSB/C (1) Differential Non-Linearity 0.003 LSB/C (1) Off Isolation b60 dB (1,2,3) Feedthrough b60 dB (1,2) VCC Power Supply Rejection b60 dB (1,2) Input Resistance 750 1.2K X(4) DC Input Leakage g1.0 0 g1.5 mA Voltage on Analog Input Pin ANGND b 0.5 V REF a 0.5 V (5) Sampling Capacitor 3.0 pF *An ‘‘LSB’’ as used here has a value of approximately 20 mV. NOTES: 1. These values are expected for most parts at 25 §C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode.

87C196CA DESIGN CONSIDERATIONS The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2.0. The CA is designed for strict functional and electrical com- patibility to the Kx family as well as integration of on- chip networking capability. The 87C196CA has few- er peripheral functions than the 196KR, due in part to the integration of the CAN peripheral. Following are the functionality differences between the 196KR and 196CA devices. 196KR Features Unsupported on the 196CA: Analog Channels 0 and 1 INST Pin Functionality SLPINT and SLPCS Pin Support HLD/HLDA Functionality External Clocking/Direction of Timer 1 Quadrature Clocking Timer 1 Dynamic Buswidth EPA Capture Channels 4–7 (1) External Memory. Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. The pro- grammer must define the bus mode by setting the associated bits in the CCB. (2) Auto-Programming Mode. The 87C196CA de- vice will ONLY support the 16-bit zero wait state bus during auto-programming. (3) EPA4 through EPA7. Since the CA device is based on the KR design, these functions are in the device, however there are no associated pins. A programmer can use these as compare- only channels or for other functions like software timer, start an A/D conversion, or reset timers. (4) Slave Port Support. The Slave port can not be used on the 196CA due to a function change for P5.4/SLPINT and P5.1/SLPCS not being bond- ed-out. (5) Port Functions. Some port pins have been re- and PxIO registers can still be updated and read. The programmer should not use the correspond- ing bits associated with the removed port pins to conditionally branch in software. Treat these bits as RESERVED. Additionally, these port pins should be setup in- ternally by software as follows: 1. Written to PxREG as ‘‘1’’ or ‘‘0’’. 2. Configured as Push/Pull, PxIO as ‘‘0’’. 3. Configured as LSIO. This configuration will effectively strap the pin either high or low. DO NOT Configure as Open Drain output ‘’1’’, or as an Input pin. This device is CMOS. (6) EPA Timer RESET/Write Conflict. If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. (7) Valid Time Matches. The timer must incre- ment/decrement to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. (8) Write Cycle during Reset. If RESET occurs dur- ing a write cycle, the contents of the external memory device may be corrupted. (9) Indirect Shift Instruction. The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. (10) P2.7 (CLKOUT). P2.7 (CLKOUT) does not op- erate in open drain mode.

This data sheet was published prior to first available silicon. Consequently, there is no known errata at this time. 87C196CA DESIGN CONSIDERATIONS 1. PORT0 On the 87C196CA the analog inputs for P0.0 and P0.1 have been multiplexed and tied to V REF. There- fore, initiating an analog conversion on ACH0 or ACH1 will result in a value equal to full scale (3FFh). On the CA, the digital inputs for these two channels are tied to ground, therefore, reading P0.0 or P0.1 will result in a digital ‘‘0’’. 2. PORT1 On the 87C196CA, P1.4, P1.5, P1.6 and P1.7 have been removed from the device and is unavailable to the programmer. Corresponding bits in the port reg- isters have been ‘‘hard-wired’’ to provide the follow- ing results when read: Register Bits When Read P1ÐPIN.x (x e 4,5,6,7) 1 P1ÐREG.x (x e 4,5,6,7) 1 P1ÐDIR.x (x e 4,5,6,7) 1 P1ÐMODE.x (x e 4,5,6,7) 0 Writing to these bits will have no effect. 3. PORT2 On the 87C196CA, P2.3 and P2.5 have been re- moved from the device and are not available to the programmer. Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following re- sults when read. Register Bits When Read P2ÐPIN.x (x e 3,5) 1 P2ÐREG.x (x e 3,5) 1 P2ÐDIR.x (x e 3,5) 1 P2ÐMODE.x (x e 3,5) 0 Writing to these bits will have no effect. 4. PORT5 On the 87C196CA, P5.1 and P5.7 have been re- moved from the device and are not available to the programmer. Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following re- sults when read: Register Bits When Read P5ÐPIN.x (x e 1,7) 1 P5ÐREG.x (x e 1,7) 1 P5ÐDIR.x (x e 1,7) 1 P5ÐMODE.x (x e 1) 0 P5ÐMODE.x (x e 7) 1 Writing to these bits will have no effect. 5. PORT6 On the 87C196CA, P6.2 and P6.3 have been re- moved from the device and are not available to the programmer. Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following re- sults when read: Register Bits When Read P6ÐPIN.x (x e 2,3) 1 P6ÐREG.x (x e 2,3) 1 P6ÐDIR.x (x e 2,3) 1 P6ÐMODE.x (x e 2,3) 0 Writing to these bits will have no effect.

DATA SHEET REVISION HISTORY This is the -003 revision of the 87C196CA/CB data sheet. The following differences exist between the -002 version and the -003 revision. 1. The data sheet has been revised to ADVANCE from PRELIMINARY, indicaitng the specifica- tions have been verified through electrical tests. 2. The 87C196CB 100-ld QFP package and device pinout has been added to the data sheet. 3. The 87C196CB 100-ld QFP device supports up the 16 Mbyte of linear address space. 4. The package thermal characteristics for the PLCC packages was added to the data sheet, for the CB i JA e 35.0§C/W, iJC e 11.0§C/W. For the CA, iJA e 36.5§C/W and iJA e 10.0§C/W. 5. The AN87C196CB pin package diagram was corrected to show EA Ý as opposed to EA. 6. The REMAP bit funciton for CCB2 was corrected. Setting this bit to 0 selects EPROM/ CODERAM in segment 0FFH only. Setting this bit to 1 selects both segment 0FFH and segment 00H. 7. t RLAZ has been changed to 5 ns from 20 ns. 8. t WLWH for the CA has been changed to t OSC b20 from t OSC b 30. 9. t CLGX has been changed to 0 ns min, from t OSC b 46 max. 10. Timing specifications for the SSIO are now add- ed. These timings are currently guaranteed by design. 11. Added frequency designation to family nomen- clature Figure 2. This is the -002 revision of the 87C196CA data sheet. The following difference exist between the -001 version and the -002 revision. 1. This data sheet now includes the specifications for the 87C196CB as well as the 87C196CA. 2. ABSOLUTE MAXIMUM RATINGS have been added. 3. Maximum Frequency has been increased to 20 MHz. 4. Maximum ICC has been increased from 75 mA to 100 mA for the CB, 90 mA for the CA. 5. Idle Mode current has been increased to 35 mA from 30 mA for the CB, 40 mA for the CA. 6. Input leakage current for Port 0 (ILI1) was de- creased to 1.5 mA from 2.0 mA for the CA. 7. The electrical characteristics for the CAN mod- ule were removed. The electrical characteristics for TXCAN and RXCAN are identical to standard port pins. 8. t OSC (1/freq) was modified to reflect 20 Mhz tim- ings. 9. t OFD (Oscillator Fail Detect Specification) for clock failure to RESET pin pulled low, was added to the data sheet (4 ms min, 40 ms max) 10. t WHQX has been increased to t OSC b 25 ns min from t OSC b 30 ns min. 11. t RXDX has been replaced by t RHDX.t RLAZ has been increased to 20 ns max from 5 ns max. 12. I PP programming supply current has been in- creased to 200 mA from 100 mA. 13. t CONV Conversion time for 10 bit A/D conver- sions has been decreased to reflect 20 Mhz op- eration. 14. R RST was added for the 87C196CA (min e 6 kX/max e 65 k X. 15. t CLLHÐmin/max parameters switched to accu- rately reflect this timing parameter. 16. t RLCLÐSeparate timings for the 87C196CA vs 87C196CB. t RLCL for the CB is min b8 ns, max a20 ns. For the CA, t RLCL min a4 ns/max a30 ns. 17. t RLRH changed to T OSC b 10 ns from T OSC b 5 ns. 18. t AVGV added for the 87C196CB. 19. t LLGV added for the 87C196CB. 20. t CLGX added for the 87C196CB. 21. t RLDVÐSeparate timings for 87C196CB. t RLDV max e TOSC b 30 ns. For the 87C196CA, tRLDV max e TOSC b 22 ns. 22. HOLD/HOLDA timings added for the 87C196CB. 23. Slave Port Timings added for the 87C196CB. 24. Separate specifications for t PLPH for the 87C196CB, t PLPH, min e 100 T OSC. For the 87C196CA, t PLPH min e 50 T OSC. 25. Separate specificatons for t PLDV for the 87C196CB, t PLDV min e 100 T OSC for the 87C196CA, t PLDV min e 50 T OSC. 26. 8-Bit mode A/D characteristics added.