87C151SB INTEL | Alldatasheet
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Technical content
b40§Ct o a85§C device operation. for the 8XC151SA/SB family nomenclature. Table 1. Proliferation Options ty and Reliability Handbook (order number 210997). mal impedance test methodology. Table 2. Thermal Characteristics Table 3 lists the 8XC151SA/SB packages. Table 3. Package Information
Figure 2. The 8XC151SA/SB Family Nomenclature Table 4. Description of Product Nomenclature
7 User programmable OTPROM
Figure 3. 8XC151SA/SB 44-Lead PLCC Package
Figure 4. 8XC151SA/SB 40-Pin PDIP and Ceramic DIP Packages
Table 5. PLCC/DIP Signal Assignment Arranged by Functional Categories
Table 6. Signal Assignments Arranged by Package Number
Table 7. Signal Descriptions address from the address/data bus. PCA compare mode and PCA PWM mode. are set by a low level on INT1:0 Ý. for programming the on-chip OTPROM. the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
Table 7. Signal Descriptions (Continued) configuration byte UCONFIG0. returns the chip to normal operation. mode 0 and receives data in serial I/O modes 1, 2, and 3. counter, a falling edge on the T1:0 pin increments the count. 0 and transmits serial data in serial I/O modes 1, 2, and 3. applied to this pin for programming the on-chip OTPROM. the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
is the clock source for internal timing. an external oscillator is used, leave XTAL2 unconnected. the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature under Bias: Commercial ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§Ct o a70§C Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA Ý/VPP Pin to V SS ÀÀÀÀÀ0V to a13.0V Voltage on Any other Pin to V SS ÀÀÀb0.5V to a6.5V IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W NOTE: Maximum power dissipation is based on package heat-transfer limitations, not device power con- sumption. OPERATING CONDITIONS * TA (Ambient Temperature Under Bias): Commercial ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§Ct o a70§C Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C VCC (Digital Supply Voltage) ÀÀÀÀÀÀÀÀÀÀ4.5V to 5.5V VSS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V NOTICE: This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised infor- mation will be published when the product is avail- able. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.
Parameter values apply to all devices unless otherwise indicated. Table 8. DC Characteristics at V CC e 4.5V b 5.5V
- Under steady-state (non-transient) conditions, I OL must be externally limited as follows:
greater than the listed test conditions.
- Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and
- Capacitive loading on ports 0 and 2 causes the V
address lines are stabilizing.
- Typical values are obtained using V CC e 5.0, T A e 25§C and are not guaranteed.
Table 8. DC Characteristics at V CC e 4.5V b 5.5V (Continued)
- Under steady-state (non-transient) conditions, I OL must be externally limited as follows:
greater than the listed test conditions.
- Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and
- Capacitive loading on ports 0 and 2 causes the V
address lines are stabilizing.
- Typical values are obtained using V CC e 5.0, T A e 25§C and are not guaranteed.
All other 8XC151SA/SB pins are unconnected. Figure 5. I PD Test Condition, Powerdown Mode, V CC e 2.0V b 5.5V
by a PSEN Ý/RDÝ/WRÝ wait state. Table 9. AC Characteristics (Capacitive Loading e 50 pF) Ý are identical to those for RD Ý.
- In the formula, M eNumber of wait states (0 or 1) for ALE.
- In the formula, N eNumber of wait states (0, 1, 2, or 3) for RD Ý/PSENÝ/WRÝ.
- ‘‘Typical’’ specifications are untested and not guaranteed.
Table 9. AC Characteristics (Capacitive Loading e 50 pF) (Continued) Ý are identical to those for RD Ý.
- In the formula, M eNumber of wait states (0 or 1) for ALE.
- In the formula, N eNumber of wait states (0, 1, 2, or 3) for RD Ý/PSENÝ/WRÝ.
- ‘‘Typical’’ specifications are untested and not guaranteed.
Ý are identical to those for RD Ý.
- In the formula, M eNumber of wait states (0 or 1) for ALE.
- In the formula, N eNumber of wait states (0, 1, 2, or 3) for RD Ý/PSENÝ/WRÝ.
- ‘‘Typical’’ specifications are untested and not guaranteed.
²The value of this parameter depends on wait states. See the table of AC characteristics. Figure 6. External Read Data Bus Cycle in Nonpage Mode
²The value of this parameter depends on wait states. See the table of AC characteristics. Figure 7. External Instruction Bus Cycle in Nonpage Mode
²The value of this parameter depends on wait states. See the table of AC characteristics. Figure 8. External Write Data Bus Cycle in Nonpage Mode
²The value of this parameter depends on wait states. See the table of AC characteristics. Figure 9. External Read Data Bus Cycle in Page Mode
²The value of this parameter depends on wait states. See the table of AC characteristics. Figure 10. External Write Data Bus Cycle in Page Mode
² The value of this parameter depends on wait states. See the table of AC characteristics. a page miss requires two states (4T OSC). ²²² During a sequence of page hits, PSEN Ý remains low until the end of the last page-hit cycle. Figure 11. External Instruction Bus Cycle in Page Mode
Table 10. Serial Port Timing Shift Register Mode ² TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit. Figure 12. Serial Port Waveform ÐShift Register Mode
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER PROGRAMMING AND VERIFYING NONVOLATILE MEMORY The 87C151SA/SB has several areas of nonvolatile memory that can be programmed and/or verified: on-chip code memory (8/16 Kbytes), lock bits (3 bits), encryption array (128 bytes), and signature bytes (3 bytes). Figure 16 shows the setup for programming and/or verifying the nonvolatile memory. Table 11 lists the programming and verification operations and indi- cates which operations apply to the different ver- sions of the 87C151SA/SB. It also specifies the sig- nals on the programming input (PROG Ý) and the ports. The ROM/OTPROM mode (port 0) specifies the operation (program or verify) and the base ad- dress of the memory area. The addresses (ports 1 and 3) are relative to the base address. (On-chip memory for a 16-Kbyte ROM/OTPROM device is lo- cated at address range 0000H–3FFFH. The other areas of the ROM/OTPROM are outside the memo- ry address space and are accessible only during pro- gramming and verification.) Information in Figures 17 and 18 define the configu- ration bits. Figure 19 shows the waveforms for the programming and verification cycles, and Table 12 lists the timing specifications. The signature bytes of the 83C151SA/SB ROM versions and the 87C151SA/SB OTPROM versions are factory pro- grammed. Table 13 lists the addresses and the con- tents of the signature bytes. Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte in- formation from external application memory based on an internal address range of FFF9:8H. NOTE: The V PP source in Figure 16 must be well regu- lated and free of glitches. The voltage on the V PP pin must not exceed the specified maximum, even under transient conditions.
Table 12. Programming and Verification Modes Mode
- The PROG Ý pulse waveform is shown in Figure 19.
- Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a
information from external application memory based on an internal address range of FFF9:8H.
- When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with the address as follows:
- The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously at port 2 as
4 XALE Ý Extend Ale:
1 PAGE Ý Page Mode Select:
(compatible with MCS 51 microcontrollers)). information from external application memory based on an internal address range of FFF9:8H. Figure 17. Configuration Byte 0
7:5 Ð Reserved; set these bits when writing to UCONFIG1. information from external application memory based on an internal address range of FFF9:8H. Figure 18. Configuration Byte 1
Figure 19. Timing for Programming and Verification of Nonvolatile Memory
Table 13. Nonvolatile Memory Programming and Verification Characteristics at Table 14. Contents of the Signature Bytes