TN83C196MD

87C196MD INTEL | Alldatasheet

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This device is manufactured on PX29.5, a CHMOS III-E process. Additional process and reliability infor- mation is available in the Intel® Quality System Handbook. 272323– 2 NOTE: EPROMs are available as One Time Programmable (OTPROM) only. Figure 2.The 8XC196MD Family Nomenclature Table 1.ThermalCharacteristics Package θja θjcType PLCC 35°C/W 13 °C/W QFP 56°C/W 12 °C/W All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. Table 2.8XC196MD Memory Map Description Address External Memory or I/O 0FFFFH 06000H Internal ROM/EPROM or External 5FFFH Memory (Determined by EA) 2080H Reserved. Must contain FFH. 207FH (Note 5) 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM/EPROM Security Key 202FH 2020H Reserved. Must contain FFH. 201FH (Note 5) 201CH Reserved. Must Contain 20H 201BH (Note 5) CCB1 201AH Reserved. Must Contain 20H 2019H (Note 5) CCB0 2018H Reserved. Must contain FFH. 2017H (Note 5) 2014H Lower Interrupt Vectors 2013H 2000H SFR’s 1FFFH 1F00H External Memory 1EFFH 0200H

488 Bytes Register RAM (Note 1) 01FFH

CPU SFR’s (Notes 1. 3) 0017H 0000H NOTES: 1. Code executed in locations 0000H to 01FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196MC for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these lo- cations may change with future revisions of the device. Therefore, aprogram that relies on one or more of these locations may not function properly. xx

Table 3. Interrupt Sources, Vectors and Priorities served vectors in the 8XC196MC User’s Manual. where FG Frequency is from 4 kHz to 1 MHz. FGÐCOUNT can only be read, not written. Table 4. Port 7 Special Function Pins Table 5. Port 7 Special Function Registers

P1.7) that were not available on the 8XC196MC. Table 6. New 8XC196MD Port 1 Pins

272323–3 NOTE: NC means No Connect. Do not connect these pins. Figure 6.84-Lead PLCC Package

272323–4 Figure 7.80-Lead Shrink EIAJQFP(Quad FlatPack)

PIN DESCRIPTIONS (Alphabetically Ordered) Symbol Function ACH0–ACH13 Analog inputs to the on-chip A/D converter. ACH0–7 share the input pins the port pins can be used as standard input ports. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as V SS. ALE/ADV(P5.0) Address Latch Enable or Address Valid output, as selected by CCR. Both options allow a latch to demultiplex the address/data bus on the signal’s falling edge. When the pin is ADV , it goes inactive (high) at the end of the bus cycle. ALE/ADV is active only during external memory accesses. Can be used as standard I/O when not used as ALE/ADV. BHE/WRH (P5.5) Byte High Enable or Write High output, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE /WRH is activated only during external memory writes. BUSWIDTH (P5.7) Input for bus width selection. If CCR bits 1 and 2 e 1, this pin dynamically controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as standard I/O when not used as BUSWIDTH. CAPCOMP0–CAPCOMP5 The EPA Capture/Compare pins. CAPCOMP0–3 share the pins with EPA, they can be configured as standard I/O pins. CLKOUT Output of the internal clock generator. The frequency is (/2 of the oscillator frequency. It has a 50% duty cycle. COMPARE0–COMPARE5 The EPA Compare pins. COMPARE0–3 share the pins with P2.4–P2.7. can be configured as standard I/O pins. EA External Access enable pin. EA e 0 causes all memory accesses to be external to the chip. EA e 1 causes memory accesses from location 2000H to 5FFFH to be from the on-chip OTPROM/ROM. EA e 12.5V causes execution to begin in the programming mode. EA is latched at reset. EXTINT A programmable input on this pin causes a maskable interrupt vector through memory location 203CH. The input may be selected to be a positive/negative edge or a high/low level using WG ÐPROTECT (1FCEH). FREQOUT Programmable frequency output pin. The frequency can vary from 4 KHz to 1 MHz (16 MHz input clock). It has a 50% duty cycle. Pin may be configured as standard I/O if FREQOUT is not used. INST (P5.1) INST is high during the instruction fetch from the external memory and throughout the bus cycle. It is low otherwise. This pin can be configured as standard I/O if not used as INST. NMI A positive transition on this pin causes a non-maskable interrupt which vectors to memory location 203EH. If not used, it should be tied to V SS. May be used by Intel Evaluation boards. PORT0 8-bit high impedance input-only port. Also used as A/D converter inputs. Port0 pins should not be left floating. These pins also used to select programming modes in the OTPROM devices. PORT1 8-bit high impedance input-only port. P1.0–P1.5 are also used as A/D converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock input and direction select respectively. P1.6–P1.7 can be used as input-only pins.

PIN DESCRIPTIONS (Alphabetically Ordered) (Continued) Symbol Function PORT2 8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O pins (CAPCOMP0–3 and COMPARE0–3). PORT3 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which uses strong internal pullups.PORT4 PORT5 8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals (ALE, INST, WR ,R D , BHE , READY, BUSWIDTH). Can be used as standard I/O. PORT6 8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave Form Generator outputs. Can be used as standard output ports. PORT7 8-bit bidirectional I/O port. P7.0–P7.3 can be used as EPA I/O pins (CAPCOMP4–5 and COMPARE4–5). P7.7 can be used as FREQOUT output pin. P7.4–P7.6 are standard I/O pins. PWM0, PWM1 Programmable duty cycle, Programmable frequency Pulse Width Modulator pins. The duty cycle has a resolution of 256 steps, and the frequency can vary(P6.6, P6.7) from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as standard output if PWM is not used. RD (P5.3) Read signal output to external memory. RD is low only during external memory reads. Can be used as standard I/O when not used as RD . READY (P5.6) Ready input to lengthen external memory cycles. If READY e 0, the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY e 1. Can be used as standard I/O when not used as READY. RESET Reset input to and open-drain output from the chip. Held low for at least 16 state times to reset the chip. Input high for normal operation. RESET has an Ohmic internal pullup resistor. T1CLK Timer 1 Clock input. This pin has two other alternate functions: ACH10 and P1.2.(P1.2) T1DIR Timer 1 Direction input. This pin has two other alternate functions: ACH11 and P1.3.(P1.3) VPP The programming voltage is applied to this pin. It is also the timing pin for the return from Power Down circuit. Connect this pin with a 1 mF capacitor to V SS a n da1M X resistor to V CC. If the Power Down feature is not used, connect the pin to V CC. WG1–WG3/WG1 –WG3 3 phase output signals and their complements used in motor control applications. The pins can also be configured as standard output pins.(P6.0–P6.5) WR/WRL (P5.2) Write and Write Low output to external memory. WR will go low every external write. WRL will go low only for external writes to an even byte. Can be used as standard I/O when not used as WR /WRL. XTAL1 Input of the oscillator inverter and the internal clock generator. This pin should be used when using an external clock source. XTAL2 Output of the oscillator inverter. PMODE Determines the EPROM programming mode. (P0.4–7) PACT A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete.(P2.5)

PIN DESCRIPTIONS (Alphabetically Ordered) (Continued) Symbol Function PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming(P2.1) address/command information (input to slave). PROG A falling edge in Slave Programming Mode begins programming. A rising edge ends programming.(P2.2) PVER A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly.(P2.0) CPVER Cumulative Program Verification. Pin is high if all locations since entering a programming mode have programmed correctly.(P2.6) AINC Auto Increment. Active low input enables the auto increment mode. Auto increment will allow reading or writing of sequential EPROM locations without(P2.4) address transactions across the PBUS for each read or write.

Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage from EA or V PP to V SS or ANGND ÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a13.00V Voltage on Any Other Pin to V SS or ANGND ÀÀÀÀÀÀÀÀÀÀÀ b0.5V to a7.0V(1) Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (2) NOTES: 1. This includes V PP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer lim- itations, not device power consumption. NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature Under Bias b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V FOSC Oscillator Frequency 8 16 MHz NOTE: ANGND and V SS should be nominally at the same potential. Also V SS and V SS1 must be at the same potential. DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 0.3 V CC V VIH Input High Voltage 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.3 V I OL e 200 mA Port 2, 5, and 7, P6.6, P6.7, 0.45 V I OL e 3.2 mA CLKOUT 1.5 V I OL e 7m A VOL1 Output Low Voltage on Port 3/4 1.0 V I OL e 15 mA VOL2 Output Low Voltage on 0.45 V I OL e 10 mA Port 6.0–6.5 VOH Output High Voltage V CC b 0.3 V I OH eb 200 mA VCC b 0.7 V I OH eb 3.2 mA VCC b 1.5 V I OH eb 7m A Vtha –Vthb Hysteresis Voltage Width on 0.2 V Typical RESET

DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Symbol Parameter Min Typ Max Units Test Conditions ILI Input Leakage Current on All Input g10 mA0 V k VIN k VCC –0.3V (in RESET) Only Pins ILI1 Input Leakage Current on Port0 g3 mA0 V k VIN k VREF and Port1 IIL Input Low Current on BD Ports b70 mAV IN e 0.3 V CC (Note 1) IIL1 Input Low Current on P5.4 and b10 mA 0.2 V CC P2.6 during Reset (Note 3) IOH Output High Current on P5.4 and b2 mA 0.7 V CC P2.6 during Reset (Note 4) ICC Active Mode Current in Reset 50 70 mA XTAL1 e 16 MHz, IREF A/D Conversion Reference Current 2 5 mA VCC e VPP e VREF e 5.5V IIDL Idle Mode Current 15 30 mA IPD Power-Down Mode Current 5 50 mAV CC e VPP e VREF e 5.5V RRST RESET Pin Pullup Resistor 6k 65k X CS Pin Capacitance (Any Pin to V SS)1 0 p F F TEST e 1.0 MHz NOTES: 1. BD (Bidirectional ports) include: P2.0–P2.7, except P2.6 P3.0–P3.7 P4.0–P4.7 P5.0–P5.3 P5.5–P5.7 P7.0–P7.7 2. During normal (non-transient) conditions, the following total current limits apply: P6.0–P6.5 I OL:4 0 m A I OH:2 8 m A P3 I OL:9 0 m A I OH:4 2 m A P4 I OL:9 0 m A I OH:4 2 m A P5, CLKOUT I OL:3 5 m A I OH:3 5 m A P2, P6.6, P6.7, P7 I OL:6 3 m A I OH:6 3 m A 3. Maximum current that must be sunk by external device to ensure test mode entry. 4. Do not exceed minimum current or device may enter test mode.

Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: Signals: H Ð High L Ð Low V Ð Valid X Ð No Longer Valid Z Ð Floating A Ð Address B Ð BHE C Ð CLKOUT D Ð DATA G Ð Buswidth H Ð HOLD HA Ð HLDA L Ð ALE/ADV BR Ð BREQ RÐ R D WÐ W R /WRH/WRL X Ð XTAL1 Y Ð READY Q Ð Data Out AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 16 MHz. The system must meet the following specifications to work with the 87C196MD: Symbol Parameter Min Max Units Notes FXTAL Frequency on XTAL1 8 16 MHz 3 TOSC 1/FXTAL 62.5 125 ns TAVYV Address Valid to READY Setup 2 T OSC b 75 ns TLLYV ALE Low to READY Setup T OSC b 70 ns 4 TYLYH Not READY Time No Upper Limit ns TCLYX READY Hold after CLKOUT Low 0 T OSC b 30 ns 1 TLLYX READY Hold after ALE Low T OSC b 15 2 T OSC b 40 ns 1 TAVGV Address Valid to BUSWIDTH Setup 2 T OSC b 75 ns TLLGV ALE Low to BUSWIDTH Setup T OSC b 60 ns 4 TCLGX Buswidth Hold after CLKOUT Low 0 ns TAVDV Address Valid to Input Data Valid 3 T OSC b 55 ns 2 TRLDV RD Active to Input Data Valid T OSC b 22 ns 2 TCLDV CLKOUT Low to Input Data Valid T OSC b 50 ns TRHDZ End of RD to Input Data Float T OSC ns TRXDX Data Hold after RD Inactive 0 ns NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 T OSC * N, where N e number of wait states. 3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 4. These timings are included for compatibility with older b90 and BH products. They should not be used for newer high- speed designs.

AC ELECTRICAL CHARACTERISTICS (Continued) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, F OSC e 16 MHz. The 87C196MD will meet the following timing specifications: Symbol Parameter Min Max Units Notes TXHCH XTAL1 to CLKOUT High or Low 30 110 ns TCLCL CLKOUT Cycle Time 2 T OSC ns TCHCL CLKOUT High Period T OSC b 10 T OSC a 15 ns TCLLH CLKOUT Falling Edge to ALE Rising b51 5 n s TLLCH ALE Falling Edge to CLKOUT Rising b20 15 ns TLHLH ALE Cycle Time 4 T OSC ns 3 TLHLL ALE High Period T OSC b 10 T OSC a 10 ns TAVLL Address Setup to ALE Falling Edge T OSC b 15 ns TLLAX Address Hold after ALE Falling T OSC b 40 ns TLLRL ALE Falling Edge to RD Falling T OSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge 4 30 ns TRLRH RD Low Period T OSC b 5T OSC a 25 ns 3 TRHLH RD Rising Edge to ALE Rising Edge T OSC TOSC a 25 ns 1 TRLAZ RD Low to Address Float 5 ns TLLWL ALE Falling Edge to WR Falling T OSC b 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 25 ns TQVWH Data Stable to WR Rising Edge T OSC b 23 ns TCHWH CLKOUT High to WR Rising Edge b10 15 ns TWLWH WR Low Period T OSC b 30 ns 3 TWHQX Data Hold after WR Rising Edge T OSC b 25 ns TWHLH WR Rising Edge to ALE Rising Edge T OSC b 10 T OSC a 15 ns 1 TWHBX BHE, INST Hold after WR Rising T OSC b 10 ns TWHAX AD8–15 Hold after WR Rising T OSC b 30 ns 2 TRHBX BHE, INST Hold after RD Rising T OSC b 10 ns TRHAX AD8–15 Hold after RD Rising T OSC b 30 ns 2 NOTES: 1. Assuming back to back cycles. 2. 8-bit bus only. 3. If wait states are used, add 2 T OSC*N, where N e number of wait states.

272323–5

READY TIMINGS (One Wait State) 272323–6 BUSWIDTH TIMINGS 272323–7

Symbol Parameter Min Max Units 1/TXLXL Oscillator Frequency 8 16.0 MHz TXLXL Oscillator Period 62.5 125 ns TXHXX High Time 22 ns TXLXX Low Time 22 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CRYSTAL CONNECTIONS 272323–8 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and V SS. When using crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators, consult manufacturer for recom- mended circuitry. EXTERNAL CLOCK CONNECTIONS 272323–9 * Required if TTL driver used. Not needed if CMOS driver is used. EXTERNAL CLOCK DRIVE WAVEFORMS 272323–10 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the V IL and VIH specifications the capacitance will not exceed 20 pF. AC TESTING INPUT, OUTPUT WAVEFORMS 272323–11 AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. FLOAT WAVEFORMS 272323–12 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded V OH/VOL Level occurs IOL/IOH e g15 mA.

The sample and conversion time of the A/D convert- er in the 8-bit or 10-bit modes is programmed by loading a byte into the AD ÐTIME Special Function Register. This allows optimizing the A/D operation for specific applications. The AD ÐTIME register is functional for all possible values, but the accuracy of the A/D converter is only guaranteed for the times specificed in the operating conditions table. The value loaded into AD ÐTIME bits 5, 6, 7 deter- mines the sample time, T SAM, and is calculated us- ing the following formula: SAM e (TSAM c FOSC) b 2 TSAM e Sample time, ms FOSC e Processor frequency, MHz SAM e Value loaded into AD ÐTIME bits 5, 6, 7 SAM must be in the range 1 through 7. The value loaded into AD ÐTIME bits 0–5 deter- mines the conversion time, T CONV, and is calculated using the following formula: CONV e (TCONV c FOSC) b 3 b 1 TCONV e Conversion time, ms FOSC e Processor frequency, MHz B e 8 for 8-bit conversion B e 10 for 10-bit conversion CONV e Value loaded into AD ÐTIME bits 0–5 CONV must be in the range 2 through 31. The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V REF. VREF must be close to V CC since it supplies both the resistor ladder and the analog portion of the convert- er and input port pins. There is also an AD ÐTEST SFR that allows for conversion on ANGND and V REF as well as adjusting the zero offset. The abso- lute error listed is WITHOUT doing any adjustments. A/D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet. Test- ing is performed with V REF e 5.12V and 16.0 MHz operating frequency. After a conversion is started, the device is placed in the IDLE mode until the con- version is complete.

10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V (1) TSAM Sample Time 1.0 ms(2) TCONV Conversion Time 10.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz NOTES: ANGND and V SS should nominally be at the same potential. 1. V REF must be within 0.5V of V CC. 2. The value of AD ÐTIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions) Parameter Typical (1) Min Max Units * Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 g4 LSBs Full Scale Error 0.25 g0.5 LSBs Zero Offset Error 0.25 g0.5 LSBs Non-Linearity 1.0 g2.0 g4 LSBs Differential Non-Linearity lb1 a2 LSBs Channel-to-Channel Matching g0.1 0 g1.0 LSBs Repeatability g0.25 0 LSBs Temperature Coefficients: Offset 0.009 LSB/C Full Scale 0.009 LSB/C Differential Non-Linearity 0.009 LSB/C Off Isolation b60 dB (2, 3) Feedthrough b60 dB (2) VCC Power Supply Rejection b60 dB (2) Input Series Resistance 750 2K X(4) Voltage on Analog Input Pin ANGND b 0.5 V REF a 0.5 V (5, 6) Sampling Capacitor 3 pF DC Input Leakage g10 g3.0 mA NOTES: *An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode.

8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b40 a85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V (1) TSAM Sample Time 1.0 ms(2) TCONV Conversion Time 7.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz NOTES: ANGND and V SS should nominally be at the same potential. 1. V REF must be within 0.5V of V CC. 2. The value of AD ÐTIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Over the Above Operating Conditions) Parameter Typical (1) Min Max Units * Resolution 256 256 Level 8 8 Bits Absolute Error 0 g1 LSBs Full Scale Error g0.5 LSBs Zero Offset Error g0.5 LSBs Non-Linearity 0 g1 LSBs Differential Non-Linearity lb1 a1 LSBs Channel-to-Channel Matching 0 g1.0 LSBs Repeatability g0.25 LSBs Temperature Coefficients: Offset 0.003 LSB/C Full Scale 0.003 LSB/C Differential Non-Linearity 0.003 LSB/C Off Isolation b60 dB (2, 3) Feedthrough b60 dB (2) VCC Power Supply Rejection b60 dB (2) Input Series Resistance 750 2K X(4) Voltage on Analog Input Pin V SSb 0.5 V REF a 0.5 V (5, 6) Sampling Capacitor 3 pF DC Input Leakage g10 g3.0 mA NOTES: *An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25 §C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode.

OPERATING CONDITIONS DURING PROGRAMMING Symbol Description Min Max Units TA Ambient Temperature during Programming 20 30 §C VCC Supply Voltage during Programming 4.5 5.5 V (1) VREF Reference Supply Voltage during Programming 4.5 5.5 V (1) VPP Programming Voltage 12.25 12.75 V (2) VEA EA Pin Voltage 12.25 12.75 V (2) FOSC Oscillator Frequency during Auto 6.0 8.0 MHz and Slave Mode Programming TOSC Oscillator Frequency during 6.0 12.0 MHz Run-Time Programming NOTES: 1. V CC and V REF should nominally be at the same voltage during programming. 2. V PP and V EA must never exceed the maximum specification, or the device may be damaged. 3. V SS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol Parameter Min Max Units TSHLL Reset High to First PALE Low 1100 T OSC TLLLH PALE Pulse Width 50 T OSC TAVLL Address Setup Time 0 T OSC TLLAX Address Hold Time 100 T OSC TPLDV PROG Low to Word Dump Valid 50 T OSC TPHDX Word Dump Data Hold 50 T OSC TDVPL Data Setup Time 0 T OSC TPLDX Data Hold Time 400 T OSC TPLPH(1) PROG Pulse Width 50 T OSC TPHLL PROG High to Next PALE Low 220 T OSC TLHPL PALE High to PROG Low 220 T OSC TPHPL PROG High to Next PROG Low 220 T OSC TPHIL PROG High to AINC Low 0 T OSC TILIH AINC Pulse Width 240 T OSC TILVH PVER Hold after AINC Low 50 T OSC TILPL AINC Low to PROG Low 170 T OSC TPHVL PROG High to PVER Valid 220 T OSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.

DC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max Units IPP VPP Supply Current (When Programming) 100 mA NOTE: Do not apply V PP until V CC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 2723231–13 NOTE: P3.0 must be high (‘‘1’’)

SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 272323–14 NOTE: P3.0 must be low (‘‘0’’) SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 272323–15

When an indirect shift during divide occurs the upper 3 bits of the shift count are not masked completely. If the shift count register has the value 32 * n where n e 1, 3, 5or 7. the operand will be shifted 32 times. This should have resulted in no shift taking place. 8XC196MC to8XC196MD Design Considerations 8XC196MC and 8XC196MD are pin compatible. However, there were several pins that were not con- nected (NC) on the 8XC196MC that are I/O pins on the 8XC196MD. Port 7is abidirectional port added to the 8XC196MD. Port 1 has one additional analog or digital input that was connected to V SS on the 8XC196MC. Port 1also has two additional digital in- puts. See 8XC196MC and 8XC196MD Differences Section of this data sheet. DATA SHEET REVISION HISTORY Document 272323-003 was updated due to changes required for the lead free initiative. To address the fact that many of the package prefix variables have changed, all package prefix variables in the document are now indicated with an "x".