28F001BX-T INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 290406-007 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B Y High-Integration Blocked Architecture Ð One 8 KB Boot Block w/Lock Out Ð Two 4 KB Parameter Blocks Ð One 112 KB Main Block Y 100,000 Erase/Program Cycles Per Block Y Simplified Program and Erase Ð Automated Algorithms via On-Chip Write State Machine (WSM) Y SRAM-Compatible Write Interface Y Deep Power-Down Mode Ð 0.05 mAI CC Typical Ð 0.8 mAI PP Typical Y 12.0V g5% V PP Y High-Performance Read Ð 70/75 ns, 90 ns, 120 ns, 150 ns Maximum Access Time Ð 5.0V g10% V CC Y Hardware Data Protection Feature Ð Erase/Write Lockout during Power Transitions Y Advanced Packaging, JEDEC Pinouts Ð 32-Pin PDIP Ð 32-Lead PLCC, TSOP Y ETOXTM II Nonvolatile Flash Technology Ð EPROM-Compatible Process Base Ð High-Volume Manufacturing Experience Y Extended Temperature Options Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase. These devices aid the system designer by combining the functions of several components into one, making boot block flash an innovative alternative to EPROM and EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the 28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor interface. The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of 8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations pro- vide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s MCS É-186 family, 80286, i386 TM, i486 TM, i860 TM and 80960CA. With exactly the same memory segmentation, the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory, such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document. The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high- performance access speeds, low power consumption, and immunity to noise. Its access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown mode lowers power consumption to 0.25 mW typical through V CC, crucial in laptop computer, handheld instru- mentation and other low-power applications. The RP Ý power control input also provides absolute data protec- tion during system powerup or power loss. Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness. NOTE: The 28F001BN is equivalent to the 28F001BX.
Figure 1. 28F001BX Block Diagram Table 1. Pin Description outputs are disabled. Data is internally latched during a write cycle. reduces power consumption to standby levels. from deep powerdown sets device to Read Array mode. is active low. Addresses and data are latched on the rising edge of the WE Ý pulse.
290406–4 Figure 4. PLCC Lead Configuration
APPLICATIONS
The 28F001BX flash ‘boot block’ memory augments the non-volatility, in-system electrical erasure and reprogrammability of Intel’s standard flash memory by offering four separately erasable blocks and inte- grating a state machine to control erase and pro- gram functions. The specialized blocking architec- ture and automated programming of the 28F001BX provide a full-function, non-volatile flash memory ideal for a wide range of applications, including PC boot/BIOS memory, minimum-chip embedded pro- gram memory and parametric data storage. The 28F001BX combines the safety of a hardware-pro- tected 8-KByte boot block with the flexibility of three separately reprogrammable blocks (two 4-KByte pa- rameter blocks and one 112-KByte code block) into one versatile, cost-effective flash memory. Addition- ally, reprogramming one block does not affect code stored in another block, ensuring data integrity. The flexibility of flash memory reduces costs throughout the life cycle of a design. During the early stages of a system’s life, flash memory reduces pro- totype development and testing time, allowing the system designer to modify in-system software elec- trically versus manual removal of components. Dur- ing production, flash memory provides flexible firm- ware for just-in-time configuration, reducing system inventory and eliminating unnecessary handling and less reliable socketed connections. Late in the life cycle, when software updates or code ‘‘bugs’’ are often unpredictable and costly, flash memory reduc- es update costs by allowing the manufacturers to send floppy updates versus a technician. Alterna- tively, remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory’s fast programming time.
PP can be at either V PPL or V PPH. device powerup or after exit from deep powerdown. must be logically active to obtain data at the outputs. illustrates read bus cycle waveforms. placed in a high-impedance state. power until the operation is completed. other command can be written. Table 2. 28F001BX Bus Operations
- Refer to DC Characteristics. When V PP e VPPL, memory contents can be read but not programmed or erased.
- X can be V IL or V IH for control pins and addresses, and V PPL or V PPH for V PP.
- See DC Characteristics for V PPL,V PPH,V HH and V ID voltages.
- Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A 1 –A8,
- Device ID e 94H for the 28F001BX-T and 95H for the 28F001BX-B.
- Command writes involving block erase or byte program are successfully executed only when V PP e VPPH.
- Refer to Table 3 for valid D IN during a write operation.
- Program or erase the boot block by holding RP Ý at V HH or toggling OE Ý to V HH. See AC Waveforms for program/erase
The use of RP Ý during system reset is important with automated write/erase devices. When the sys- tem comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during write/ erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intel’s Flash Memories allow proper CPU initialization fol- lowing a system reset through the use of the RP Ý input. In this application RP Ý is controlled by the same RESET Ý signal that resets the system CPU. Intelligent Identifier Operation The Intelligent Identifier operation outputs the manu- facturer code, 89H; and the device code, 94H for the 28F001BX-T and 95H for the 28F001BX-B. Pro- gramming equipment or the system CPU can then automatically match the device with its proper erase and programming algorithms. PROGRAMMING EQUIPMENT CE Ý and OE Ý at a logic low level (V IL), with A 9 at high voltage V ID (see DC Characteristics) activates this operation. Data read from locations 00000H and 00001H represent the manufacturer’s code and the device code respectively. IN-SYSTEM PROGRAMMING The manufacturer- and device-codes can also be read via the Command Register. Following a write of 90H to the Command Register, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the de- vice code (94H for the 28F001BX-T and 95H for the 28F001BX-B). It is not necessary to have high volt- age applied to V PP to read the Intelligent Identifiers from the Command Register. Write Writes to the Command Register allow read of de- vice data and Intelligent Identifiers. They also con- trol inspection and clearing of the Status Register. Additionally, when V PP e VPPH, the Command Reg- ister controls device erasure and programming. The contents of the register serve as input to the internal state machine. The Command Register itself does not occupy an addressable memory location. The register is a latch used to store the command and address and data information needed to execute the command. Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Program Setup Com- mand requires both appropriate command data and the address of the location to be programmed, while the Program command consists of the data to be written and the address of the location to be pro- grammed. The Command Register is written by bringing WE Ý to a logic-low level (V IL) while CE Ý is low. Address- es and data are latched on the rising edge of WE Ý. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the AC Wave- form for Write Operations, Figure 13, for specific tim- ing parameters. COMMAND DEFINITIONS When V PPL is applied to the V PP pin, read opera- tions from the Status Register, intelligent identifiers, or array blocks are enabled. Placing V PPH on V PP enables successful program and erase operations as well. Device operations are selected by writing specific commands into the Command Register. Table 3 de- fines these 28F001BX commands. Read Array Command Upon initial device powerup and after exit from deep-powerdown mode, the 28F001BX defaults to Read Array mode. This operation is also initiated by writing FFH into the Command Register. Microproc- essor read cycles retrieve array data. The device re- mains enabled for reads until the Command Regis- ter contents are altered. Once the internal write state machine has started an erase or program op- eration, the device will not recognize the Read Array command, until the WSM has completed its opera- tion. The Read Array command is functional when V PP e VPPL or V PPH. Intelligent Identifier Command for In-System Programming The 28F001BX contains an Intelligent Identifier op- eration to supplement traditional PROM-program- ming methodology. The operation is initiated by writ- ing 90H into the Command Register. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cy- cle from address 00001H returns the device code of 94H (28F001BX-T) or 95H (28F001BX-B). To termi- nate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is func- tional when V PP e VPPL or V PPH.
Table 3. 28F001BX Command Definitions
- Bus operations are defined in Table 2.
e Identifier Address: 00H for manufacturer code, 01H for device code. BA e Address within the block being erased. PA e Address of memory location to be programmed.
- SRD e Data read from Status Register. See Table 4 for a description of the Status Register bits.
PD e Data to be programmed at location PA. Data is latched on the rising edge of WE Ý. IID e Data read from Intelligent Identifiers.
- Following the Intelligent Identifier command, two read operations access manufacture and device codes.
- Commands other than those shown above are reserved by Intel for future device implementations and should not be
bits indicate various failure conditions (see Table 4). the way the device may be used. ther byte programs or block erases are attempted.
Table 4. 28F001BX Status Register Definitions masked out when polling the Status Register. Program or Erase Status bits are checked for success. was entered. Attempt the operation again. Status bit of the Status Register (SR.7). and should not be attempted. pended (both will be set to ‘‘1s’’). (see Figure 11; Erase Suspend/Resume Flowchart).
Program Setup/Program Commands Programming is executed by a two-write sequence. The program Setup command (40H) is written to the Command Register, followed by a second write specifying the address and data (latched on the ris- ing edge of WE Ý) to be programmed. The WSM then takes over, controlling the program and verify algorithms internally. After the two-command pro- gram sequence is written to it, the 28F001BX auto- matically outputs Status Register data when read (see Figure 9; Byte Program Flowchart). The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register. Only the Read Status Register command is valid while programming is active. When the Status Register indicates that program- ming is complete, the Program Status bit should be checked. If program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for ‘‘1s’’ that do not successfully program to ‘‘0s’’. The Command Register remains in Read Status Register mode until further commands are issued to it. If byte program is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. Program attempts while V PPL k VPP k VPPH pro- duce spurious results and should not be attempted. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. Howev- er, redundancy requires that cell size be doubled; an expensive solution. Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. Second, the oxide area per cell subjected to the tunneling electrical field is one- tenth that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 Mv/cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failure. The 28F001BX-B and 28F001BX-T are capable of 100,000 program/erase cycles on each parameter block, main block and boot block. ON-CHIP PROGRAMMING ALGORITHM The 28F001BX integrates the Quick Pulse program- ming algorithm of prior Intel Flash Memory devices on-chip, using the Command Register, Status Regis- ter and Write State Machine (WSM). On-chip inte- gration dramatically simplifies system software and provides processor-like interface timings to the Command and Status Registers. WSM operation, in- ternal program verify and V PP high voltage presence are monitored and reported via appropriate Status Register bits. Figure 9 shows a system software flowchart for device programming. The entire se- quence is performed with V PP at V PPH. Program abort occurs when RP Ý transitions to V IL,o rV PP drops to V PPL. Although the WSM is halted, byte data is partially programmed at the location where programming was aborted. Block erasure or a re- peat of byte programming will initialize this data to a known value. ON-CHIP ERASE ALGORITHM As above, the Quick Erase algorithm of prior Intel Flash Memory devices is now implemented internal- ly, including all preconditioning of block data. WSM operation, erase success and V PP high voltage pres- ence are monitored and reported through the Status Register. Additionally, if a command other than Erase Confirm is written to the device after Erase Setup has been written, both the Erase Status and Program Status bits will be set to ‘‘1’’. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 10 shows a system software flowchart for block erase. Erase typically takes 1–4 seconds per block. The Erase Suspend/Erase Resume command sequence allows interrupt of this erase operation to read data from a block other than that in which erase is being performed . A system software flowchart is shown in Figure 11. The entire sequence is performed with V PP at V PPH. Abort occurs when RP Ý transitions to V IL or V PP falls to V PPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. 11
tion being attempted and indicating boot block lock. Repeat for subsequent bytes. reset the device to Read Array Mode. programmed before full status is checked. attempting retry or other error recovery. Figure 9. 28F001BX Byte Programming Flowchart
Repeat for subsequent blocks. attempts are allowed by the Write State Machine. where multiple blocks are erased before full status is checked. Figure 10. 28F001BX Block Erase Flowchart
Figure 11. 28F001BX Erase Suspend/Resume Flowchart Ý can return to normal TTL levels.
Flash memory power switching characteristics re- quire careful device coupling. System designers are interested in 3 supply current issues; standby current levels (I SB), active current levels (I CC) and transient peaks producted by falling and rising edges of CE Ý. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 mF ceramic capacitor connected between its V CC and GND, and between its V PP and GND. These high frequency, low inherent-induc- tance capacitors should be placed as close as pos- sible to the device. Additionally, for every 8 devices, a 4.7 mF electrolytic capacitor should be placed at the array’s power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. VPP Trace on Printed Circuit Boards Programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the V PP power sup- ply trace. The V PP pin supplies the memory cell cur- rent for programming. Use similar trace widths and layout considerations given to the V CC power bus. Adequate V PP supply traces and decoupling will de- crease V PP voltage spikes and overshoots. VCC,V PP,R P Ý Transitions and the Command/Status Registers Programming and erase completion are not guaran- teed if V PP drops below V PPH. If the V PP Status bit of the Status Register (SR.3) is set to ‘‘1’’, a Clear Status Register command MUST be issued before further program/erase attempts are allowed by the WSM. Otherwise, the Program (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to ‘‘1’’ if error is detected. RP Ý transitions to V IL during program and erase also abort the operations. Data is partially altered in either case, and the com- mand sequence must be repeated after normal op- eration is restored. Device poweroff, or RP Ý tran- sitions to V IL, clear the Status Register to initial val- ue 80H. The Command Register latches commands as is- sued by system software and is not altered by V PP or CE Ý transitions or WSM actions. Its state upon powerup, after exit from Deep-Powerdown or after V CC transitions below V LKO, is FFH, or Read Array Mode. After program or erase is complete, even after V PP transitions down to V PPL, the Command Register must be reset to read array mode via the Read Array command if access to the memory array is desired. Power Up/Down Protection The 28F001BX is designed to offer protection against accidental erasure or programming during power transitions. Upon power-up, the 28F001BX is indifferent as to which power supply, V PP or V CC, powers up first. Power supply sequencing is not re- quired. Internal circuitry in the 28F001BX ensures that the Command Register is reset to Read Array mode on power up. A system designer must guard against spurious writes for V CC voltages above V LKO when V PP is active. Since both WE Ý and CE Ý must be low for a command write, driving either to V IH will inhibit writes. The Command Register architecture provides an added level of protection since alteration of mem- ory contents only occurs after successful completion of the two-step command sequences. Finally, the device is disabled, until RP Ý is brought to V IH, regardless of the state of its control inputs. This provides an additional level of protection. 28F001BX Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases us- able battery life because the 28F001BX does not consume any power to retain code or data when the system is off. In addition, the 28F001BX’s Deep-Powerdown mode ensures extremely low power dissipation even when system power is applied. For example, laptop and other PC applications, after copying BIOS to DRAM, can lower RP Ý to V IL, producing negligible power consumption. If access to the boot code is again needed, as in case of a system RESET Ý, the part can again be accessed, following the t PHAV wakeup cycle required after RP Ý is first raised back to V IH. The first address presented to the device while in powerdown requires time t PHAV, after RP Ý tran- sitions high, before outputs are valid. Further ac- cesses follow normal timing. See AC Characteris- ticsÐRead-Only Operations and Figure 12 for more information.
ABSOLUTE MAXIMUM RATINGS * Operating Temperature During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 §Ct o7 0 §C(1) During Erase/Program ÀÀÀÀÀÀÀÀÀÀÀ0 §Ct o7 0 §C(1) Operating Temperature During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b40§Ct o a85§C(2) During Erase/Program ÀÀÀÀÀÀ b40§Ct o a85§C(2) Temperature under Bias ÀÀÀÀÀÀÀÀÀ b10§Ct o8 0 §C(1) Temperature under Bias ÀÀÀÀÀÀÀ b20§Ct o a90§C(2) Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀÀ b65§Ct o1 2 5 §C Voltage on Any Pin (except A 9,R P Ý,O E Ý,V CC and V PP) with Respect to GND ÀÀÀÀÀÀÀÀÀÀ b2.0V to 7.0V (3) Voltage on A 9,R P Ý, and OE Ý with Respect to GND ÀÀÀÀÀÀÀ b2.0V to 13.5V (3, 4) VPP Program Voltage with Respect to GND During Erase/Program ÀÀÀÀÀÀ b2.0V to 14.0V (3, 4) VCC Supply Voltage with Respect to GND ÀÀÀÀÀÀÀÀÀÀ b2.0V to 7.0V (3) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (5) NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Parameter Min Max Unit TA Operating Temperature (1) 07 0 §C TA Operating Temperature (2) b40 85 §C VCC Supply Voltage 4.50 5.50 V NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Operating temperature is for extended temperature product defined by this specification. 3. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods k20 ns. Maximum DC voltage on input/output pins is V CC a0.5V which, during transitions, may overshoot to V CC a 2.0V for periods k20 ns. 4. Maximum DC voltage on A 9 or V PP may overshoot to a14.0V for periods k20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. DC CHARACTERISTICS VCC e 5.0V g10%, T A e 0§Ct o a70§C Symbol Parameter Notes Min Typ Max Unit Test Conditions IIL Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1.2 2.0 mA V CC e VCC Max CEÝ e RPÝ e VIH 30 100 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V ICCD VCC Deep Power-Down Current 1 0.05 1.0 mAR P Ý e GND g0.2V
DC CHARACTERISTICS (Continued) VCC e 5.0V g10%, T A e 0§Ct o a70§C Symbol Parameter Notes Min Typ Max Unit Test Conditions ICCR VCC Read Current 1 13 30 mA V CC e VCC Max, CE Ý e VIL f e 8 MHz, I OUT e 0m A ICCP VCC Programming Current 1 5 20 mA Programming in Progress ICCE VCC Erase Current 1 6 20 mA Erase in Progress ICCES VCC Erase Suspend Current 1, 2 5 10 mA Erase Suspended CEÝ e VIH IPPS VPP Standby Current 1 g1 g10 mAV PP s VCC 90 200 mAV PP l VCC IPPD VPP Deep Power-Down Current 1 0.80 1.0 mAR P Ý e GND g0.2V IPPP VPP Programming Current 1 6 30 mA V PP e VPPH Programming in Progress IPPE VPP Erase Current 1 6 30 mA V PP e VPPH Erase in Progress IPPES VPP Erase Suspend Current 1 90 300 mAV PP e VPPH Erase Suspended IID A9 Intelligent Identifier Current 1 90 500 mAA 9 e VID VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH Output High Voltage 2.4 V V CC e VCC Min IOH e 2.5 mA VID A9 Intelligent Identifier Voltage 11.5 13.0 V VPPL VPP during Normal Operations 3 0.0 6.5 V VPPH VPP during Prog/Erase Operations 11.4 12.0 12.6 V VLKO VCC Erase/Write Lock Voltage 2.5 V VHH RPÝ,O E Ý Unlock Voltage 11.4 12.6 V Boot Block Prog/Erase NOTES: are valid for all product versions (packages and speeds). 2. I CCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the sum of I CCES and I CCR. 3. Erase/Programs are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL.
VCC e 5.0V g10%, T A eb 40§Ct o a85§C Symbol Parameter Notes Min Typ Max Unit Test Conditions IIL Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1.2 2.0 mA V CC e VCC Max CEÝ e RPÝ e VIH 30 150 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V ICCD VCC Deep Power-Down Current 1 0.05 2.0 mAR P Ý e GND g0.2V ICCR VCC Read Current 1 13 35 mA V CC e VCC Max, CE Ý e VIL f e 8 MHz, I OUT e 0m A ICCP VCC Programming Current 1 5 20 mA Programming in Progress ICCE VCC Erase Current 1 6 20 mA Erase in Progress ICCES VCC Erase Suspend Current 1, 2 5 10 mA Erase Suspended CEÝ e VIH IPPS VPP Standby Current 1 g1 g15 mAV PP s VCC 90 400 mAV PP l VCC IPPD VPP Deep Power-Down Current 1 0.80 1.0 mAR P Ý e GND g0.2V IPPP VPP Programming Current 1 6 30 mAV PP e VPPH Programming in Progress IPPE VPP Erase Current 1 6 30 mA V PP e VPPH Erase in Progress IPPES VPP Erase Suspend Current 1 90 400 mAV PP e VPPH Erase Suspended IID A9 Intelligent Identifier Current 1 90 500 mAA 9 e VID VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CCa0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage (TTL) 2.4 V V CC e VCC Min IOH e 2.5 mA VOH2 Output High Voltage (CMOS) 0.85 V CC VV CC e VCC Min IOH eb 2.5 mA VCCb0.4 V CC e VCC Min IOH eb 100 mA VID A9 Intelligent Identifier Voltage 11.5 13.0 V VPPL VPP during Normal Operations 3 0.0 6.5 V VPPH VPP during Prog/Erase Operations 11.4 12.0 12.6 V VLKO VCC Erase/Write Lock Voltage 2.5 V VHH RPÝ,O E Ý Unlock Voltage 11.4 12.6 V Boot Block Prog/Erase
NOTES: are valid for all product versions (packages and speeds). 2. I CCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the sum of I CCES and I CCR. 3. Erase/Programs are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL. CAPACITANCE(1) TA e 25§C, f e 1 MHz Symbol Parameter Max Unit Conditions CIN Input Capacitance 8 pF V IN e 0V COUT Output Capacitance 12 pF V OUT e 0V NOTE: 1. Sampled, not 100% tested. AC INPUT/OUTPUT REFERENCE WAVEFORM 290406–10 STANDARD TEST CONFIGURATION AC TESTING LOAD CIRCUIT 290406–11 CL e 100 pF CL Includes Jig Capacitance RL e 3.3 k X HIGH SPEED TEST CONFIGURATION AC TESTING LOAD CIRCUIT 290406–23 CL e 30 pF CL Includes Jig Capacitance RL e 3.3 k X
AC CHARACTERISTICSÐRead-Only Operations (1) Symbol Parameter Notes 28F001BX-70 28F001BX-90 Units VCC e 5V V CC e 5V V CC e 5V g5% g10% g10% 30 pF 100 pF 100 pF Min Max Min Max Min Max tAVAV tRC Read Cycle Time 70 75 90 ns tAVQV tACC Address to Output Delay 70 75 90 ns tELQV tCE CEÝ to Output Delay 2 70 75 90 ns tPHQV tPWH RPÝ to Output Delay 600 600 600 ns tGLQV tOE OEÝ to Output Delay 2 27 30 35 ns tELQX tLZ CEÝ to Output in Low Z 3 0 0 0 ns tEHQZ tHZ CEÝ to Output in High Z 3 55 55 35 ns tGLQX tOLZ OEÝ to Output in Low Z 3 0 0 0 ns tGHQZ tDF OEÝ to Output in High Z 3 30 30 30 ns tOH Output Hold from 3 0 0 0 ns Address CE Ý,o rO E Ý Change, Whichever Occurs First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE Ý may be delayed up to t CE –tOE after the falling edge of CE Ý without impact on t CE. 3. Sampled, but not 100% tested. 4. See High Speed Test Configuration. 5. See Standard Test Configuration.
AC CHARACTERISTICSÐRead-Only Operations (1) E28F001BX-150 Unit E28F001BX-120 TE28F001BX-150 Versions(2) VCC g10% N28F001BX-120 N28F001BX-150 P28F001BX-120 TN28F001BX-150 P28F001BX-150 Symbol Parameter Notes Min Max Min Max tAVAV tRC Read Cycle Time 120 150 ns tAVQV tACC Address to Output Delay 120 150 ns tELQV tCE CEÝ to Output Delay 3 120 150 ns tPHQV tPWH RPÝ High to Output Delay 600 600 ns tGLQV tOE OEÝ to Output Delay 3 50 55 ns tELQX tLZ CEÝ to Output Low Z 4 0 0 ns tEHQZ tHZ CEÝ High to Output High Z 4 55 55 ns tGLQX tOLZ OEÝ to Output Low Z 4 0 0 ns tGHQZ tDF OEÝ High to Output High Z 4 30 30 ns tOH Output Hold from 4 0 0 ns Addresses, CE Ý or OE Ý Change, Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. Model Number Prefixes: E e TSOP (Standard Pinout), N e PLCC, P e PDIP, T e Extended Temperature. Refer to standard test configuration. 3. OE Ý may be delayed up to t CE –tOE after the falling edge of CE Ý without impact on t CE. 4. Sampled, not 100% tested.
Figure 12. AC Waveform for Read Operations
AC CHARACTERISTICSÐWrite/Erase/Program Operations (1, 9) Symbol Parameter Notes 28F001BX-70 28F001BX-90 Units VCC e 5V V CC e 5V V CC e 5V 30 pF 100 pF 100 pF Min Max Min Max Min Max tAVAV tWC Write Cycle Time 70 75 90 ns tPHWL tPS RPÝ High Recovery to WE Ý 2 480 480 480 ns Going Low tELWL tCS CEÝ Setup to WE Ý Going Low 10 10 10 ns tWLWH tWP WEÝ Pulse Width 35 40 40 ns tPHHWH tPHS RPÝ VHH Setup to WE Ý Going 2 100 100 100 ns High tVPWH tVPS VPP Setup to WE Ý Going High 2 100 100 100 ns tAVWH tAS Address Setup to WE Ý Going 3 35 40 40 ns High tDVWH tDS Data Setup to WE Ý Going High 4 35 40 40 ns tWHDX tDH Data Hold from WE Ý High 10 10 10 ns tWHAX tAH Address Hold from WE Ý High 10 10 10 ns tWHEH tCH CEÝ Hold from WE Ý High 10 10 10 ns tWHWL tWPH WEÝ Pulse Width High 35 35 35 ns tWHQV1 Duration of Programming 5, 6, 7 15 15 15 ms Operation tWHQV2 Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec (Boot) tWHQV3 Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec (Parameter) tWHQV4 Duration of Erase Operation 5, 6, 7 3.0 3.0 3.0 sec (Main) tWHGL Write Recovery before Read 0 0 0 ms tQVVL tVPH VPP Hold from Valid SRD 2, 6 0 0 0 ns tQVPH tPHH RPÝ VHH Hold from Valid SRD 2, 7 0 0 0 ns tPHBR Boot-Block Relock Delay 2 100 100 100 ns NOTES: 1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte programming or block erasure. 4. Refer to Table 3 for valid D IN for byte programming or block erasure. 5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. Program and erase durations are measured to completion (SR.7 e 1). V PP should be held at V PPH until determination of program/erase success (SR.3/4/5 e 0). 7. For boot block programming and erasure, RP Ý should be held at V HH until determination of program/erase success (SR.3/4/5 e 0). 8. Alternate boot block access method. 9. Erase/Program Cycles on extended temperature products is 10,000 cycles. 10. See high speed test configuration. 11. See standard test configuration.
AC CHARACTERISTICSÐWrite/Erase/Program Operations (1, 9) Versions V CC g10%(10) 28F001BX-120 28F001BX-150 Unit Symbol Parameter Notes Min Max Min Max tAVAV tWC Write Cycle Time 120 150 ns tPHWL tPS RPÝ High Recovery to WE Ý Going Low 2 480 480 ns tELWL tCS CEÝ Setup to WE Ý Going Low 10 10 ns tWLWH tWP WEÝ Pulse Width 50 50 ns tPHHWH tPHS RPÝ VHH Setup to WE Ý Going High 2 100 100 ns tVPWH tVPS VPP Setup to WE Ý Going High 2 100 100 ns tAVWH tAS Address Setup to WE Ý Going High 3 50 50 ns tDVWH tDS Data Setup to WE Ý Going High 4 50 50 ns tWHDX tDH Data Hold from WE Ý High 10 10 ns tWHAX tAH Address Hold from WE Ý High 10 10 ns tWHEH tCH CEÝ Hold from WE Ý High 10 10 ns tWHWL tWPH WEÝ Pulse Width High 50 50 ns tWHQV1 Duration of Programming Operation 5, 6, 7 15 15 ms tWHQV2 Duration of Erase Operation (Boot) 5, 6, 7 1.3 1.3 sec tWHQV3 Duration of Erase Operation (Parameter) 5, 6, 7 1.3 1.3 sec tWHQV4 Duration of Erase Operation (Main) 5, 6, 7 3.0 3.0 sec tWHGL Write Recovery before Read 0 0 ms tQVVL tVPH VPP Hold from Valid SRD 2, 6 0 0 ns tQVPH tPHH RPÝ VHH Hold from Valid SRD 2, 7 0 0 ns tPHBR Boot-Block Relock Delay 2 100 100 ns PROM Programmer Specifications Versions V CC g10% 28F001BX-120 28F001BX-150 Unit Symbol Parameter Notes Min Max Min Max tGHHWL OEÝ VHH Setup to WE Ý Going Low 2, 8 480 480 ns tWHGH OEÝ VHH Hold from WE Ý High 2, 8 480 480 ns NOTES: 1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte programming or block erasure. 4. Refer to Table 3 for valid D IN for byte programming or block erasure. 5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. Program and erase durations are measured to completion (SR.7 e 1). V PP should be held at V PPH until determination of program/erase success (SR.3/4/5 e 0). 7. For boot block programming and erasure, RP Ý should be held at V HH until determination of program/erase success (SR.3/4/5 e 0). 8. Alternate boot block access method. 9. Erase/Program Cycles on extended temperature products is 10,000 cycles. 10. See standard test configuration.
ERASE AND PROGRAMMING PERFORMANCE Parameter Notes 28F001BX-120 28F001BX-150 Unit Min Typ (1) Max Min Typ (1) Max Boot Block Erase Time 2 2.10 14.9 2.10 14.9 Sec Boot Block Program Time 2 0.15 0.52 0.15 0.52 Sec Parameter Block Erase Time 2 2.10 14.6 2.10 14.6 Sec Parameter Block Program Time 2 0.07 0.26 0.07 0.26 Sec Main Block Erase Time 2 3.80 20.9 3.80 20.9 Sec Main Block Program Time 2 2.10 7.34 2.10 7.34 Sec Chip Erase Time 2 10.10 65 10.10 65 Sec Chip Program Time 2 2.39 8.38 2.39 8.38 Sec NOTES: 1. 25 §C, 12.0 V PP. 2. Excludes System-Level Overhead.
Figure 17. AC Waveform for Write Operations
Figure 18. Alternate Boot Block Access Method Using OE Ý
AC CHARACTERISTICS FOR CE Ý-CONTROLLED WRITES (1) Symbol Parameter Notes 28F001BX-70 28F001BX-90 Units VCC e 5V V CC e 5V V CC e 5V 30 pF 100 pF 100 pF Min Max Min Max Min Max tAVAV tWC Write Cycle Time 70 75 90 ns tPHEL tPS RPÝ High Recovery to CE Ý 2 480 480 480 ns Going Low tWLEL tWS WEÝ Setup to CE Ý Going Low 0 0 0 ns tELEH tCP CEÝ Pulse Width 50 55 55 ns tPHHEH tPHS RPÝ VHH Setup to CE Ý Going 2 100 100 100 ns High tVPEH tVPS VPP Setup to CE Ý Going High 2 100 100 100 ns tAVEH tAS Address Setup to CE Ý Going 3 35 40 40 ns High tDVEH tDS Data Setup to CE Ý Going High 4 35 40 40 ns tEHDX tDH Data Hold from CE Ý High 10 10 10 ns tEHAX tAH Address Hold from CE Ý High 10 10 10 ns tEHWH tWH WEÝ Hold from CE Ý High 0 0 0 ns tEHEL tEPH CEÝ Pulse Width High 20 20 20 ns tEHQV1 Duration of Programming 5, 6 15 15 15 ms Operation tEHQV2 Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec (Boot) tEHQV3 Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec (Parameter) tEHQV4 Duration of Erase Operation 5, 6 3.0 3.0 3.0 sec (Main) tEHGL Write Recovery before Read 0 0 0 ms tQVVL tVPH VPP Hold from Valid SRD 2, 5 0 0 0 ns tQVPH tPHH RPÝ VHH Hold from Valid SRD 2, 6 0 0 0 ns tPHBR Boot-Block Relock Delay 2 100 100 100 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE Ý and WE Ý. In systems where CEÝ defines the write pulse width (within a longer WE Ý timing waveform), all set-up, hold and inactive WE Ý times should be measured relative to the CE Ý waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte programming or block erasure. 4. Refer to Table 3 for valid D IN for byte programming or block erasure. 5. Program and erase durations are measured to completion (SR.7 e 1). V PP should be held at V PPH until determination of program/erase success (SR.3/4/5 e 0). 6. For boot block programming and erasure, RP Ý should be held at V HH until determination of program/erase success (SR.3/4/5 e 0). 7. Alternate boot block access method. 8. See high speed test configuration. 9. See standard text configuration.
AC CHARACTERISTICS FOR CE Ý-CONTROLLED WRITES (1) Versions V CC g10% 28F001BX-120 28F001BX-150 Unit Symbol Parameter Notes Min Max Min Max tAVAV tWC Write Cycle Time 120 150 ns tPHEL tPS RPÝ High Recovery to CE Ý Going Low 2 480 480 ns tWLEL tWS WEÝ Setup to CE Ý Going Low 0 0 ns tELEH tCP CEÝ Pulse Width 70 70 ns tPHHEH tPHS RPÝ VHH Setup to CE Ý Going High 2 100 100 ns tVPEH tVPS VPP Setup to CE Ý Going High 2 100 100 ns tAVEH tAS Address Setup to CE Ý Going High 3 50 50 ns tDVEH tDS Data Setup to CE Ý Going High 4 50 50 ns tEHDX tDH Data Hold from CE Ý High 10 10 ns tEHAX tAH Address Hold from CE Ý High 15 15 ns tEHWH tWH WEÝ Hold from CE Ý High 0 0 ns tEHEL tEPH CEÝ Pulse Width High 25 25 ns tEHQV1 Duration of Programming Operation 5, 6 15 15 ms tEHQV2 Duration of Erase Operation (Boot) 5, 6 1.3 1.3 sec tEHQV3 Duration of Erase Operation (Parameter) 5, 6 1.3 1.3 sec tEHQV4 Duration of Erase Operation (Main) 5, 6 3.0 3.0 sec tEHGL Write Recovery before Read 0 0 ms tQVVL tVPH VPP Hold from Valid SRD 2, 5 0 0 ns tQVPH tPHH RPÝ VHH Hold from Valid SRD 2, 6 0 0 ns tPHBR Boot-Block Relock Delay 2 100 100 ns PROM Programmer Specifications Versions V CC g10% 28F001BX-120 28F001BX-150 Unit Symbol Parameter Notes Min Max Min Max tGHHEL OEÝ VHH Setup to CE Ý Going Low 2, 7 480 480 ns tEHGH OEÝ VHH Hold from CE Ý High 2, 7 480 480 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE Ý and WE Ý. In systems where CEÝ defines the write pulse width (within a longer WE Ý timing waveform), all set-up, hold and inactive WE Ý times should be measured relative to the CE Ý waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte programming or block erasure. 4. Refer to Table 3 for valid D IN for byte programming or block erasure. 5. Program and erase durations are measured to completion (SR.7 e 1). V PP should be held at V PPH until determination of program/erase success (SR.3/4/5 e 0). 6. For boot block programming and erasure, RP Ý should be held at V HH until determination of program/erase success (SR.3/4/5 e 0). 7. Alternate boot block access method.
Figure 19. Alternate AC Waveform for Write Operations
ORDERING INFORMATION
290406–18 VALID COMBINATIONS: 32-Lead TSOP 32-Lead PLCC 32-Pin PDIP Commercial E28F001BX-T70 N28F001BX-T70 P28F001BX-T70 E28F001BX-T90 N28F001BX-T90 P28F001BX-T90 E28F001BX-T120 N28F001BX-T120 P28F001BX-T120 E28F001BX-T150 N28F001BX-T150 P28F001BX-T150 E28F001BX-B70 N28F001BX-B70 P28F001BX-B70 E28F001BX-B90 N28F001BX-B90 P28F001BX-B90 E28F001BX-B120 N28F001BX-B120 P28F001BX-B120 E28F001BX-B150 N28F001BX-B150 P28F001BX-B150 Extended TE28F001BX-T90 TN28F001BX-T90 TP28F001BX-T90 TE28F001BX-T150 TN28F001BX-T150 TP28F001BX-B90 TE28F001BX-B90 TN28F001BX-B90 TE28F001BX-B150 TN28F001BX-B150 ADDITIONAL INFORMATION References Order Number Document
292046 AP-316 ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
292077 AP-341 ‘‘Designing an Updateable BIOS Using Flash Memory’’
292161 AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’
292178 AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’
294005 ER-20 ‘‘ETOX II Flash Memory Technology’’
Revision History
-004 Removed Preliminary classification. Latched address A 16 in Figure 5. Updated Boot Block Program and Erase section: ‘‘If boot block program or erase is attempted while RP Ý is at V IH, either the Program Status or Erase Status bit will be set to ‘‘1’’, reflective of the operation being attempted and indicating boot block lock.’’ Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart Added DC Characteristics typical current values Combined V PP Standby current and V PP Read current into one V PP Standby current spec with two test conditions (DC Characteristics table) Added maximum program/erase times to Erase and Programming Performance table. Added Figures 13–16 Added Extended Temperature proliferations -005 PWD changed to RP Ý for JEDEC standardization compatibility Revised symbols, i.e.; CE ,O E , etc. to CE Ý,O E Ý, etc. -006 Added specifications for -90 and -70 product versions. Added V OH CMOS Specification. -007 Added reference to 28F001BN.