TF28F008SA-100

28F008SA INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 290429-005 28F008SA 8-MBIT (1-MBIT x 8) FlashFile TM MEMORY Extended Temperature Specifications Included Y High-Density Symmetrically-Blocked Architecture Ð Sixteen 64-Kbyte Blocks Y Extended Cycling Capability Ð 100,000 Block Erase Cycles Ð 1.6 Million Block Erase Cycles per Chip Y Automated Byte Write and Block Erase Ð Command User Interface Ð Status Register Y System Performance Enhancements Ð RY/BY Ý Status Output Ð Erase Suspend Capability Y Deep Power-Down Mode Ð 0.20 mAI CC Typical Y Very High-Performance Read Ð 85 ns Maximum Access Time Y SRAM-Compatible Write Interface Y Hardware Data Protection Feature Ð Erase/Write Lockout during Power Transitions Y Industry Standard Packaging Ð 40-Lead TSOP, 44-Lead PSOP Y ETOX III Nonvolatile Flash Technology Ð 12V Byte Write/Block Erase Intel’s 28F008SA 8-Mbit FlashFile TM Memory is the highest density nonvolatile read/write solution for sol- id-state storage. The 28F008SA’s extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The 28F008SA brings new capabilities to porta- ble computing. Application and operating system software stored in resident flash memory arrays provide instant-on, rapid execute-in-place and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high density data acquisition applications, the 28F008SA offers a more cost-effective and reliable alterna- tive to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the 28F008SA’s nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages. Pin assign- ments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks. Intel’s 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media. A deep powerdown mode lowers power consumption to 1 mW typical thru V CC, crucial in portable computing, handheld instrumentation and other low-power applications. The RP Ý power control input also provides absolute data protection during system powerup/down. Manufactured on Intel’s 0.8 micron ETOX process, the 28F008SA provides the highest levels of quality, reliability and cost-effectiveness.

The 28F008SA is a high-performance 8-Mbit (8,388,608 bit) memory organized as 1 Mbyte (1,048,576 bytes) of 8 bits each. Sixteen 64-Kbyte (65,536 byte) blocks are included on the 28F008SA. A memory map is shown in Figure 6 of this specifica- tion. A block erase operation erases one of the six- teen blocks of memory in typically 1.6 seconds , in- dependent of the remaining blocks. Each block can be independently erased and written 100,000 cy- cles. Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the 28F008SA. The 28F008SA is available in the 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick) and 44- lead PSOP (Plastic Small Outline) packages. Pin- outs are shown in Figures 2 and 4 of this specifica- tion. The Command User Interface serves as the inter- face between the microprocessor or microcontroller and the internal operation of the 28F008SA. Byte Write and Block Erase Automation allow byte write and block erase operations to be execut- ed using a two-write command sequence to the Command User Interface. The internal Write State Machine (WSM) automatically executes the algo- rithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or micro- controller. Writing of memory data is performed in byte increments typically within 9 ms, an 80% im- provement over current flash memory products. I PP byte write and block erase currents are 10 mA typical, 30 mA maximum. V PP byte write and block erase voltage is 11.4V to 12.6V . The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation. The RY/BY Ý output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY Ý mini- mizes both CPU overhead and system power con- sumption. When low, RY/BY Ý indicates that the WSM is performing a block erase or byte write oper- ation. RY/BY Ý high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. Maximum access time is 85 ns (t ACC) over the com- mercial temperature range (0 §Ct o a70§C) and over VCC supply voltage range (4.5V to 5.5V and 4.75V to 5.25V). ICC active current (CMOS Read) is 20 mA typical, 35 mA maximum at 8 MHz . When the CE Ý and RP Ý pins are at V CC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the RPÝ pin is at GND, minimizing power consumption and providing write protection. ICC current in deep powerdown is 0.20 mA typical . Reset time of 400 ns is required from RP Ý switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 ms from RP Ý high until writes to the Command User Interface are recognized by the 28F008SA. With RP Ý at GND, the WSM is reset and the Status Register is cleared.

Figure 1. Block Diagram

Table 1. Pin Description latched during a write cycle. disabled. Data is internally latched during a write cycle. the memory device and reduces power consumption to standby levels. automation. Exit from Deep Powerdown sets device to read-array mode. during a read cycle. OE Ý is active low. rising edge of the WE Ý pulse. to tri-state off when the chip is deselected or data outputs are disabled. the array or writing bytes of each block. With V PP k VPPLMAX, memory contents cannot be altered.

Figure 2. TSOP Lead Configurations

Figure 3. TSOP Serpentine Layout

1. Connect all V CC and GND pins of each device to common power supply outputs. DO NOT leave V CC or GND inputs

Figure 4. PSOP Lead Configuration

Figure 5. 28F008SA Array Interface to Intel386SL Microprocessor Superset through PI Bus Resident O/S and Applications and Motherboard Solid-State Disk.

verified thru the Status Register. erase status for verification. data and execute code from any other block. Figure 6. Memory Map

VPP e VPPL, memory contents cannot be altered. PP can be at either V PPL or V PPH. Ý and WE Ý must also be at V IH. Figure 10 illustrates read bus cycle waveforms. placed in a high-impedance state. tive power until the operation completes. Table 2. Bus Operations

1. Refer to DC Characteristics. When V PP e VPPL, memory contents can be read but not written or erased.
2. X can be V IL or V IH for control pins and addresses, and V PPL or V PPH for V PP. See DC Characteristics for V PPL and V PPH

the WSM is not busy, in Erase Suspend mode or deep powerdown mode.

1. Command writes involving block erase or byte write are only successfully executed when V
2. Refer to Table 3 for valid D IN during a write operation.

value 10000, upon return to normal operation. other command can be written. same RESET Ý signal that resets the system CPU. identifiers from the Command User Interface. Table 3. Command Definitions

1. Bus operations are defined in Table 2.

e Identifier Address: 00H for manufacturer code, 01H for device code. BA e Address within the block being erased. WA e Address of memory location to be written.

1. SRD e Data read from Status Register. See Table 4 for a description of the Status Register bits.

WD e Data to be written at location WA. Data is latched on the rising edge of WE Ý. IID e Data read from Intelligent Identifiers.

1. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
2. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
3. Commands other than those shown above are reserved by Intel for future device implementations and should not be

input to the internal state machine. Ý to a logic-low level (V IL) while CE Ý is low. 3 defines the 28F008SA commands. Table 4. Status Register Definitions quence was entered. Attempt the operation again. back between V PPL and V PPH.

Intelligent Identifier Command The 28F008SA contains an Intelligent Identifier op- eration, initiated by writing 90H into the Command User Interface. Following the command write, a read cycle from address 00000H retrieves the manufac- turer code of 89H. A read cycle from address 00001H returns the device code of A2H. To termi- nate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is func- tional when V PP e VPPL or V PPH. Read Status Register Command The 28F008SA contains a Status Register which may be read to determine when a byte write or block erase operation is complete, and whether that oper- ation completed successfully. The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User In- terface. After writing this command, all subsequent read operations output data from the Status Regis- ter, until another valid command is written to the Command User Interface. The contents of the Status Register are latched on the falling edge of OE Ý or CE Ý, whichever occurs last in the read cy- cle. OE Ý or CE Ý must be toggled to V IH before further reads to update the Status Register latch. The Read Status Register command functions when V PP e VPPL or V PPH. Clear Status Register Command The Erase Status and Byte Write Status bits are set to ‘‘1’’s by the Write State Machine and can only be reset by the Clear Status Register Command. These bits indicate various failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or eras- ing multiple blocks in sequence). The Status Regis- ter may then be polled to determine if an error oc- curred during that sequence. This adds flexibility to the way the device may be used. Additionally, the V PP Status bit (SR.3) MUST be re- set by system software before further byte writes or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command User Interface. The Clear Status Register command is functional when V PP e VPPL or V PPH. Erase Setup/Erase Confirm Commands Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, followed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After the two-com- mand erase sequence is written to it, the 28F008SA automatically outputs Status Register data when read (see Figure 8; Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY/BY Ý pin, or the WSM Status bit of the Status Register. When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Register should be cleared. The Command User Interface remains in Read Status Register mode until further commands are issued to it. This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, reliable block erasure can only occur when V PP e VPPH. In the absence of this high voltage, memory contents are protected against era- sure. If block erase is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. Erase attempts while V PPL k VPP k VPPH produce spurious results and should not be attempted. Erase Suspend/Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend command (B0H) to the Com- mand User Interface requests that the WSM sus- pend the erase sequence at a predetermined point in the erase algorithm. The 28F008SA continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will de- termine when the erase operation has been sus- pended (both will be set to ‘‘1’’). RY/BY Ý will also transition to V OH. At this point, a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process. The Erase Suspend Status and WSM Status bits of the Status Register will be automatically cleared and RY/BY Ý will return to V OL. After the Erase Resume command is written to it, the 28F008SA automatical- ly outputs Status Register data when read (see Fig- ure 9; Erase Suspend/Resume Flowchart). V PP must remain at V PPH while the 28F008SA is in Erase Suspend.

Byte Write Setup/Write Commands (40H or 10H) Byte write is executed by a two-command sequence. The Byte Write Setup command (40H or 10H) is writ- ten to the Command User Interface, followed by a second write specifying the address and data (latched on the rising edge of WE Ý) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two- command byte write sequence is written to it, the 28F008SA automatically outputs Status Register data when read (see Figure 7; Byte Write Flowchart). The CPU can detect the completion of the byte write event by analyzing the output of the RY/BY Ý pin, or the WSM Status bit of the Status Register. Only the Read Status Register command is valid while byte write is active. When byte write is complete, the Byte Write Status bit should be checked. If byte write error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for ‘‘1’’s that do not successfully write to ‘‘0’’s. The Command User In- terface remains in Read Status Register mode until further commands are issued to it. If byte write is attempted while V PP e VPPL, the V PP Status bit will be set to ‘‘1’’. Byte write attempts while V PPL k VPP k VPPH produce spurious results and should not be attempted. EXTENDED BLOCK ERASE/BYTE WRITE CYCLING Intel has designed extended cycling capability into its ETOX flash memory technologies. The 28F008SA is designed for 100,000 byte write/block erase cycles on each of the sixteen 64-Kbyte blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunnel- ing electric field combine to greatly reduce oxide stress and the probability of failure. A 20-Mbyte sol- id-state drive using an array of 28F008SAs has a MTBF (Mean Time Between Failure) of 33.3 million hours (1), over 600 times more reliable than equiva- lent rotating disk technology. AUTOMATED BYTE WRITE The 28F008SA integrates the Quick-Pulse program- ming algorithm of prior Intel Flash devices on-chip, using the Command User Interface, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register. WSM operation, inter- nal verify and V PP high voltage presence are moni- tored and reported via the RY/BY Ý output and ap- propriate Status Register bits. Figure 7 shows a system software flowchart for device byte write. The entire sequence is performed with V PP at V PPH. Byte write abort occurs when RP Ý transitions to V IL,o r VPP drops to V PPL. Although the WSM is halted, byte data is partially written at the location where byte write was aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value. AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally, includ- ing all preconditioning of block data. WSM opera- tion, erase success and V PP high voltage presence are monitored and reported through RY/BY Ý and the Status Register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase Status and Byte Write Status bits will be set to ‘‘1’’s. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 8 shows a system software flowchart for block erase. Erase typically takes 1.6 seconds per block. The Erase Suspend/Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 9. The entire sequence is performed with V PP at V PPH. Abort occurs when RP Ý transitions to V IL or V PP falls to V PPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. DESIGN CONSIDERATIONS Three-Line Output Control The 28F008SA will often be used in large memory arrays. Intel provides three control inputs to accom- modate multiple memory connections. Three-line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE Ý, while OE Ý should be connected to all memory devices and the system’s READ Ý control line. This assures that only selected memory devices have active outputs while deselect- ed memory devices are in Standby Mode. RP Ý should be connected to the system Powergood sig- nal to prevent unintended writes during system pow- er transitions. Powergood should also toggle during system reset. (1)Assumptions: 10-Kbyte file written every 10 minutes. (20-Mbyte array)/(10-Kbyte file) e 2,000 file writes before erase required. (2000 files writes/erase) c (100,000 cycles per 28F008SA block) e 200 million file writes. (200 c 106 file writes) c (10 min/write) c (1 hr/60 min) e 33.3 c 106 MTBF.

finished executing the internal algorithm. attempting retry or other error recovery. Figure 7. Automated Byte Write Flowchart

before full status is checked. attempting retry or other error recovery. Figure 8. Automated Block Erase Flowchart

Figure 9. Erase Suspend/Resume Flowchart the device outputs’ capacitive and inductive loading. selection will suppress transient voltage peaks. crease V PP voltage spikes and overshoots.

VCC,V PP,R P Ý Transitions and the Command/Status Registers Byte write and block erase completion are not guar- anteed if V PP drops below V PPH. If the V PP Status bit of the Status Register (SR.3) is set to ‘‘1’’, a Clear Status Register command MUST be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to ‘‘1’’s if error is detected. RP Ý transitions to VIL during byte write and block erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or RP Ý transitions to V IL, clear the Status Register to initial value 10000 for the upper 5 bits. The Command User Interface latches commands as issued by system software and is not altered by V PP or CE Ý transitions or WSM actions. Its state upon powerup, after exit from deep powerdown or after V CC transitions below V LKO, is Read Array Mode. After byte write or block erase is complete, even after V PP transitions down to V PPL, the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired. Power Up/Down Protection The 28F008SA is designed to offer protection against accidental block erasure or byte writing dur- ing power transitions. Upon power-up, the 28F008SA is indifferent as to which power supply, V PP or V CC, powers up first. Power supply sequenc- ing is not required. Internal circuitry in the 28F008SA ensures that the Command User Interface is reset to the Read Array mode on power up. A system designer must guard against spurious writes for V CC voltages above V LKO when V PP is active. Since both WE Ý and CE Ý must be low for a command write, driving either to V IH will inhibit writes. The Command User Interface architecture provides an added level of protection since altera- tion of memory contents only occurs after success- ful completion of the two-step command sequences. Finally, the device is disabled until RP Ý is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases us- able battery life, because the 28F008SA does not consume any power to retain code or data when the system is off. In addition, the 28F008SA’s deep powerdown mode ensures extremely low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an ar- ray of 28F008SAs for solid-state storage, can lower RP Ý to V IL in standby or sleep modes, producing negligable power consumption. If access to the 28F008SA is again needed, the part can again be read, following the t PHQV and t PHWL wakeup cycles required after RP Ý is first raised back to V IH. See AC CharacteristicsÐRead-Only and Write Opera- tions and Figures 10 and 11 for more information.

ABSOLUTE MAXIMUM RATINGS * Operating Temperature During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 §Ct o a70§C(1) During Block Erase/Byte Write ÀÀÀÀ0 §Ct o a70§C Temperature Under Bias ÀÀÀÀÀÀÀÀÀ b10§Ct o a80§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a125§C Voltage on Any Pin (except V CC and V PP) with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(2) VPP Program Voltage with Respect to GND during Block Erase/Byte Write ÀÀÀ b2.0V to a14.0V(2, 3) VCC Supply Voltage with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(2) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (4) NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods k20 ns. Maximum DC voltage on input/output pins is V CC a 0.5V which, during transitions, may overshoot to V CC a 2.0V for periods k20 ns. 3. Maximum DC voltage on V PP may overshoot to a14.0V for periods k20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. 5% V CC specifications reference the 28F008SA-85 in its High Speed configuration. 10% V CC specifications reference the 28F008SA-85 in its Standard configuration, and the 28F008SA-120. OPERATING CONDITIONS Symbol Parameter Notes Min Max Unit TA Operating Temperature 0 70 §C VCC VCC Supply Voltage (10%) 5 4.50 5.50 V VCC VCC Supply Voltage (5%) 5 4.75 5.25 V DC CHARACTERISTICS Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1, 3 1.0 2.0 mA V CC e VCC Max CEÝ e RPÝ e VIH 30 100 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V ICCD VCC Deep PowerDown 1 0.20 1.2 mAR P Ý e GND g0.2V Current I OUT (RY/BYÝ) e 0m A ICCR VCC Read Current 1 20 35 mA V CC e VCC Max, CE Ý e GND f e 8 MHz, I OUT e 0m A CMOS Inputs 25 50 mA V CC e VCC Max, CE Ý e VIL f e 8 MHz, I OUT e 0m A TTL Inputs

DC CHARACTERISTICS (Continued) Symbol Parameter Notes Min Typ Max Unit Test Condition ICCW VCC Byte Write Current 1 10 30 mA Byte Write In Progress ICCE VCC Block Erase Current 1 10 30 mA Block Erase In Progress ICCES VCC Erase Suspend Current 1, 2 5 10 mA Block Erase Suspended CEÝ e VIH IPPS VPP Standby Current 1 g1 g15 mAV PP s VCC IPPD VPP Deep PowerDown 1 0.10 5.0 mAR P Ý e GND g0.2V Current IPPR VPP Read Current 200 mAV PP l VCC IPPW VPP Byte Write Current 1 10 30 mA V PP e VPPH Byte Write in Progress IPPE VPP Block Erase Current 1 10 30 mA V PP e VPPH Block Erase in Progress IPPES VPP Erase Suspend 1 90 200 mAV PP e VPPH Current Block Erase Suspended VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 3 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage (TTL) 3 2.4 V V CC e VCC Min IOH eb 2.5 mA VOH2 Output High Voltage 0.85 V CC VI OH eb 2.5 mA (CMOS) V CC e VCC Min VCC b 0.4 I OH eb 100 mA VCC e VCC Min VPPL VPP during Normal 4 0.0 6.5 V Operations VPPH VPP during Erase/Write 11.4 12.0 12.6 V Operations VLKO VCC Erase/Write Lock 2.0 V Voltage

EXTENDED TEMPERATURE OPERATING CONDITIONS Symbol Parameter Notes Min Max Unit TA Operating Temperature b40 a85 §C VCC VCC Supply Voltage (10%) 5 4.50 5.50 V VCC VCC Supply Voltage (5%) 5 4.75 5.25 V DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1, 3 1.0 2.0 mA V CC e VCC Max CEÝ e RPÝ e VIH 30 100 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V ICCD VCC Deep PowerDown 1 0.20 20 mAR P Ý e GND g0.2V Current I OUT (RY/BYÝ) e 0m A ICCR VCC Read Current 1 20 35 mA V CC e VCC Max, CE Ý e GND f e 8 MHz, I OUT e 0m A CMOS Inputs 25 50 mA V CC e VCC Max, CE Ý e VIL f e 8 MHz, I OUT e 0m A TTL Inputs ICCW VCC Byte Write Current 1 10 30 mA Byte Write In Progress ICCE VCC Block Erase Current 1 10 30 mA Block Erase In Progress ICCES VCC Erase Suspend Current 1, 2 5 10 mA Block Erase Suspended CEÝ e VIH IPPS VPP Standby Current 1 g1 g15 mAV PP s VCC IPPD VPP Deep PowerDown 1 0.10 5.0 mAR P Ý e GND g0.2V Current IPPR VPP Read Current 200 mAV PP l VCC IPPW VPP Byte Write Current 1 10 30 mA V PP e VPPH Byte Write in Progress IPPE VPP Block Erase Current 1 10 30 mA V PP e VPPH Block Erase in Progress IPPES VPP Erase Suspend 1 90 200 mAV PP e VPPH Current Block Erase Suspended

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued) Symbol Parameter Notes Min Typ Max Unit Test Condition VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CC a 0.5 V VOL Output Low Voltage 3 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage 3 2.4 V V CC e VCC Min (TTL) IOH eb 2.5 mA VOH2 Output High Voltage 0.85 V CC VI OH eb 2.5 mA (CMOS) V CC e VCC Min VCC b 0.4 I OH eb 100 mA VCC e VCC Min VPPL VPP during Normal 4 0.0 6.5 V Operations VPPH VPP during Erase/Write 11.4 12.0 12.6 V Operations VLKO VCC Erase/Write Lock 2.0 V Voltage CAPACITANCE(5) TA e 25§C, f e 1 MHz Symbol Parameter Typ Max Unit Condition CIN Input Capacitance 6 8 pF V IN e 0V COUT Output Capacitance 8 12 pF V OUT e 0V NOTES: are valid for all product versions (packages and speeds). 2. I CCES is specified with the device deselected. If the 28F008SA is read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Includes RY/BY Ý. 4. Block Erases/Byte Writes are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL. 5. Sampled, not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM (1) 290429–11 AC test inputs are driven at V OH (2.4 V TTL) for a Logic ‘‘1’’ and V OL (0.45 V TTL) for a Logic ‘‘0’’. Input timing begins at V IH (2.0 V TTL) and V IL (0.8 V TTL). Output timing ends at V IH and VIL. Input rise and fall times (10% to 90%) k 10 ns. AC TESTING LOAD CIRCUIT (1) CL e 100 pF CL Includes Jig Capacitance 290429–12 RL e 3.3 k X HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM (2) 290429–17 AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0’’. Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) k 10 ns. HIGH SPEED AC TESTING LOAD CIRCUIT (2) CL e 30 pF CL Includes Jig Capacitance 290429–18 RL e 3.3 k X NOTES: 1. Testing characteristics for 28F008SA-85 in Standard configuration, and 28F008SA-120. 2. Testing characteristics for 28F008SA-85 in High Speed configuration. AC CHARACTERISTICSÐRead-Only Operations (1) Versions VCCg5% 28F008SA-85 (4) UnitVCCg10% 28F008SA-85 (5) 28F008SA-120(5) Symbol Parameter Notes Min Max Min Max Min Max tAVAV tRC Read Cycle Time 85 90 120 ns tAVQV tACC Address to Output Delay 85 90 120 ns tELQV tCE CEÝ to Output Delay 2 85 90 120 ns tPHQV tPWH RPÝ High to Output Delay 400 400 400 ns tGLQV tOE OEÝ to Output Delay 2 40 45 50 ns tELQX tLZ CEÝ to Output Low Z 3 0 0 0 ns tEHQZ tHZ CEÝ High to Output High Z 3 55 55 55 ns tGLQX tOLZ OEÝ to Output Low Z 3 0 0 0 ns tGHQZ tDF OEÝ High to Output High Z 3 30 30 30 ns tOH Output Hold from 3 0 0 0 ns Addresses, CE Ý or OE Ý Change, Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE Ý may be delayed up to t CE –tOE after the falling edge of CE Ý without impact on t CE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICSÐRead-Only Operations (1) Versions V CCg10% 28F008SA-100 (5) Unit Symbol Parameter Notes Min Max tAVAV tRC Read Cycle Time 100 ns tAVQV tACC Address to Output Delay 100 ns tELQV tCE CEÝ to Output Delay 2 100 ns tPHQV tPWH RPÝ High to Output Delay 400 ns tGLQV tOE OEÝ to Output Delay 2 55 ns tELQX tLZ CEÝ to Output Low Z 3 0 ns tEHQZ tHZ CEÝ High to Output High Z 3 55 ns tGLQX tOLZ OEÝ to Output Low Z 3 0 ns tGHQZ tDF OEÝ High to Output High Z 3 30 ns tOH Output Hold from Addresses, CE Ý or 3 0 ns OEÝ Change, Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE Ý may be delayed up to t CE –tOE after the falling edge of CE Ý without impact on t CE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

Figure 10. AC Waveform for Read Operations

AC CHARACTERISTICSÐWrite Operations (1) Versions VCCg5% 28F008SA-85 (7) UnitVCCg10% 28F008SA-85 (8) 28F008SA-120(8) Symbol Parameter Notes Min Max Min Max Min Max tAVAV tWC Write Cycle Time 85 90 120 ns tPHWL tPS RPÝ High Recovery to 2 1 1 1 ms WEÝ Going Low tELWL tCS CEÝ Setup to WE Ý Going 10 10 10 ns Low tWLWH tWP WEÝ Pulse Width 40 40 40 ns tVPWH tVPS VPP Setup to WE Ý Going 2 100 100 100 ns High tAVWH tAS Address Setup to WE Ý 34 0 4 0 4 0 n s Going High tDVWH tDS Data Setup to WE Ý Going 4 40 40 40 ns High tWHDX tDH Data Hold from WE Ý High 5 5 5 ns tWHAX tAH Address Hold from WE Ý 55 5 n s High tWHEH tCH CEÝ Hold from WE Ý High 10 10 10 ns tWHWL tWPH WEÝ Pulse Width High 30 30 30 ns tWHRL WEÝ High to RY/BY Ý 100 100 100 ns Going Low tWHQV1 Duration of Byte Write 5, 6 6 6 6 ms Operation tWHQV2 Duration of Block Erase 5, 6 0.3 0.3 0.3 sec Operation tWHGL Write Recovery before 0 0 0 ms Read tQVVL tVPH VPP Hold from Valid SRD, 2, 6 0 0 0 ns RY/BYÝ High NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY Ý e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Notes 28F008SA-85 28F008SA-120 Unit Min Typ (1) Max Min Typ (1) Max Block Erase Time 2 1.6 10 1.6 10 sec Block Write Time 2 0.6 2.1 0.6 2.1 sec Byte Write Time 8 (Note 3) 8 (Note 3) ms NOTES: 1. 25 §C, 12.0 V PP. 2. Excludes System-Level Overhead. 3. Contact your Intel representative for information on the maximum byte write specification. EXTENDED TEMPERATURE OPERATION AC CHARACTERISTICSÐWrite Operations (1) Versions V CCg10% 28F008SA-100 (8) Unit Symbol Parameter Notes Min Max tAVAV tWC Write Cycle Time 100 ns tPHWL tPS RPÝ High Recovery to WE Ý Going Low 2 1 ms tELWL tCS CEÝ Setup to WE Ý Going Low 10 ns tWLWH tWP WEÝ Pulse Width 40 ns tVPWH tVPS VPP Setup to WE Ý Going High 2 100 ns tAVWH tAS Address Setup to WE Ý Going High 3 40 ns tDVWH tDS Data Setup to WE Ý Going High 4 40 ns tWHDX tDH Data Hold from WE Ý High 5 ns tWHAX tAH Address Hold from WE Ý High 5 ns tWHEH tCH CEÝ Hold from WE Ý High 10 ns tWHWL tWPH WEÝ Pulse Width High 30 ns tWHRL WEÝ High to RY/BY Ý Going Low 100 ns tWHQV1 Duration of Byte Write Operation 5, 6 6 ms tWHQV2 Duration of Block Erase Operation 5, 6 0.3 sec tWHGL Write Recovery before Read 0 ms tQVVL tVPH VPP Hold from Valid SRD, RY/BY Ý High 2, 6 0 ns NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY Ý e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

EXTENDED TEMPERATURE OPERATION BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Notes 28F008SA-100 Unit Min Typ (1) Max Block Erase Time 2 1.6 10 sec Block Write Time 2 0.6 2.1 sec Byte Write Time 8 (Note 3) ms NOTES: 1. 25 §C, 12.0 V PP. 2. Excludes System-Level Overhead. 3. Contact your Intel representative for information on the maximum byte write specification.

Figure 11. AC Waveform for Write Operations

ALTERNATIVE CE Ý-CONTROLLED WRITES Versions VCCg5% 28F008SA-85 (6) UnitVCCg10% 28F008SA-85 (7) 28F008SA-120(7) Symbol Parameter Notes Min Max Min Max Min Max tAVAV tWC Write Cycle Time 85 90 120 ns tPHEL tPS RPÝ High Recovery to 2 1 1 1 ms CEÝ Going Low tWLEL tWS WEÝ Setup to CE Ý Going 0 0 0 ns Low tELEH tCP CEÝ Pulse Width 50 50 50 ns tVPEH tVPS VPP Setup to CE Ý Going 2 100 100 100 ns High tAVEH tAS Address Setup to CE Ý 34 0 4 0 4 0 n s Going High tDVEH tDS Data Setup to CE Ý Going 4 40 40 40 ns High tEHDX tDH Data Hold from CE Ý High 5 5 5 ns tEHAX tAH Address Hold from CE Ý 55 5 n s High tEHWH tWH WEÝ Hold from CE Ý High 0 0 0 ns tEHEL tEPH CEÝ Pulse Width High 25 25 25 ns tEHRL CEÝ High to RY/BY Ý 100 100 100 ns Going Low tEHQV1 Duration of Byte Write 5 6 6 6 ms Operation tEHQV2 Duration of Block Erase 5 0.3 0.3 0.3 sec Operation tEHGL Write Recovery before 0 0 0 ms Read tQVVL tVPH VPP Hold from Valid SRD, 2, 5 0 0 0 ns RY/BYÝ High NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE Ý and WE Ý. In systems where CEÝ defines the write pulsewidth (within a longer WE Ý timing waveform), all setup, hold and inactive WE Ý times should be measured relative to the CE Ý waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY Ý e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

EXTENDED TEMPERATURE OPERATION ALTERNATIVE CE Ý-CONTROLLED WRITES Versions V CCg10% 28F008SA-100 (7) Unit Symbol Parameter Notes Min Max tAVAV tWC Write Cycle Time 100 ns tPHEL tPS RPÝ High Recovery to CE Ý Going Low 2 1 ms tWLEL tWS WEÝ Setup to CE Ý Going Low 0 ns tELEH tCP CEÝ Pulse Width 50 ns tVPEH tVPS VPP Setup to CE Ý Going High 2 100 ns tAVEH tAS Address Setup to CE Ý Going High 3 40 ns tDVEH tDS Data Setup to CE Ý Going High 4 40 ns tEHDX tDH Data Hold from CE Ý High 5 ns tEHAX tAH Address Hold from CE Ý High 5 ns tEHWH tWH WEÝ Hold from CE Ý High 0 ns tEHEL tEPH CEÝ Pulse Width High 25 ns tEHRL CEÝ High to RY/BY Ý Going Low 100 ns tEHQV1 Duration of Byte Write Operation 5 6 ms tEHQV2 Duration of Block Erase Operation 5 0.3 sec tEHGL Write Recovery before Read 0 ms tQVVL tVPH VPP Hold from Valid SRD, RY/BY Ý High 2, 5 0 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE Ý and WE Ý. In systems where CEÝ defines the write pulsewidth (within a longer WE Ý timing waveform), all setup, hold and inactive WE Ý times should be measured relative to the CE Ý waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid A IN for byte write or block erasure. 4. Refer to Table 3 for valid D IN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 e 1, RY/BY Ý e VOH). V PP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 e 0) 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris- tics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

Figure 12. Alternate AC Waveform for Write Operations

ORDERING INFORMATION

290429–16 VALID COMBINATIONS E28F008SA-85 F28F008SA-85 PA28F008SA-85 TE28F008SA-100 TB28F008SA-100 E28F008SA-120 F28F008SA-120 PA28F008SA-120 TF28F008SA-100 ADDITIONAL INFORMATION Order Number 28F008SA-L Datasheet 290435 ‘‘28F008SA 8-Mbit (1-Mbit x 8) Flash Memory SmartDie TM Product Specification’’ 271296 AP-359 ‘‘28F008SA Hardware Interfacing’’ 292094 AP-360 ‘‘28F008SA Software Drivers’’ 292095 AP-364 ‘‘28F008SA Automation and Algorithms’’ 292099 ER-27 ‘‘The Intel 28F008SA Flash Memory’’ 294011 ER-28 ‘‘ETOX TM III Flash Memory Technology’’ 290412

REVISION HISTORY

002 Revised from Advanced Information to Preliminary

Modified Erase Suspend Flowchart Removed -90 speed bin Integrated -90 characteristics into -85 speed bin Combined V PP Standby current and V PP Read current into one V PP Standby current spec with two test conditions (DC Characteristics table) Lowered V LKO from 2.2V to 2.0V.

004 PWD renamed to RPÝ for JEDEC standardization

compatibility. Changed I PPS Standby current spec from g10 mA to g15 mA in DC Characteristics table.

005 Added Extended Temperature Specs for 28F008SA

Added V OHZ (Output High VoltageÐCMOS) Spec Added Byte Write Time Spec