PA28F400B5T80 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 Product Overview
- 2.0 PRODUCT DESCRIPTION
- 2.1 Pin Descriptions
- 2.2 Pinouts
- 2.3 Memory Blocking Organization
- 2.3.1 One 16-KB Boot Block
- 2.3.2 Two 8-KB Parameter Blocks
- 2.3.3 Main Blocks - One 96-KB + Additional
- 3.0 PRINCIPLES OF OPERATION
- 3.1 Bus Operations
- 3.1.1 Read
- 3.1.2 Output Disable
- 3.1.3 Standby
- 3.1.4 Word/Byte Configuration
- 3.1.5 Deep Power-Down/Reset
- 3.1.6 Write
- 3.2 Modes of Operation
- 3.2.1 Read Array
- 3.2.2 Read Identifier
- 3.2.3 Read Status Register
- 3.2.4 Word/Byte Program
- 3.2.5 Block Erase
- 3.3 Boot Block Locking
- 3.3.2 WP# = VIL for Boot Block Locking
- 3.3.3 RP# = VHH or WP# = VIH for Boot Block
- 3.3.4 Note For 8-Mbit 44-PSOP Package
- 4.0 DESIGN CONSIDERATIONS
- 4.1 Power Consumption
- 4.1.1 Active Power
- 4.1.2 Automatic Power Savings (APS)
- 4.1.3 Standby Power
- 4.1.4 Deep Power-Down Mode
- 4.2 Power-Up/Down Operation
- 4.2.1 RP# Connected To System Reset
- 4.3 Board Design
- 4.3.1 Power Supply Decoupling
- 5.0 ELECTRICAL SPECIFICATIONS
- 5.1 Absolute Maximum Ratings
- 5.2 Operating Conditions
- 5.3 Capacitance
- 5.4 DC Characteristics—Commercial and
- 5.5 DC Characteristics—Automotive
- 5.6 AC Characteristics—Read Operations—
- 5.7 AC Characteristics—Read Operations—
- 5.8 Erase and Program Timings—Commercial
- 5.9 Erase and Program Timings—Automotive
- 5.10 AC Characteristics—Write Operations—
- 5.11 AC Characteristics—Write Operations—
- 6.0 ORDERING INFORMATION
- 7.0 ADDITIONAL INFORMATION
E PRELIMINARY June 1999 Order Number: 290599-007 /c110 SmartVoltage Technology 5 Volt Boot Block Flash:
5 V Reads, 5 V or 12 V Writes
Increased Programming Throughput at 12 V V PP /c110 Very High-Performance Read 2-, 4-Mbit: 55 ns Access Time 8-Mbit: 70 ns Access Time /c110 x8 or x8/x16-Configurable Data Bus /c110 Low Power Consumption Max 60 mA Read Current at 5 V Auto Power Savings: <1 mA Typical Standby Current /c110 Optimized Array Blocking Architecture 16-KB Protected Boot Block Two 8-KB Parameter Blocks 96-KB and 128-KB Main Blocks Top or Bottom Boot Locations /c110 Extended Temperature Operation –40 °C to +85 °C /c110 Industry-Standard Packaging 40, 48-Lead TSOP, 44-Lead PSOP /c110 Extended Block Erase Cycling 100,000 Cycles at Commercial Temp 10,000 Cycles at Extended Temp 30,000 Cycles for Parameter Blocks and 1,000 Cycles for Main Blocks at Automotive Temperature /c110 Hardware Data Protection Feature Absolute Hardware-Protection for Boot Block Write Lockout during Power Transitions /c110 Automated Word/Byte Program and Block Erase Command User Interface Status Registers Erase Suspend Capability /c110 SRAM-Compatible Write Interface /c110 Reset/Deep Power-Down Input Provides Low-Power Mode and Reset for Boot Operations /c110 Pinout Compatible 2, 4, and 8 Mbit /c110 ETOX™ Flash Technology 0.6 µ ETOX IV Initial Production 0.4 µ ETOX V Later Production The Intel® 5 Volt Boot Block Flash memory family provides 2-, 4-, and 8-Mbit memories featuring high- density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for embedded code execution applications, such as networking infrastructure and office automation. Based on Intel ® Boot Block architecture, the 5 Volt Boot Block Flash memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. This family of products comes in industry- standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP. NOTE: This document formerly known as Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit.
5 VOLT BOOT BLOCK
28F200B5, 28F004/400B5, 28F800B5 (x8/x16)
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F200B5, 28F0040/400B5, 28F800B5 may contain design defects or errors known are errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com COPYRIGHT © INTEL CORPORATION 1997, 1998, 1999 CG-041493 *Other brands and names are the property of their respective owners.
28F200B5, 28F004/400B5, 28F800B5 E
4 PRELIMINARY
REVISION HISTORY
-001 Original Version -002 Minor changes throughout document. Section 3.1.5 and Figure 14 redone to clarify program/erase operation abort. Information added to Table 2, Figure 1, and Section 3.3 to clarify WP# on 8-Mbit, 44-PSOP. Read and Write Waveforms changed to numbered format. Typical numbers removed from DC Characteristics and Erase/Program Timings. -003 Minor text changes throughout document. Figure 1, 44-PSOP pinout: mistake on pin 3 on 2-Mbit pinout corrected from A17 to NC. Specs tEHQZ and tGHQZ improved. Explanations of program/erase abort commands reworked in Table 6, Command Codes. -004 Specifications for 28F004B5 40-TSOP version added; Erase suspend text and flowchart updated for clarity (Section 3.2.5.1, Table 6, Figure 10) -005 Added TE28F004B5 product offerings to ordering information chart. Added 55 ns speed capability for 2- and 4-Mbit devices. Revised I CCD max value. Name of document changed from Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit. -006 Added automotive temperature product offerings. -007 Modified document to show new 8-Mbit, 80 ns automotive temperature product offerings.
1.0 INTRODUCTION
and 8-Mbit 5 Volt Boot Block Flash memories.
1.1 Product Overview
Table 1. 5 Volt Boot Block Flash Boot Block Family: Feature Summary
- As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer
capable of 60 ns read access times when VCC = 5 V ± 5% and 30 pF load.
- Automotive versions of this product are only available as 28F200B5, 28F400B5 and 28F800B5 and are only offered in the
28F200B5, 28F004/400B5, 28F800B5 E
6 PRELIMINARY
SmartVoltage technology enables fast factory programming and low-power designs. Specifically designed for 5 V systems, 5 Volt Boot Block Flash components support read operations at 5 V V CC and internally configure to program/erase at 5 V or 12 V. The 12 V V PP option renders the fastest program and erase performance which will increase your factory throughput. With the 5 V V PP option, VCC and VPP can be tied together for a simple 5 V design. In addition, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK . The memory array is asymmetrically divided into blocks in an asymmetrical architecture to accommodate microprocessors that boot from the top (denoted by -T suffix) or the bottom (-B suffix) of the memory map. The blocks incl ude a hardware-lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and additional block(s) of 131,072 bytes). See Figures 4–7 for memory maps. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. At automotive temperature, each parameter block can be independently erased and programmed 30,000 times, and each main and boot block 1,000 times. Unlike erase operations, which erase all locations within a block simultaneously, each byte or word in the flash memory can be programmed independently of other memory locations. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.3 for details). The system processor interfaces to the flash device through a Command User Interface (CUI), using valid command sequences to initiate device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I CCR current is 1 mA. When CE# and RP# pins are at V CC , the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. A reset time (t PHQV ) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (t PHEL ) from RP#-high until writes to the CUI are recognized. See Section 4.2. The deep power-down mode can also be used as a device reset, allowing the flash to be reset along with the rest of the system. For example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system com ponents, the flash memory could remain in a non-read mode, such as erase. Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read mode upon activation of the Reset signal. This also provides protection against unwanted command writes due to invalid system bus conditions during system reset or power-up/down sequences. These devices are configurable at power-up for either byte-wide or word-wide input/output using the BYTE# pin. Please see Table 2 for a detailed description of BYTE# operations, especially the usage of the DQ 15/A–1 pin. These 5 Volt Boot Block Flash memory products are available in the 44-lead PSOP (Plastic Small Outline Package), which is ROM/EPROM- compatible, and the 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick) as shown in Figure 1, and 2, respectively.
2.0 PRODUCT DESCRIPTION
This section describes the pinout and block architecture of the device family.
2.1 Pin Descriptions
The pin descriptions table details the usage of each of the device pins.
Table 2. Pin Descriptions don’t care in the signature mode when BYTE# is low. when CE# and WE# are active. Data is internally latched during the write cycle. tri-state when the chip is de-selected or the outputs are disabled. during a Program command. Data is internally latched during the write cycle. 15/A–1 becomes the lowest order address for data output on DQ0–DQ 7. through the CE# and RP# input stages. a read cycle. OE# is active low. unlocking. It is backwards-compatible with the BX/BL/BV products. transitions from logic-low to logic-high, the device defaults to the read array mode. erased. This overrides any control from the WP# input.
8 PRELIMINARY
Table 2. Pin Descriptions (Continued) level signal in a system without a 12 V supply. required to unlock the boot block. See Section 3.3 for details on write protection. read and programmed on DQ0–DQ 15. against Program and Erase commands. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating.
2.2 Pinouts
Figure 2. Applications using an 8-bit bus can use 8-Mbit pinouts going outward from the center.
10 PRELIMINARY
Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only)
2.3 Memory Blocking Organization
2.3.1 ONE 16-KB BOOT BLOCK
WP# pins, as is detailed in Section 3.3.
2.3.2 TWO 8-KB PARAMETER BLOCKS
2.3.3 MAIN BLOCKS - ONE 96-KB +
12 PRELIMINARY
NOTE: In x8 operation, the least significant system address should be connected to A-1. Figure 6. Byte-Wide x8-Mode Memory Maps (Top Boot) NOTE: In x8 operation, the least significant system address should be connected to A-1. Figure 7. Byte-Wide x8-Mode Memory Maps (Bottom Boot)
E 28F200B5, 28F004/400B5, 28F800B5 13PRELIMINARY
3.0 PRINCIPLES OF OPERATION
The system processor accesses the 5 Volt Boot Block Flash memories through the Command User Interface (CUI), which accepts commands written with standard microprocessor write timings and TTL-level control inputs. The flash can be switched into each of its three read and two write modes through commands issued to the CUI. A comprehensive chart showing the state transitions is in Appendix A. After initial device power-up or return from deep power-down mode, the device defaults to read array mode. In this mode, manipulation of the memory control pins allows array read, standby, and output disable operations. The other read modes, read identifier and read status register, can be reached by issuing the appropriate command to the CUI. Array data, identifier codes and status register results can be accessed using these commands independently from the V PP voltage. Read identifier mode can also be accessed by PROM programming equipment by raising A 9 to high voltage (VID). CUI commands sequences also control the write functions of the flash memory, Program and Erase. Issuing program or erase command sequences internally latches addresses and data and initiates Write State Machine (WSM) operations to execute the requested write function. The WSM internally regulates the program and erase algorithms, including pulse repetition, internal verification, and margining of data, freeing the host processor from these tasks and allowing precise control for high reliability. To execute Program or Erase commands, V PP must be at valid write voltage (5 V or 12 V). While the WSM is executing a program operation, the device defaults to the read status register mode and all commands are ignored. Thus during the programming process, only status register data can be accessed from the device. While the WSM is executing a erase operation, the device also defaults to the read status register mode but one additional command is available, erase suspend to read, which will suspend the erase operation and allow reading of array data. The suspended erase operation can be completed by issuing the Erase Resume command. After the program or erase operation has completed, the device remains in read status register mode. From this mode any of the other read or write modes can be reached with the appropriate command. For example, to read data, issue the Read Array command. Additional Program or Erase commands can also be issued from this state. During program or erase operations, the array data is not available for reading or code execution, except during an erase suspend. Consequently, the software that initiates and polls progress of program and erase operations must be copied to and executed from system RAM during flash memory update. After successful completion, reads are again possible via the Read Array command. Each of the device modes will be discussed in detail in the following sections.
3.1 Bus Operations
The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. These bus operations are summarized in Tables 3 and 4.
3.1.1 READ
The flash memory has three read modes available, read array, read identifier, and read status. These read modes are accessible independent of the V PP voltage. RP# can be at either VIH or VHH . The appropriate read-mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and, when active, enables the selected memory device. OE# is the data output (DQ 0–DQ 15) control and when active drives the selected memory data onto the I/O bus. In read modes, WE# must be at V IH and RP# must be at V IH or VHH . Figure 15 illustrates a read cycle.
28F200B5, 28F004/400B5, 28F800B5 E
14 PRELIMINARY
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (if available on the device) DQ 0–DQ 15 are placed in a high- impedance state.
3.1.3 STANDBY
Deselecting the device by bringing CE# to a logic- high level (VIH) places the device in standby mode which substantially reduces device power consumption. In standby, outputs DQ 0–DQ 15 are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues functioning and consuming active power until the operation completes.
3.1.4 WORD/BYTE CONFIGURATION
The 16-bit devices can be configured for either an 8-bit or 16-bit bus width by setting the BYTE# pin before power-up. This is not applicable to the 8-bit only E28F004B5. When BYTE# is set to logic low, the byte-wide mode is enabled, where data is read and programmed on DQ 0–DQ 7 and DQ15/A–1 becomes the lowest order address that decodes between the upper and lower byte. DQ 8–DQ 14 are tri-stated during the byte-wide mode. When BYTE# is at logic high, the word-wide mode is enabled, and data is read and programmed on DQ 0–DQ 15.
3.1.5 DEEP POWER-DOWN/RESET
RP# at VIL initiates the deep power-down mode, also referred to as reset mode. From read mode, RP# going low for time tPLPH deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. After return from power-down, a time t PHQV is required until the initial memory access outputs are valid. A delay (t PHWL or tPHEL ) is required after return from power-down before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. This case is shown in Figure 14A. If RP# is taken low for time t PLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: When RP# goes low, the device shuts down the operation in progress, a process which takes time t PLRH to complete. After this time tPLRH , the part will either reset to read array mode (if RP# has gone high during tPLRH , Figure 14B) or enter deep power-down mode (if RP# is still logic low after t PLRH , Figure 14C). In both cases, after returning from an aborted operation, the relevant time t PHQV or tPHWL /tPHEL must be waited before a read or write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of t PLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, processor expects to read from the flash memory. Automated flash memories provide status information when read during program or block erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel ® Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.6 WRITE
The CUI does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings when WE# and CE# are low, OE# = V IH, and the proper address and data (command) are presented. The address and data for a command are latched on the rising edge of WE# or CE#, whichever goes high first. Figure 16 illustrates a write operation.
Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH) Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
- Refer to DC Characteristics.
- X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP .
- See DC Characteristics for VPPLK , VPPH1 , VPPH2 , VHH , VID voltages.
- Manufacturer and device codes may also be accessed via a CUI write sequence, A0 selects, all other addresses = X.
- See Table 5 for device IDs.
- Refer to Table 7 for valid D
IN during a write operation.
- Command writes for block erase or program are only executed when VPP = VPPH1 or VPPH2 .
- To program or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.3.
- RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
- This column does not apply to the E28F004B5 since it is a x8-only device.
16 PRELIMINARY
3.2 Modes of Operation
3.2.1 READ ARRAY
location in conjunction with a read bus operation. voltage and RP# can be VIH or VHH . Table 5. Intelligent Identifier Codes In byte-mode, the upper byte will be tri-stated.
3.2.2 READ IDENTIFIER
array mode, write a Read Array command (FFH).
3.2.3 READ STATUS REGISTER
register bit codes are defined in Table 8. DQ 15/A–1 retains the low order address function. status register contents change while being read. completion of a program or erase operation.
3.2.3.1 Clearing the Status Register
reset by the Clear Status Register command.
E 28F200B5, 28F004/400B5, 28F800B5 17PRELIMINARY these bits, several operations (such as cumulatively erasing multiple blocks or programming several bytes in sequence) may be performed before polling the status register to determine if an error occurred during the series. Issue the Clear Status Register command (50H) to clear the status register. It functions independently of the applied V PP voltage and RP# can be VIH or VHH . This command is not functional during block erase suspend modes. Resetting the part with RP# also clears the status register.
3.2.4 WORD/BYTE PROGRAM
Word or byte program operations are executed by a two-cycle command sequence. Program Set-Up (40H) is issued, followed by a second write that specifies the address and data (latched on the rising edge of WE# or CE#, whichever comes first). The WSM then takes over, controlling the program and program verify algorithms internally. While the WSM is working, the device automatically enters read status register mode and remains there after the word/byte program is complete. (see Figure 8). The completion of the program event is indicated on status register bit SR.7. When a word/byte program is complete, check status register bit SR.4 for an error flag (“1”). The cause of a failure may be found on SR.3, which indicates “1” if V PP was out of program/erase voltage range (VPPH1 or VPPH2 ). The status register should be cleared before the next operation. The internal WSM verify only detects errors for “1”s that do not successfully write to “0”s. Since the device remains in status register read mode after programming is completed, a command must be issued to switch to another mode before beginning a different operation.
3.2.5 BLOCK ERASE
A block erase changes all block data to 1’s (FFFFH) and is initiated by a two-cycle command. An Erase Set-Up command (20H) is issued first, followed by an Erase Confirm command (D0H) along with an address within the target block. The address will be latched at the rising edge of WE# or CE#, whichever comes first. Internally, the WSM will program all bits in the block to “0,” verify all bits are adequately programmed to “0,” erase all bits to “1,” and verify that all bits in the block are sufficiently erased. After block erase command sequence is issued, the device automatically enters read status register mode and outputs status register data when read (see Figure 9). The completion of the erase event is indicated on status register bit SR.7. When an erase is complete, check status register bit SR.5 for an error flag (“1”). The cause of a failure may be found on SR.3, which indicates “1” if V PP was out of program/erase voltage range (VPPH1 or VPPH2 ). If an Erase Set-Up (20H) command is issued but not followed by an Erase Confirm (D0H) command, then both the program status (SR.4) and the erase status (SR.5) will be set to “1.” The status register should be cleared before the next operation. Since the device remains in status register read mode after erasing is completed, a command must be issued to switch to another mode before beginning a different operation.
3.2.5.1 Erase Suspend/Resume
The Erase Suspend command (B0H) interrupts an erase operation in order to read data in another block of memory. While the erase is in progress, issuing the Erase Suspend command requests that the WSM suspend the erase algorithm after a certain latency period. After issuing the Erase Suspend command, write the Read Status Register command, then check bit SR.7 and SR.6 to ensure the device is in the erase suspend mode (both will be set to “1”). This check is necessary because the WSM may have completed the erase operation before the Erase Suspend command was issued. If this occurs, the Erase Suspend command would switch the device into read array mode. See Appendix A for a comprehensive chart showing the state transitions. When erase has been suspended, a Read Array command (FFH) can be written to read from blocks other than that which is suspended. The only other valid commands at this time are Erase Resume (D0H) or Read Status Register. During erase suspend mode, the chip can go into a pseudo-standby mode by taking CE# to V IH, which reduces active current draw. VPP must remain at VPPH1 or VPPH2 (the same VPP level used for block erase) while erase is suspended. RP# must also remain at V IH or VHH (the same RP# level used for block erase).
18 PRELIMINARY
and the next instruction issued in order to continue. Table 6. Command Codes and Descriptions
00 Invalid/
these codes for future functions.
40 Program
when OE# is enabled. To read the array, issue a Read Array command.
10 Alternate
20 Erase
this can not cancel that operation in progress. address and data, and begin erasing the block indicated on the address pins. Suspend commands and will output status register data when OE# is toggled low. Status register data is updated by toggling either OE# or CE# low.
70 Read Status
outputs status register data, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. This is one of the two commands that is executable while the WSM is operating.
Table 6. Command Codes and Descriptions (Continued)
50 Clear Status
90 Intelligent
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. Table 7. Command Bus Definitions
- Bus operations are defined in Tables 3 and 4.
- IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
- SRD - Data read from Status Register.
- IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
- BA = Address within the block being erased.
- PA = Address to be programmed. PD = Data to be programmed at location PA.
- Either 40H or 10H commands is valid.
- When writing commands to the device, the upper data bus [DQ
20 PRELIMINARY
Table 8. Status Register Bit Definition checking program or erase status bits.
- WSM has applied the max number of erase
- Erase Set-Up command was followed by a
command other than Erase Confirm.
- WSM has applied the max number of program
- Erase Set-Up command was followed by a
command other than Erase Confirm. be masked out when polling the status register.
before further attempts are allowed by the Write State Machine. where multiple bytes are programmed before full status is checked. retry or other error recovery. Repeat for subsequent word/byte program operations. program operation, or after a sequence of word/byte programs. Figure 8. Automated Word/Byte Program Flowchart
22 PRELIMINARY
attempts are allowed by the Write State Machine. cases where multiple blocks are erase before full status is checked. retry or other error recovery. Repeat for subsequent block erasures. Write FFH after the last operation to reset device to read array mode. Figure 9. Automated Block Erase Flowchart
Figure 10. Erase Suspend/Resume Flowchart
24 PRELIMINARY
3.3 Boot Block Locking
result in a error in the status register.
3.3.2 WP# = V IL FOR BOOT BLOCK
3.3.3 RP# = V HH OR WP# = VIH FOR BOOT
defines the write protection methods.
3.3.4 NOTE FOR 8-MBIT 44-PSOP
package combinations have WP# pins. Table 9. Write Protection Truth Table
4.0 DESIGN CONSIDERATIONS
robustness of system designs using flash memory.
4.1 Power Consumption
will detail how to take advantage of these features.
4.1.1 ACTIVE POWER
4.1.2 AUTOMATIC POWER SAVINGS (APS)
E 28F200B5, 28F004/400B5, 28F800B5 25PRELIMINARY
4.1.3 STANDBY POWER
When CE# is at a logic-high level (VIH), and the device is not programming or erasing, the memory enters in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ 0–DQ 15 or DQ0–DQ 7) are placed in a high-impedance state independent of the status of the OE# signal. When CE# is at logic- high level during program or erase operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
4.1.4 DEEP POWER-DOWN MODE
The 5 Volt Boot Block Flash family supports a low typical I CCD in deep power-down mode, which turns off all circuits to save power. This mode is activated by the RP# pin when it is at a logic-low (GND ± 0.2 V). Note: BYTE# pin must be at CMOS levels to meet the ICCD specification. During read modes, the RP# pin going low de- selects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of t PHQV . RP# transitions to VIL, or turning power off to the device will clear the status register. During an program or erase operation, RP# going low for time tPLPH will abort the operation, but the location’s memory contents will no longer valid and additional timing must be met. See Section 3.1.5 and Figure 15 and Table 10 for additional information.
4.2 Power-Up/Down Operation
The device protects against accidental block erasure or programming during power transitions. Power supply sequencing is not required, so either V PP or VCC can power-up first. The CUI defaults to the read mode after power-up, but the system must drop CE# low or present an address to receive valid data at the outputs. A system designer must guard against spurious writes when V CC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. Additionally, alteration of memory can only occur after successful completion of a two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
4.2.1 RP# CONNECTED TO SYSTEM
Using RP# properly during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may in a mode other than Read Array. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU.
4.3 Board Design
4.3.1 POWER SUPPLY DECOUPLING
Flash memory’s switching characteristics require careful decoupling methods. System designers should consider three supply current issues: standby current levels (I CCS ), active current levels (ICCR ), and transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between V CC and GND, and between V PP and GND. These high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 4.3.2 V PP TRACE ON PRINTED CIRCUIT BOARDS In-system updates to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. Since the VPP pin supplies the current for programming and erasing, it should have similar trace widths and layout considerations as given to the V CC power supply trace. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
28F200B5, 28F004/400B5, 28F800B5 E
26 PRELIMINARY
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings*
Commercial Operating Temperature Extended Operating Temperature During Read/Erase/Program.. –40 °C to +85 °C Automotive Operating Temperature During Read/Erase/Program –40 °C to +125 °C Voltage on Any Pin (except V CC , VPP , A9 and RP#) Voltage on Pin RP# or Pin A9 VPP Program Voltage with Respect to GND during Block Erase and Word/Byte Program .. –2.0 V to +14.0 V(2,3) VCC Supply Voltage NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is V CC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. Maximum DC voltage on RP# or A9 may overshoot to 13.5 V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time.
5.2 Operating Conditions
Symbol Parameter Notes Min Max Units TA Commercial Operating Temperature 0 +70 °C Extended Operating Temperature –40 +85 °C Automotive Operating Temperature –40 +125 °C VCC 5 V VCC Supply Voltage (10%) 1 4.50 5.50 Volts 5 V VCC Supply Voltage (5%) 2 4.75 5.25 Volts VPP 5 V VPP Supply Voltage (10%) 1 4.50 5.50 Volts 12 V VCC Supply Voltage (5%) 1 11.4 12.6 Volts NOTES: 1. 10% V CC specifications apply to the standard test configuration (Figures 12 and 13). 2. 5% V CC specifications apply to the high-speed test configuration (Figures 11 and 13).
E 28F200B5, 28F004/400B5, 28F800B5 27PRELIMINARY
5.3 Capacitance
TA = 25 °C, f = 1 MHz Symbol Parameter Note Typ Max Unit Conditions C IN Input Capacitance 4 6 8 pF V IN = 0 V C OUT Output Capacitance 4, 7 10 12 pF V OUT = 0 V 1. Sampled, not 100% tested.
5.4 DC Characteristics—Commercial and Extended Temperature
Sym Parameter Note Typ Max Typ Max Unit Test Condition IIL Input Load Current 1 ±1.0 ±1.0 µA V CC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ± 10 ± 10 µA V CC = VCC Max, VIN = VCC or GND ICCS VCC Standby Current 1,3 2.0 2.5 mA VCC = VCC Max, CE# = RP# = BYTE# = WP# = VIH 130 150 µA VCC = VCC Max CE# = RP# = VCC ± 0.2 V ICCD VCC Deep Power-Down Current 12 0 2 0 µ A V CC = VCC Max, VIN = VCC or GND RP# = GND ± 0.2 V ICCR VCC Read Current (Word or Byte Mode) 1,5, 60 65 mA CMOS INPUTS VCC = VCC Max, CE# = GND, OE# = VCC, f = 10 MHz (5 V), IOUT = 0 mA, Inputs=GND or VCC 65 70 mA TTL INPUTS VCC = VCC Max, CE# = VIL, OE# = VIH , f = 10 MHz (5 V), IOUT = 0 mA, Inputs = VIL or VIH ICCW VCC Program Current 1,4 50 50 mA V PP = VPPH 1 (at 5 V) (Word or Byte Mode) 45 45 mA VPP = VPPH 2 (at 12 V) ICCE VCC Erase Current 1,4 35 45 mA V PP = VPPH 1 (at 5 V) 30 40 mA V PP = VPPH 2 (at 12 V) ICCES VCC Erase Susp Current 1,2 10 12.0 mA CE# = V IH , Block Erase Suspend IPPS VPP Standby Current 1 ± 10 ± 15 µA V PP < VPPH 2 IPPD VPP Deep Power-Down Current 1 5.0 10 µA RP# = GND ± 0.2 V IPPR VPP Read Current 1 200 200 µA V PP ≥ VPPH 2
28F200B5, 28F004/400B5, 28F800B5 E
28 PRELIMINARY
5.4 DC Characteristics—Commercial and Extended Temperature (Continued)
Sym Parameter Note Typ Max Typ Max Unit Test Condition IPPW VPP Program Current 1,4 25 30 mA V PP = VPPH 1 (at 5 V) (Word or Byte Mode) 20 25 V PP = VPPH 2 (at 12 V) IPPE VPP Erase Current 1,4 20 25 mA V PP = VPPH 1 (at 5 V) 15 20 V PP = VPPH 2 (at 12 V) IPPES VPP Erase Susp Current 1 200 200 µA V PP = VPPH , Block Erase Suspend IRP# RP# Unlock Current 1,4 500 500 µA RP# = V HH (to unlock Boot Block) IID A9 Identifier Current 1,4 500 500 µA A 9 = VID Sym Parameter Note Min Max Unit Test Condition VID A9 Intelligent Identifier Voltage 11.4 12.6 V VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V V VOL Output Low Voltage 0.45 V V CC = VCC Min, IOL = 5.8 mA VOH 1 Output High Voltage (TTL) 2.4 V V CC = VCC Min, IOH = –2.5 mA VOH 2 Output High Voltage (CMOS) 0.85 x VCC VV CC = VCC Min, IOH = –2.5 mA VCC – 0.4V VV CC = VCC Min, IOH = –100 µA VPPLK VPP Lock-Out Voltage 3 0.0 1.5 V Complete Data Protection VPPH 1V PP (Prog/Erase Operations) 4.5 5.5 V V PP at 5 V VPPH 2V PP (Prog/Erase Operations) 11.4 12.6 V V PP at 12 V VLKO VCC Erase/Prog Lock Voltage 2.0 V VHH RP# Unlock Voltage 11.4 12.6 V Boot Block Program/Erase
E 28F200B5, 28F004/400B5, 28F800B5 29PRELIMINARY NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR . 3. Block erases and word/byte program operations are inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH 1 and VPPLK . 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to less than 1 mA typical, in static operation.
5.5 DC Characteristics—Automotive Temperature
Sym Parameter Notes Min Typ Max Unit Test Conditions IIL Input Load Current 1 ± 5.0 µA V CC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 10 µA V CC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 1,3 0.8 2.5 mA TTL VCC = VCC Max CE# = VIL f = 10 MHz IOUT = 0 mA Inputs = VIL or VIH 2, 4 Mbit 70 250 µA CMOS VCC = VCC Max CE# = VIL f = 10 MHz IOUT = 0 mA Inputs = VIL or VIH
8 Mbit 70 220 µA
2, 4 Mbit 1 0.2 105 µA V CC = VCC Max VIN = VCC or GND RP# = GND ± 0.2 V 8 Mbit 1 0.2 104.5 µA
28F200B5, 28F004/400B5, 28F800B5 E
30 PRELIMINARY
5.5 DC Characteristics—Automotive Temperature (Continued)
Sym Parameter Notes Min Typ Max Unit Test Conditions ICCR VCC Read Current for Word or Byte 1,5,6 55 70 mA TTL VCC = VCC Max CE# = VIL f = 10 MHz IOUT = 0 mA Inputs = VIL or VIH 50 70 mA CMOS VCC = VCC Max CE = VIL f = 10 MHz (5 V) 5 MHz (3.3 V) IOUT = 0 mA Inputs = GND ± 0.2 V or VCC ± 0.2 V ICCW VCC Program Current for Word or Byte 1,4 25 50 mA V PP = VPPH 1 (at 5 V) Program in Progress 20 45 mA V PP = VPPH 2 (at 12 V) Program in Progress ICCE VCC Erase Current 1,4 22 45 mA V PP = VPPH 1 (at 5 V) Block Erase in Progress 18 40 mA V PP = VPPH 2 (at 12 V) Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 5 12.0 mA CE# = V IH Block Erase Suspend VPP = VPPH 1 (at 5 V) IPPS VPP Standby Current 1 ± 5 ± 15 µA V PP ≤ VCC IPPD VPP Deep Power-Down Current 1 0.2 10 µA RP# = GND ± 0.2 V IPPR VPP Read Current 1 50 200 µA V PP >VCC IPPW VPP Program Current for Word or Byte 11 3 3 0 m A V PP = VPPH VPP = VPPH 1 (at 5 V) Program in Progress 82 5 m A V PP = VPPH VPP = VPPH 2 (at 12 V) Program in Progress
E 28F200B5, 28F004/400B5, 28F800B5 31PRELIMINARY Sym Parameter Notes Min Typ Max Unit Test Conditions IPPE VPP Erase Current 1 15 25 mA V PP = VPPH VPP = VPPH 1 (at 5 V) Block Erase in Progress 10 20 mA V PP = VPPH VPP = VPPH 2 (at 12 V) Block Erase in Progress IPPES VPP Erase Suspend Current 1 50 200 µA V PP = VPPH Block Erase Suspend in Progress IRP# RP# Boot Block Unlock Current 1,4 500 µA RP# = V HH VPP = 12 V IID A9 Intelligent Identifier Current 1,4 500 µA A 9 = VID VID A9 Intelligent Identifier Voltage 11.4 12.6 V VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC 0.5V V VOL Output Low Voltage (TTL)
0.45 V V CC = VCC Min
VPP = 12 V IOL = 5.8 mA VOH 1 Output High Voltage (TTL)
2.4 V V CC = VCC Min
IOH = –1.5 mA VOH 2 Output High Voltage (CMOS) VCC – 0.4 V VV CC = VCC Min IOH = –100 µA VPPLK VPP Lock-Out Voltage 3 0.0 1.5 V Complete Write Protection VPPH 1V PP (Program/Erase Operations) 4.5 5.5 V V PP at 5 V VPPH 2V PP (Program/Erase Operations) 11.4 12.6 V V PP at 12 V VLKO VCC Program/Erase Lock Voltage 2.0 V VHH RP# Unlock Voltage 11.4 12.6 V Boot Block Program/ Erase VPP = 12 V
32 PRELIMINARY
- All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all
product versions (packages and speeds).
- ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of
- Block erases and word/byte program operations are i nhibited when VPP = VPPLK , and not guaranteed in the range between
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces I
CCR to less than 1 mA typical, in static operation. Input rise and fall times (10% to 90%) <10 ns. Figure 11. High Speed Test Waveform (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 12. Standard Test Waveform
C L includes jig capacitance. Figure 13. Test Configuration
5 V Standard Test 100 580 390
5 V High-Speed Test 30 580 390
Figure 14. AC Waveform for Reset Operation Table 10. Reset Specifications(1)
- If RP# is tied to VCC , these specs are not applicable.
- These specifications are valid for all product versions
- If RP# is asserted while a program or block erase, is
not executing, the reset will complete within tPLPH .
- A reset time, tPHQV , is required after tPLRH until outputs
are valid. See Section 3.1.5 for detailed information.
28F200B5, 28F004/400B5, 28F800B5 E
34 PRELIMINARY
5.6 AC Characteristics—Read Operations—Commercial and Extended
# Sym Parameter V CC 5V ± 5%(4) 5V±10% (5) 5V± 10%(5) 5V± 10%(5) Unit Load 30 pF 100 pF 100 pF 100 pF Notes Min Max Min Max Min Max Min Max R1 tAVAV Read Cycle 2, 4 Mbit 7 55 70 80 80 ns Time 8 Mbit 70 80 90 90 ns R2 t AVQV Address to 2, 4 Mbit 7 55 70 80 80 ns Output Delay 8 Mbit 70 80 90 90 ns R3 t ELQV CE# to 2, 4 Mbit 2,7 55 70 80 80 ns Output Delay 8 Mbit 70 80 90 90 ns R4 tGLQV OE# to Output Delay 2 30 35 40 40 ns R5 tPHQV RP# to Output Delay 450 450 450 450 ns R6 tELQX CE# to Output in Low Z 3 0 0 0 0 ns R7 tGLQX OE# to Output in Low Z 3 0 0 0 0 ns R8 tEHQZ CE# to Output in High Z 3 20 20 20 25 ns R9 tGHQZ OE# to Output in High Z 3 20 20 20 25 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 30 0 0 0 n s NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to t CE –tOE after the falling edge of CE# without impact on tCE . 3. Sampled, but not 100% tested. 4. See Test Configuration (Figure 13), 5 V High-Speed Test component values. 5. See Test Configuration (Figure 13), 5 V Standard Test component values. 6. Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device is in deep power-down or powered down. 7. As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer to the 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update to determine the specific 28F200B5 –T/B60 material that is capable of 55 ns read access times. All other 28F200B5 T/B60 devices are capable of 60 ns read access times when V CC = 5 V ± 5% and 30 pF load.
E 28F200B5, 28F004/400B5, 28F800B5 35PRELIMINARY
5.7 AC Characteristics—Read Operations—Automotive Temperature
Speed –80 –90 # Sym Parameter Density V CC 5 V ± 10%(5) 5 V ± 10%(5) Unit Load 100 pF 100 pF Notes Min Max Min Max R1 t AVAV Read Cycle Time 2, 4 Mbit 80 n/a ns
8 Mbit 80 90 ns
R2 t AVQV Address to Output Delay 2, 4 Mbit 80 n/a ns R3 t ELQV CE# to Output Delay 2, 4 Mbit 2 80 n/a ns R4 t GLQV OE# to Output Delay 2 40 40 ns R5 t PHQV RP# to Output Delay 550 550 ns R6 t ELQX CE# to Output in Low Z 3 0 0 ns R7 t GLQX OE# to Output in Low Z 3 0 0 ns R8 t EHQZ CE# to Output in High Z 3 25 25 ns R9 t GHQZ OE# to Output in High Z 3 25 25 ns R10 t OH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 30 0 n s NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to t CE –tOE after the falling edge of CE# without impact on tCE . 3. Sampled, but not 100% tested. 4. See Test Configuration (Figure 13), 5 V High-Speed Test component values. 5. See Test Configuration (Figure 13), 5 V Standard Test component values. 6. Dynamic BYTE# switching between word and byte modes is not supported. Mode change s must be made when the device is in deep power-down or powered down. 7. As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer to the 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update to determine the specific 28F200B5 –T/B60 material that is capable of 55 ns read access times. All other 28F200B5 T/B60 devices are capable of 60 ns read access times when V CC = 5 V ± 5% and 30 pF load.
36 PRELIMINARY
Figure 15. AC Waveforms for Read Operations
5.8 Erase and Program Timings —Commercial and Extended Temperature
- All numbers are sampled, not 100% tested.
- Max erase times are specified under worst case conditions. The max erase times are tested at the same value
CC and VPP . See Note 3 for typical conditions.
- Typical conditions are 25 °C with VCC and VPP at the center of the specified voltage range. Production programming using
VCC = 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time.
- Contact your Intel representative for information regarding maximum byte/word write specifications.
- Max program times are guaranteed for the two parameter blocks and 96-KB main block only.
E 28F200B5, 28F004/400B5, 28F800B5 37PRELIMINARY
5.9 Erase and Program Timings —Automotive Temperature
VCC = 5 V ± 10% VPP 5 V ± 10% 12 V ± 5% Parameter Typ Max Typ Max Units Boot/Parameter Block Erase Time 0.6 7.8 0.34 4.0 s Main Block Erase Time 1.0 15.4 0.8 7.1 s Main Block Write Time (Byte Mode) 2.0 16.8 1.4 6.8 s Main Block Write Time (Word Mode) 1.3 8.4 0.9 3.4 s NOTES: 1. All numbers are sampled, not 100% tested. 2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of V CC and VPP . See Note 3 for typical conditions. 3. Typical conditions are 25 °C with VCC and VPP at the center of the specified voltage range. Production programming using VCC = 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time. 4. Contact your Intel representative for information regarding maximum byte/word write specifications. 5. Max program times are guaranteed for the two parameter blocks and 96-KB main block only.
28F200B5, 28F004/400B5, 28F800B5 E
38 PRELIMINARY
5.10 AC Characteristics—Write Operations—Commercial and Extended
# Sym Parameter Note Min Max Min Max Unit W1 t PHWL (tPHEL ) RP# High Recovery to WE# (CE#) Going Low 450 450 ns W2 t ELWL (tWLEL ) CE# (WE#) Setup to WE# (CE#) Going Low 00 n s W3 t WP Write Pulse Width 9 50 60 ns W4 t DVWH (tDVEH ) Data Setup to WE# (CE#) Going High 4 50 60 ns W5 t AVWH (tAVEH ) Address Setup to WE# (CE#) Going High 3 50 60 ns W6 t WHEH (tEHWH ) CE# (WE#) Hold from WE# (CE#) High 0 0 ns W7 t WHDX (tEHDX ) Data Hold from WE# (CE#) High 4 0 0 ns W8 t WHAX (tEHAX ) Address Hold from WE# (CE#) High 3 0 0 ns W9 t WPH Write Pulse Width High VCC = 5 V ± 5% 10 10 ns VCC = 5 V ± 10% 20 20 ns W10 t PHHWH (tPHHEH ) RP# V HH Setup to WE# (CE#) Going High 6,8 100 100 ns W11 t VPWH (tVPEH )V PP Setup to WE# (CE#) Going High 5,8 100 100 ns W12 t QVPH RP# VHH Hold from Valid SRD 6,8 0 0 ns W13 t QVVL VPP Hold from Valid SRD 5,8 0 0 ns W14 t PHBR Boot Block Lock Delay 7,8 100 100 ns NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics—Read-Only Operations. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1). 6. For boot block program/erase, RP# should be held at V HH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 9. Write pulse width (t WP ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . 10. Write pulse width high (tWPH ) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
E 28F200B5, 28F004/400B5, 28F800B5 39PRELIMINARY
5.11 AC Characteristics—Write Operations—Automotive Temperature
# Sym Parameter Note Min Max Min Max Unit W0 t AVAV Write Cycle Time 2,4 Mbit 80 n/a ns W1 t PHWL (tPHEL ) RP# High Recovery to WE# (CE#) Going Low 450 450 ns W2 t ELWL (tWLEL ) CE# (WE#) Setup to WE# (CE#) Going Low 00 n s W3 t WP Write Pulse Width 9 60 60 ns W4 t DVWH (tDVEH ) Data Setup to WE# (CE#) Going High 46 0 6 0 n s W5 t AVWH (tAVEH ) Address Setup to WE# (CE#) Going High 36 0 6 0 n s W6 t WHEH (tEHWH ) CE# (WE#) Hold from WE# (CE#) High 00 n s W7 t WHDX (tEHDX ) Data Hold from WE# (CE#) High 40 0 n s W8 t WHAX (tEHAX ) Address Hold from WE# (CE#) High 30 0 n s W9 t WPH Write Pulse Width High VCC = 5 V ± 5% 10 10 ns W10 t PHHWH (tPHHEH ) RP# V HH Setup to WE# (CE#) Going High 6,8 100 100 ns W11 t VPWH (tVPEH )V PP Setup to WE# (CE#) Going High 5,8 100 100 ns W12 t QVPH RP# VHH Hold from Valid SRD 6,8 0 0 ns W13 t QVVL VPP Hold from Valid SRD 5,8 0 0 ns W14 t PHBR Boot Block Lock Delay 7,8 100 100 ns NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics—Read-Only Operations. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1). 6. For boot block program/erase, RP# should be held at V HH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 9. Write pulse width (t WP ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . 10. Write pulse width high (tWPH ) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
40 PRELIMINARY
A. V CC power-up and standby. B. Write Program Set-Up or Erase Set-Up Command. C. Write valid address & data (if program operation) or Erase Confirm (if erase operation) command. D. Automated program or erase delay. E. Read status register data. F. Write Read Array command if write operations are completed. Figure 16. AC Waveforms for Write Operations
E 28F200B5, 28F004/400B5, 28F800B5 41PRELIMINARY
6.0 ORDERING INFORMATION
Operating Temperature/Package E = Comm.l Temp. TSOP TE = Ext. Temp. TSOP PA = Comm. Temp. 44-Lead PSOP TB = Ext. Temp. 44-Lead PSOP AB = Automotive Temp. 44-Lead PSOP Product line designator for all Intel® Flash products Access Speed (ns) Voltage Options (VPP /VCC ) 5 = 5 or 12 / 5) Density/Organization X00 = x8/x16 Selectable (X = 2, 4, 8) 00X = x8-only (X = 4) T = Top Blocking B = Bottom Blocking Architecture B = Boot Block VALID COMBINATIONS 40-Lead TSOP 44-Lead PSOP 48-Lead TSOP Commercial 2M PA28F200B5T60 E28F200B5T60 PA28F200B5B60 E28F200B5B60 PA28F200B5T80 E28F200B5T80 PA28F200B5B80 E28F200B5B80 4M E28F004B5T60 PA28F400B5T60 E28F400B5T60 E28F004B5B60 PA28F400B5B60 E28F400B5B60 E28F004B5T80 PA28F400B5T80 E28F400B5T80 E28F004B5B80 PA28F400B5B80 E28F400B5B80 8M PA28F800B5T70 E28F800B5T70 PA28F800B5B70 E28F800B5B70 PA28F800B5T90 E28F800B5T90 PA28F800B5B90 E28F800B5B90 Extended 2M TB28F200B5T80 TE28F200B5T80 TB28F200B5B80 TE28F200B5B80 4M TE28F004B5T80 TB28F400B5T80 TE28F400B5T80 TE28F004B5B80 TB28F400B5B80 TE28F400B5B80 8M TB28F800B5T90 TE28F800B5T90 TB28F800B5B90 TE28F800B5B90 Automotive 2M AB28F200B5T80 AB28F200B5B80 4M AB28F400B5T80 AB28F400B5B80 8M AB28F800B5T80 AB28F800B5B80 AB28F800B5T90 AB28F800B5B90
28F200B5, 28F004/400B5, 28F800B5 E
42 PRELIMINARY
7.0 ADDITIONAL INFORMATION
292194 AB-65 Migrating SmartVoltage Boot Block Flash Designs to 5 Volt Boot Block Flash
297862 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update Note 3 2-Mbit SmartVoltage Boot Block Flash Memory Family datasheet Note 3 4-Mbit SmartVoltage Boot Block Flash Memory Family datasheet Note 3 8-Mbit SmartVoltage Boot Block Flash Memory Family datasheet NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. These documents can be located at the Intel World Wide Web support site, http://www.intel.com/support/flash/memory
E 28F200B5, 28F004/400B5, 28F800B5 43PRELIMINARY APPENDIX A WRITE STATE MACHINE: CURRENT-NEXT STATE CHART Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (10/40H) Erase Setup (20H) Erase Confirm (D0H) Erase Susp. (B0H) Erase Resume (D0H) Read Status (70H) Clear Status (50H) Read ID (90H) Read Array “1” Array Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Program Setup “1” Status Program (Command Input = Data to be programmed) Program: Not Complete “0” Status Program Program: Complete “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase Setup “1” Status Erase Command Error Erase Erase Cmd. Error Erase Erase Command Error Erase Cmd. Error “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase: Not Complete “0” Status Erase Erase Susp. to Status Erase Erase: Complete “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase Suspend to Status “1” Status Erase Susp. to Array Res’d. Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Susp. to Array Res’d. Erase Suspend to Array “1” Array Erase Susp. to Array Res’d. Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Susp. to Array Res’d. Read Status “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Read Identifier “1” ID Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID
28F200B5, 28F004/400B5, 28F800B5 E
44 PRELIMINARY
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