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X9000 INTEL | Alldatasheet

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Technical content

Datasheet sections

• 1.1 Terminology
• 1.2 References
• 2 Low Power Features
• 2.1 Clock Control and Low-Power States
• 2.1.1 Core Low-Power State Descriptions
• 2.1.2 Package Low-Power State Descriptions
• 2.2 Enhanced Intel SpeedStep® Technology
• 2.3 Extended Low-Power States
• 2.4 FSB Low-Power Enhancements
• 2.4.1 Dynamic FSB Frequency Switching
• 2.4.2 Intel® Dynamic Acceleration Technology
• 2.5 VID-x
• 2.6 Processor Power Status Indicator (PSI-2) Signal
• 3 Electrical Specifications
• 3.1 Power and Ground Pins
• 3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
• 3.3 Voltage Identification
• 3.4 Catastrophic Thermal Protection
• 3.5 Reserved and Unused Pins
• 3.6 FSB Frequency Select Signals (BSEL[2:0])
• 3.7 FSB Signal Groups
• 3.8 CMOS Signals
• 3.9 Maximum Ratings
• 3.10 Processor DC Specifications
• 4 Package Mechanical Specific ations and Pin Information
• 4.1 Package Mechanical Specifications
• 4.2 Processor Pinout and Pin List
• 5 Thermal Specifications
• 5.1 Thermal Features
• 5.1.1 Thermal Diode
• 5.1.2 Intel® Thermal Monitor
• 5.1.3 Digital Thermal Sensor
• 5.2 Out of Specification Detection
• 5.3 PROCHOT# Signal Pin

Document Number: 318914-001 Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process for Platforms Based on Mobile Intel® 965 Express Chipset Family Datasheet January 2008

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. 45-nm products are manufactured on a lead-free process. Lead-free per EU RoHS directive July, 2006. Some E.U. RoHS exemptions may apply to other components used in the product package. Residual amounts of halogens are below November, 2007 proposed IPC/JEDEC J-STD-709 standards. This device is protected by U.S. patent numbers 5,315,448 and 6,516,132, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Devices incorporating Macrovision's copy protection technology can only be sold or distributed to companies appearing on Macrovision's list of “Authorized Buyers” at: www.macrovision.com. Reverse engineering or disassembly is prohibited. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others. Copyright © 2008, Intel Corporation. All rights reserved.

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Revision History

318914 -001 Initial release January 2008

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1 Introduction

The Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor built on 45- nanometer process technology are the next generation high-performance, low-power mobile processors based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo processor and Intel Core 2 Extreme processor support the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8 Controller Hub-Based Systems. The document contains electrical, mechanical and thermal specifications for the following processors:

• Intel Core 2 Duo processor - Standard Voltage
• Intel Core 2 Extreme processor Note: In this document, the Intel Core 2 Duo processor and Intel Core 2 Extreme mobile processor built on 45-nm process technology are referred to as the processor. The Mobile Intel® 965 Express Chipset family is referred to as the (G)MCH. The following list provides some of the key features on this processor:
• Dual-core processor for mobile with enhanced performance.
• Supports Intel® architecture with Intel® Wide Dynamic Execution.
• Supports L1 cache-to-cache (C2C) transfer.
• Supports PSI2 functionality.
• Supports Enhanced Intel® Virtualization Technology.
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each core.
• On-die, up to 6-MB second-level shar ed cache with Advanced Transfer Cache Architecture.
• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD Extensions 3 (SSSE3) and SSE4.1 Instruction Sets.
• 800-MHz Source-Synchronous front side bus (FSB).
• Advanced power management features including Enhanced Intel SpeedStep® Technology and Dynamic FSB frequency switching.
• Digital Thermal Sensor (DTS).
• Intel® 64 architecture.
• Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM).
• Micro-FCPGA and Micro-FCBGA packaging technologies (Extreme Edition only available in Micro-FCPGA).
• Execute Disable Bit support for enhanced security.
• Deep Power-Down Technology with P_LVL6 I/O Support.
• Half-ratio support (N/2) for Core-to-Bus ratio.

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1.1 Terminology

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel® processors. Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities to laptops. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non- executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel ® Architecture Software Developer's Manual for more detailed information. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). Half ratio support (N/2) for Core to Bus ratio Penryn processor support the N/2 feature which allows having fractional core to bus ratios. This feature provides the flexibility of having more frequency options and be able to have products with smaller frequency steps. Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture. Intel® Virtualization Technology Processor virtualization which, when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. TDP Thermal Design Power. V CC The processor core power supply. VSS The processor ground.

1.2 References

Intel® Core™2 Duo Mobile Proces sor and Intel® Core™2 Extreme Processor on 45-nm Technology Specification Update 318915 Mobile Intel® 965 Express Chipset Family Datasheet 316273 Mobile Intel® 965 Express Chipset Family Specification Update 316274 Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Datasheet See http://www.intel.com/ design/chipsets/datashts/ 313056.htm Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M) Specification Update See http://www.intel.com/ design/chipsets/specupdt/ 313057.htm Intel® 64 and IA-32 Architectures Software Developer’s Manual See http://www.intel.com/ design/pentium4/manuals/ index_new.htm Intel® 64 and IA-32 Architectures Software Developer's Manuals Documentation Change See http:// developer.intel.com/design/ processor/specupdt/ 252046.htm Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669

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2 Low Power Features

2.1 Clock Control and Low-Power States

The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel® Enhanced Deeper Sleep, and Intel Deep Power-Down low-power states. When both cores coincide in a common core low-power state, the central power management logic ensures the entire processor enters the respective package low-power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read to the (G)MCH. The processor implements two software interfaces for requesting low-power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model- specific register (MSR). If a core encounters a chipset break event while STPCLK# is asserted, it then asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to the system logic that individual cores should return to the C0 state and the processor should return to the Normal state. Figure 1 shows the core low-power states and Figure 2 shows the package low-power states for the processor. Table 1 maps the core low-power states to package low-power states.

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Figure 1. Core Low-Power States † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state. Ø — P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.

2.1.1 Core Low-Power State Descriptions

2.1.1.1 Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2 Core C1/AutoHALT Power-Down State

C1/AutoHALT is a low-power state entered when a core executes the HALT instruction. immediately initialize itself. return execution to the HALT state. Figure 2. Package Low-Power States Table 1. Coordination of Core Low- Power States at the Package Level

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While in AutoHALT power-down state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT power- down state.

2.1.1.3 Core C1/MWAIT Power-Down State

C1/MWAIT is a low-power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

2.1.1.4 Core C2 State

Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in the C2 state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5 Core C3 State

Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architecture in the C3 state. The monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual-core processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.

2.1.1.6 Core C4 State

Individual cores of the dual-core processor can enter the C4 state by initiating a P_LVL4 or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core behavior in the C4 state is nearly identical to the behavior in the C3 state. The only difference is that if both processor cores are in C4, the central power management logic will request that the entire processor enter the Deeper Sleep package low-power state (see Section 2.1.2.6). To enable the package-level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.2.6 for further details on Intel Enhanced Deeper Sleep state.

2.1.1.7 Core C6 State

C6 is a radical, new, power-saving state which is being implemented on this processor. In C6 the processor saves its entire architectural state onto an on-die SRAM, hence allowing it to run at a voltage V C6 that is lower than Enhanced Deeper Sleep voltage. An individual core of the dual-core processor can enter the C6 state by initiating a P_LVL6 I/O read to the P_BLK or an MWAIT(C6) instruction. The primary method to enter C6 used by newer operating systems (that support MWAIT) will be through the MWAIT instruction. When the core enters C6, it saves the processor state that is relevant to the processor context in an on-die SRAM that resides on a separate power plane V CCP (I/O power supply). This allows the main core VCC to be lowered to a very low-voltage VC6. The on- die storage for saving the processor state is implemented as a per-core SRAM. The microcode performs the save and restore of the processor state on entry and exit from C6, respectively.

2.1.2 Package Low-Power State Descriptions

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2 Stop-Grant State

When the STPCLK# pin is asserted, each core of the dual-core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low-power state. When the STPCLK# pin is deasserted, each core returns to its previous core low-power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC Specification T45. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP#, as per AC Specification T75. While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state. The PBE# signal may be driven when the processor is in the Stop-Grant state. PBE# will be asserted if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state. A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop occurs with the assertion of the SLP# signal.

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2.1.2.3 Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.

2.1.2.4 Sleep State

The Sleep state is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.

2.1.2.5 Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re- started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in the Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in the Deep Sleep state. When the processor is in the Deep Sleep state it will not respond to interrupts or snoop transactions.

Warning: Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.

2.1.2.6 Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels. One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state, which is a sub-state of the Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely reducing the L2 cache and entering the Intel Enhanced Deeper Sleep state. In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins. Refer to the platform design guides for further details. Exit from Deeper Sleep or the Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point.

2.1.2.6.1 Intel

® Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the L2 cache has been reduced to zero ways and completely shut down. The following events occur when the processor enters the Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4) instruction and then progressively reduces the L2 cache to zero.
• Once the L2 cache has been reduced to zero, the processor triggers a special chipset sequence to notify the chipset to redirect all FSB traffic, except APIC messages, to memory. The snoops are replied as misses by the chipset and are directed to main memory instead of the L2 cache. This allows for higher residency of the processor’s Intel Enhanced Deeper Sleep state.
• The processor drives the VID code corre sponding to the Intel Enhanced Deeper Sleep state core voltage on the VID[6:0] pins.

2.1.2.6.2 Intel ® Deep Power-Down State (Previously known as Package C6 State)

When both cores have entered the CC6 state and the L2 cache has been shrunk down to zero ways, the processor will enter the Intel Deep Power-Down state or C6 state. To do so both cores save their architectural states in the on-die SRAM that resides in the V CCP domain. At this point, the core VCC will be dropped to the lowest core voltage VC6. The processor is now in an extremely low-power state. In the Intel Deep Power-Down state, the processor does not need to be snooped, as all the caches are flushed before entering C6. C6 exit is triggered by the chipset when it detects a break event. It deasserts the DPRSTP#, DPSLP#, SLP#, and STPCLK# pins to exit the processor out of the C6 state. At DPSLP# deassertion, the core VCC ramps up to the LFM value and the processor starts up its internal PLLs. At SLP# deassertion the processor is reset and the architectural state is read back into the cores from an on-die SRAM. The restore will be done in both cores irrespective of the break event and which core it is directed to. The C6 exit event will put both cores in CC0. Refer to Figure 3 and Figure 4 for C6 entry sequence and exit sequence.

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2.1.2.6.3 Dynamic Cache Sizing

• The second core is already in C4 and Intel Enhanced Deeper Sleep state or C6 state is enabled (as specified in Section 2.1.1.6).
• The C0 timer that tracks continuous residency in the Normal package state has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold. If the FSB speed-to-processor core speed ratio is above the predefined L2 shrink threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing decisions.

Figure 3. C6 Entry Sequence Figure 4. C6 Exit Sequence

Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep state or C6 will expand the L2 cache to two ways and invalidate previously disabled cache ways. If the L2 cache reduction conditions stated above still exist when the last core returns to C4 and the package enters the Intel Enhanced Deeper Sleep state or C6, then the L2 will be shrunk to zero again. If a core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not the one currently entering the interrupt routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded upon the next interrupt event. In addition, the processor supports Full Shrink on L2 cache. When the MWAIT C6 instruction is executed with a hint=0x2 in ECX[3:0], the micro code will shrink all the active ways of the L2 cache in one step. This ensures that the package enters C6 immediately when both cores are in CC6 instead of iterating till the cache is reduced to zero. The operating system (OS) is expected to use this hint when it wants to enter the lowest power state and can tolerate the longer entry latency. L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not enter Intel Enhanced Deeper Sleep state or C6 since the L2 cache remains valid and in full size.

2.2 Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. The key features of Enhanced Intel SpeedStep Technology follow:

• Multiple voltage and frequency operating points provide optimal performance at the lowest power.
• Voltage and frequency selection is software controlled by writing to processor MSRs: — If the target frequency is higher than the current frequency, V CC is ramped up in steps by placing new values on the VID pins, and the PLL then locks to the new frequency. — If the target frequency is lower than th e current frequency, the PLL locks to the new frequency, and the VCC is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp ra tes internally to ensure glitch-free transitions.
• Low transition latency and large number of transitions possible per second: — Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping.

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• Improved Intel® Thermal Monitor mode: — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up-transition to the previous frequency and voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system-level thermal management.
• Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection — Intel® Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. — Dual-core thermal management synchronization. Each core in the dual processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage. The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic Acceleration Technology mode on select SKUS. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode.

2.3 Extended Low-Power States

Extended low-power states (C1E, C2E, C3E, C4E, C6E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package low-power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in low-power states. C6 is always enabled in the extended low-power state, as described above. Note: Long-term reliability cannot be assured unless all the extended low power states are enabled. The processor implements two software interfaces for requesting extended package low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring IA32_MISC_ENABLES MSR bits to automatically promote package low- power states to extended package low-power states.

Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the BIOS for the processor to remain within specification. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor. As processor technology changes, enabling the extended low-power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying to this guideline may affect the long-term reliability of the processor. Caution: Enhanced Intel SpeedStep Technology transitions are multi-step processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low-power states since processor clocks are not active in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and, upon exit, will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency. The transition to the lowest operating point or back to the original software requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.

2.4 FSB Low-Power Enhancements

The processor incorporates FSB low-power enhancements:

• Dynamic FSB Power-Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
• L o w V CCP (I/O termination voltage)
• Dynamic FSB frequency switching The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.

2.4.1 Dynamic FSB Frequency Switching

Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (SuperLFM). This feature is supported at FSB frequencies of 800-MHz on the Santa Rosa platform and does not entail a change in the external bus signal (BCLK) frequency. Instead, both the processor and (G)MCH internally lower their BCLK reference frequency to 50% of the externally visible frequency. Both the processor and (G)MCH maintain a virtual BCLK signal (“VBCLK”) that is aligned to the external BCLK,

22 Datasheet

but at half the frequency. After a downward shift, it would appear externally as if the bus is running with a 100-MHz base clock in all aspects except that the actual external BCLK remains at 200 MHz. The transition into Super LFM, a “down-shift,” is done following a handshake between the processor and (G)MCH. A similar handshake is used to indicate an “up-shift,” a change back to normal operating mode. Ensure this feature is enabled and supported in the BIOS.

2.4.2 Intel® Dynamic Acceleration Technology

The processor supports the Intel Dynamic Acceleration Technology mode. The Intel Dynamic Acceleration Technology feature allows one core of the processor to operate at a higher frequency point when the other core is inactive and the operating system requests increased performance. This higher frequency is called the “opportunistic frequency” and the maximum rated operating frequency is the “guaranteed frequency.” Note: Extreme Edition processors do not support Intel Dynamic Acceleration Technology. Intel Dynamic Acceleration Technology mode enabling requires:

• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state
• Enhanced Multi-Threaded Thermal Management (EMTTM)
• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS. When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw an Instantaneous current (I CC_CORE_INST) for a short duration of tINST; however, the average ICC current will be “lesser then” or “equal” to ICCDES current specification. Please refer to the Processor DC Specifications section for more details.

2.5 VID-x

The processor implements the VID-x feature for improved control of core voltage levels when the processor enters a reduced power consumption state. VID-x applies only when the processor is in the Intel Dynamic Acceleration Technology performance state and one or more cores are in low-power state (i.e., CC3/CC4/CC6). VID-x provides the ability for the processor to request core voltage level reductions greater than one VID tick. The amount of VID tick reduction is fixed and only occurs while the processor is in the Intel Dynamic Acceleration Technology mode. This improved voltage regulator efficiency, during periods of reduced power consumption, allows for leakage reduction that results in platform power savings and extended battery life.

2.6 Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. For details, refer to the platform design guide for PSI-2. Functionality is expanded further to support three processor states when:

• Both cores are in idle state.
• Only one core is in active state.
• Both cores are in active state.

3 Electrical Specifications

3.1 Power and Ground Pins

determined by the VID (Voltage ID) pins.

3.2 FSB Clock (BCLK[1:0] ) and Processor Clocking

3.3 Voltage Identification

Table 2. Voltage Identification Definition (Sheet 1 of 4)

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Table 2. Voltage Identification Definition (Sheet 2 of 4)

Table 2. Voltage Identification Definition (Sheet 3 of 4)

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3.4 Catastrophic Thermal Protection

PWRGOOD signal is not asserted, and during package C6. Table 2. Voltage Identification Definition (Sheet 4 of 4)

3.5 Reserved and Unused Pins

processor and the location of all RSVD pins. internally and can be left as “No Connects”.

3.6 FSB Frequency Select Signals (BSEL[2:0])

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

3.7 FSB Signal Groups

(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 3. BSEL[2:0] Encoding for BCLK Frequency

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1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. In processor systems where there is no de bug port implemented on the system board,

implemented on the system board, these signals are no-connects.

1. BPM[2:1]# and PRDY# are AGTL+ output-only signals.
2. PROCHOT# signal type is open drain output and CMOS input.
3. On-die termination differs from other AGTL+ signals.

Table 4. FSB Pin Groups

3.8 CMOS Signals

3.9 Maximum Ratings

limits, functionality and long-term reliability can be expected.

1. For functional operation, all processor electr ical, signal quality, mechanical and thermal
2. Storage temperature is applic able to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias. functional operation, please refer to the processor case temperature specifications.

1. This rating applies to th e processor and does not include any tray or packaging.
2. Failure to adhere to this specification can affect the long term reliability of the processor.

Table 5. Processor Absolute Maximum Ratings

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3.10 Processor DC Specifications

processor are at TJ = 105°C. Read all notes associated with each parameter. Table 6. Voltage and Current Specifications for the Extreme Edition Processors (Sheet

1.2 GHz & VCCLFM

0.8 GHz & VCCSLFM

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

1. The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V CC.
2. Measured at the bulk capa citors on the motherboard.
3. V CC,BOOT tolerance shown in Figure 5 and Figure 6.
4. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
2. This is a steady-state I CC current specification, which is applicable when both VCCP and VCC_CORE are high.
3. Processor I CC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM
4. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
5. Intel Dynamic Acceleration Technology is not supported.

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Table 7. Voltage and Current Specificatio ns for the Dual-Core Standard Voltage

2.6 GHz & V

2.5 GHz & VCCHFM

2.4 GHz & VCCHFM

2.1 GHz & VCCHFM

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

1. The voltage specifications are as sumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. the system is not coupled in the scope probe.

1. Specified at the nominal V CC.
2. Measured at the bulk capa citors on the motherboard.
3. V CC,BOOT tolerance shown in Figure 5 and Figure 6.
4. Based on simulations and averaged over the durati on of any change in current. Specified by design/

characterization at nominal VCC. Not 100% tested.

1. This is a power-up peak current spec ification that is applicable when VCCP is high and VCC_CORE is low.
2. This is a steady-state I cc current specification that is applicable when both VCCP and VCC_CORE are high.
3. Processor I CC requirements in Intel Dynamic Acceleration Technology mode is lesser than ICC in HFM
4. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
5. Instantaneous current I CC_CORE_INST of 55 A has to be sustained for short time (tINST) of 10 µs. Average

current levels described herein. Figure 5. Active V CC and ICC Loadline Standard Voltage and Extreme Edition Processors Differential Remote Sense required.

34 Datasheet

NOTE: Deeper Sleep mode tolerance depends on VID value.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltag e where rising edge of BCLK0 is equal to the
3. For V in between 0 V and VIH.
4. Cpad includes die capacitance only. No package parasitics are included.
5. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
6. Measurement taken from differential waveform.
7. Measurement taken from single-ended waveform.
8. Only applies to the differe ntial rising edge (Clock rising and Clock# falling).

Figure 6. Deeper Sleep V CC and ICC Loadline Standard Voltage and Extreme Edition Differential Remote Sense required. Table 8. FSB Differential BCLK Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as
3. V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as
4. V IH and VOH may experience excursions above VCCP. However, input signal drivers must

comply with the signal quality specifications.

1. This is the pull-down driver resistance. Refer to processor I/O Buffer Models for I/V

RON (max) = 0.51*RTT. RTT typical value of 55 Ω is used for RON typ/min/max calculations.

1. GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The VCCP

referred to in these specifications is the instantaneous VCCP.

1. R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver.

models for I/V characteristics.

1. Specified with on die R TT and RON are turned off. Vin between 0 and VCCP.
2. Cpad includes die capaci tance only. No package parasitics are included.
3. This is the external re sistor on the comp pins.
4. On-die termination resist ance, measured at 0.33*VCCP.
5. Applies to Signals A[35:3].
6. Applies to Si gnals D[63:0].
7. Applies to Signals BPRI#,DEFER#,PREQ#, RESET#, RS[2:0]#, TRDY#, ADS#, BNR#,

ADSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#. Table 9. AGTL+ Signal Group DC Specifications

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1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V CCP referred to in these specifications refers to instantaneous VCCP.
3. Refer to the processor I/O Buffe r Models for I/V characteristics.
4. For V in between 0 V and VCCP. Measured when the driver is tristated.z
5. Cpad1 includes die capacitance only fo r DPRSTP#, DPSLP#, PWRGOOD. No package
6. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are
7. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

platform design guide for details.

1. For V in between 0 V and VOH.
2. Cpad includes die capacitance only. No package parasitics are included.

Table 10. CMOS Signal Group DC Specifications Table 11. Open Drain Signal Group DC Specifications

Package Mechanical Specifications and Pin Information

4 Package Mechanical

4.1 Package Mechanical Specifications

The processor is available in 6-MB and 3-MB, 478-pin Micro-FCPGA packages as well as 6-MB and 3-MB, 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7 through Figure 10. The mechanical package pressure specifications are in a direction normal to the surface of the processor. This requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under tilt, stack-up tolerances and other similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor. Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel’s BGA packages so as to not impact solder joint reliability after reflow. This load limit ensures that impact to the package solder joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric should be used in parallel with the 689 kPa (100 psi) pressure limit as long as neither limits are exceeded. In some cases, designing to 15-lbf will exceed the pressure specification of 689 kPa (100 psi) and therefore should be reduced to ensure both limits are maintained. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the thermal or mechanical solution. Refer to the Santa Rosa Platform Mechanical Design Guide for details. Caution: The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors are electrically conductive so care should be taken to avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors and possibly damage the device or render it inactive.

38 Datasheet

Figure 7. 6-MB and 3-MB on 6-MB Die Micr o-FCPGA Processor Package Drawing (Sheet

0.65 MAX

Figure 8. 6-MB and 3-MB on 6-MB Die Micr o-FCPGA Processor Package Drawing (Sheet

1.5 MAX ALLOWABLE

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Figure 9. 6-MB and 3-MB on 6-MB Die Micr o-FCBGA Processor Package Drawing (Sheet

Figure 10. 6-MB and 3-MB on 6-MB die Micr o-FCBGA Processor Package Drawing (Sheet

0.55 MAX ALLOWABLE

42 Datasheet

Figure 11. 3-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

Figure 12. 3-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

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Figure 13. 3-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)

Figure 14. 3-MB Micro-FC BGA Processor Package Drawing (Sheet 2 of 2)

46 Datasheet

4.2 Processor Pinout and Pin List

package. Table 12 provides the pin list, arranged numerically by pin number.

1. Keying option for µFCPGA, A1 and B1 are depopulated.
2. Keying option for µFCBGA, A1 is depopulated and B1 is VSS.

Figure 15. Processor Pinout (Top Package View, Left Side)

Figure 16. Processor Pinout (T op Package View, Right Side)

Table 12. Pin Listing by Pin Name

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Table 13. Pin Listing by Pin

56 Datasheet

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Table 14. Signal Descript ion (Sheet 1 of 8) are sampled before RESET# is deasserted. output Write bus transaction. reply ID match operations associated with the new transaction. outputs and latch their inputs. stall, the current bus owner cannot issue any new transactions. performance monitoring tools. Guide for UP and DP Platforms for detailed information.

the FSB. It must connect the appropriate pins of both FSB agents. the bus by deasserting BPRI#. synthesizer. All agents must operate at the same frequency. precision (1% tolerance) resistors. indicate a valid data transfer. group is inverted and therefore sampled active high. connect in the system. DBR# is not a processor signal. Table 14. Signal Description (Sheet 2 of 8)

64 Datasheet

connect the appropriate pins on both FSB agents. within the covered group, would change level in the next cycle. deasserted. DPRSTP# is driven by the ICH8M chipset. clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Table 14. Signal Descript ion (Sheet 3 of 8)

Data strobe used to latch in D[63:0]#. when the processor detects an unmasked floating-point error. event, it will remain asserted until STPCLK# is deasserted. Instruction Application Note. GTLREF determines the signal reference level for AGTL+ input pins. receivers to determine if a signal is a Logical 0 or Logical 1. can be continued by reasserting HIT# and HITM# together. Table 14. Signal Description (Sheet 4 of 8)

66 Datasheet

no effect when the NE bit in Control Register 0 (CR0) is set. output Write bus transaction. connect the appropriate pins of both FSB agents. RESET#, then the processor executes its Built-in Self-Test (BIST). Pentium processor. Both signals are asynchronous. Table 14. Signal Descript ion (Sheet 5 of 8)

processor has reached its maximum safe operating temperature. active until the system deasserts PROCHOT#. lower power states (Deep Sleep and Deeper Sleep). stable before a subsequent rising edge of PWRGOOD. should be driven high throughout boundary scan operation. source synchronous to ADSTB[0]#. must connect the appropriate pins of both FSB agents. pins on the board be kept open for possible future use. Table 14. Signal Description (Sheet 6 of 8)

68 Datasheet

processor begins program execution from the SMM handler. processor will tristate its outputs. signals to all processor core units except the FSB and APIC units. clock; STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. THRMDA Other Thermal Diode Anode. THRMDC Other Thermal Diode Cathode. system by the THERMTRIP# (Thermal Trip) pin. Table 14. Signal Descript ion (Sheet 7 of 8)

must connect the appropriate pins of both FSB agents. must be driven low during power on Reset. VCC Input Processor core power supply. VSS Input Processor core ground node. VCCA Input V CCA provides isolated power for the internal processor core PLLs. VCCP Input Processor I/O Power Supply. Intel® MVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise. specification variations. See Table 2 for definitions of these pins. should be used to sense ground near the silicon with little noise. Table 14. Signal Description (Sheet 8 of 8)

Package Mechanical Specifications and Pin Information

70 Datasheet

5 Thermal Specifications

1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
2. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is less than

Table 15. Power Specifications for the Extreme Edition Processor

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1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

1. Not 100% tested. These power specifications are determined by characterization of the
2. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

1. The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
2. Processor TDP requirements in Intel Dynamic Acceleration Technology mode is lesser than

Table 16. Power Specifications for Du al-Core Standard Voltage Processors

2.6 GHz & VCCHFM

0.8 GHz & VCCLFM

5.1 Thermal Features

limits as set forth in Section 5.1. damage to the processor and potentially other components in the system.

• T h e r m a l d i o d e
• Intel Thermal Monitor
• Digital thermal sensor Note: The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when the maximum specified processor junction temperature has been reached.

5.1.1 Thermal Diode

thermal sensor that is connected to the transistor. they have a part capable of reading the thermal diode in BJT model. processor model-specific register (MSR). Table 17 to Table 18 provide the diode interface and transistor model specifications. Table 17. Thermal Diode Interface

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1. Intel does not support or re commend operation of the thermal diode under reverse bias.
2. Characterized across a temperature range of 50-105°C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, nQ, represents the deviat ion from ideal transistor model behavior as

5.1.2 Intel® Thermal Monitor

the TCC is active continuously. internal die temperature reaches the maximum allowed value for operation. Table 18. Thermal Diode Parame ters using Transistor Model

active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. When TM2 is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced Multi Threaded Thermal Monitoring (EMTTM). EMTTM is a processor feature that enhances TM2 with a processor throttling algorithm known as Adaptive TM2. Adaptive TM2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the OS can request the processor to throttling to any point between Intel Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor. The Intel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 and TM2 be enabled on the processors. TM1, TM2 and EMTTM features are collectively referred to as adaptive thermal monitoring features. TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 will also activate to help cool down the processor. If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a TM2 period is active, there are two possible results: 1. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition-based target frequency, the processor load-based transition will be deferred until the TM2 event has been completed. 2. If the processor load-based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition-based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If Bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via Bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on/50% off; however, in on-demand mode the duty cycle can be On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.

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Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low- power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor junction temperature drops below the thermal trip point. If thermal monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3 In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.

5.1.3 Digital Thermal Sensor

The processor also contains an on-die digital thermal sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the thermal monitor. The DTS is only valid while the processor is in the normal operating state (the normal package level low-power state). Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below TJ,max. Catastrophic temperature conditions are detectable via an out of specification status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not ensured once the activation of the out of specification status bit is set. The DTS-relative temperature readout corresponds to the thermal monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications.

Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.

5.2 Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shutdown before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register, and it generates a thermal interrupt.

5.3 PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If TM1 or TM2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. Only a single PROCHOT# pin exists at a package level of the processor. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above TCC temperature trip point, and both cores will have their core clocks modulated. If TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state. It is important to note that Intel recommends both TM1 and TM2 to be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor cores will enter the lowest programmed TM2 performance state. It should be noted that force TM1 on TM2, enabled via BIOS, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1, TM2, and force TM1 on TM2 are all enabled, then the processor will still apply only TM2. PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. §